1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2022, Ovidiu Panait <ovpanait@gmail.com>
4  */
5 #include <common.h>
6 #include <cpu.h>
7 #include <dm.h>
8 #include <asm/cpuinfo.h>
9 #include <asm/global_data.h>
10 #include <asm/pvr.h>
11 
12 DECLARE_GLOBAL_DATA_PTR;
13 
14 #define update_cpuinfo_pvr(pvr, ci, name)					\
15 {										\
16 	u32 tmp = PVR_##name(pvr);						\
17 	if (ci != tmp)								\
18 		printf("PVR value for " #name " does not match static data!\n");\
19 	ci = tmp;								\
20 }
21 
microblaze_cpu_probe_all(void * ctx,struct event * event)22 static int microblaze_cpu_probe_all(void *ctx, struct event *event)
23 {
24 	int ret;
25 
26 	ret = cpu_probe_all();
27 	if (ret)
28 		return log_msg_ret("Microblaze cpus probe failed\n", ret);
29 
30 	return 0;
31 }
32 EVENT_SPY(EVT_DM_POST_INIT_F, microblaze_cpu_probe_all);
33 
microblaze_set_cpuinfo_pvr(struct microblaze_cpuinfo * ci)34 static void microblaze_set_cpuinfo_pvr(struct microblaze_cpuinfo *ci)
35 {
36 	u32 pvr[PVR_FULL_COUNT];
37 
38 	microblaze_get_all_pvrs(pvr);
39 
40 	update_cpuinfo_pvr(pvr, ci->icache_size, ICACHE_BYTE_SIZE);
41 	update_cpuinfo_pvr(pvr, ci->icache_line_length, ICACHE_LINE_LEN);
42 
43 	update_cpuinfo_pvr(pvr, ci->dcache_size, DCACHE_BYTE_SIZE);
44 	update_cpuinfo_pvr(pvr, ci->dcache_line_length, DCACHE_LINE_LEN);
45 
46 	update_cpuinfo_pvr(pvr, ci->use_mmu, USE_MMU);
47 	update_cpuinfo_pvr(pvr, ci->ver_code, VERSION);
48 	update_cpuinfo_pvr(pvr, ci->fpga_code, TARGET_FAMILY);
49 }
50 
microblaze_set_cpuinfo_static(struct udevice * dev,struct microblaze_cpuinfo * ci)51 static void microblaze_set_cpuinfo_static(struct udevice *dev,
52 					  struct microblaze_cpuinfo *ci)
53 {
54 	const char *hw_ver = CONFIG_XILINX_MICROBLAZE0_HW_VER;
55 	const char *fpga_family = CONFIG_XILINX_MICROBLAZE0_FPGA_FAMILY;
56 
57 	ci->icache_size = dev_read_u32_default(dev, "i-cache-size", 0);
58 	ci->icache_line_length = dev_read_u32_default(dev,
59 						"i-cache-line-size", 0);
60 
61 	ci->dcache_size = dev_read_u32_default(dev, "d-cache-size", 0);
62 	ci->dcache_line_length = dev_read_u32_default(dev,
63 						"d-cache-line-size", 0);
64 
65 	ci->cpu_freq = dev_read_u32_default(dev, "clock-frequency", 0);
66 	ci->addr_size = dev_read_u32_default(dev, "xlnx,addr-size", 32);
67 	ci->use_mmu = dev_read_u32_default(dev, "xlnx,use-mmu", 0);
68 
69 	ci->ver_code = microblaze_lookup_cpu_version_code(hw_ver);
70 	ci->fpga_code = microblaze_lookup_fpga_family_code(fpga_family);
71 }
72 
microblaze_cpu_probe(struct udevice * dev)73 static int microblaze_cpu_probe(struct udevice *dev)
74 {
75 	microblaze_set_cpuinfo_static(dev, gd_cpuinfo());
76 
77 	if (microblaze_cpu_has_pvr_full())
78 		microblaze_set_cpuinfo_pvr(gd_cpuinfo());
79 	else
80 		debug("No PVR support. Using only static CPU info.\n");
81 
82 	return 0;
83 }
84 
microblaze_cpu_get_desc(const struct udevice * dev,char * buf,int size)85 static int microblaze_cpu_get_desc(const struct udevice *dev, char *buf,
86 				   int size)
87 {
88 	struct microblaze_cpuinfo *ci = gd_cpuinfo();
89 	const char *cpu_ver, *fpga_family;
90 	u32 cpu_freq_mhz;
91 	int ret;
92 
93 	cpu_freq_mhz = ci->cpu_freq / 1000000;
94 	cpu_ver = microblaze_lookup_cpu_version_string(ci->ver_code);
95 	fpga_family = microblaze_lookup_fpga_family_string(ci->fpga_code);
96 
97 	ret = snprintf(buf, size,
98 		       "MicroBlaze @ %uMHz, Rev: %s, FPGA family: %s",
99 		       cpu_freq_mhz, cpu_ver, fpga_family);
100 	if (ret < 0)
101 		return ret;
102 
103 	return (ret >= size) ? -ENOSPC : 0;
104 }
105 
microblaze_cpu_get_info(const struct udevice * dev,struct cpu_info * info)106 static int microblaze_cpu_get_info(const struct udevice *dev,
107 				   struct cpu_info *info)
108 {
109 	struct microblaze_cpuinfo *ci = gd_cpuinfo();
110 
111 	info->cpu_freq = ci->cpu_freq;
112 	info->address_width = ci->addr_size;
113 
114 	if (ci->icache_size || ci->dcache_size)
115 		info->features |= BIT(CPU_FEAT_L1_CACHE);
116 
117 	if (ci->use_mmu)
118 		info->features |= BIT(CPU_FEAT_MMU);
119 
120 	return 0;
121 }
122 
microblaze_cpu_get_count(const struct udevice * dev)123 static int microblaze_cpu_get_count(const struct udevice *dev)
124 {
125 	return 1;
126 }
127 
128 static const struct cpu_ops microblaze_cpu_ops = {
129 	.get_desc	= microblaze_cpu_get_desc,
130 	.get_info	= microblaze_cpu_get_info,
131 	.get_count	= microblaze_cpu_get_count,
132 };
133 
134 static const struct udevice_id microblaze_cpu_ids[] = {
135 	{ .compatible = "xlnx,microblaze-11.0" },
136 	{ .compatible = "xlnx,microblaze-10.0" },
137 	{ .compatible = "xlnx,microblaze-9.6" },
138 	{ .compatible = "xlnx,microblaze-9.5" },
139 	{ .compatible = "xlnx,microblaze-9.4" },
140 	{ .compatible = "xlnx,microblaze-9.3" },
141 	{ .compatible = "xlnx,microblaze-9.2" },
142 	{ .compatible = "xlnx,microblaze-9.1" },
143 	{ .compatible = "xlnx,microblaze-9.0" },
144 	{ .compatible = "xlnx,microblaze-8.50.c" },
145 	{ .compatible = "xlnx,microblaze-8.50.b" },
146 	{ .compatible = "xlnx,microblaze-8.50.a" },
147 	{ .compatible = "xlnx,microblaze-8.40.b" },
148 	{ .compatible = "xlnx,microblaze-8.40.a" },
149 	{ .compatible = "xlnx,microblaze-8.30.a" },
150 	{ .compatible = "xlnx,microblaze-8.20.b" },
151 	{ .compatible = "xlnx,microblaze-8.20.a" },
152 	{ .compatible = "xlnx,microblaze-8.10.a" },
153 	{ .compatible = "xlnx,microblaze-8.00.b" },
154 	{ .compatible = "xlnx,microblaze-8.00.a" },
155 	{ .compatible = "xlnx,microblaze-7.30.b" },
156 	{ .compatible = "xlnx,microblaze-7.30.a" },
157 	{ .compatible = "xlnx,microblaze-7.20.d" },
158 	{ .compatible = "xlnx,microblaze-7.20.c" },
159 	{ .compatible = "xlnx,microblaze-7.20.b" },
160 	{ .compatible = "xlnx,microblaze-7.20.a" },
161 	{ .compatible = "xlnx,microblaze-7.10.d" },
162 	{ .compatible = "xlnx,microblaze-7.10.c" },
163 	{ .compatible = "xlnx,microblaze-7.10.b" },
164 	{ .compatible = "xlnx,microblaze-7.10.a" },
165 	{ .compatible = "xlnx,microblaze-7.00.b" },
166 	{ .compatible = "xlnx,microblaze-7.00.a" },
167 	{ .compatible = "xlnx,microblaze-6.00.b" },
168 	{ .compatible = "xlnx,microblaze-6.00.a" },
169 	{ .compatible = "xlnx,microblaze-5.00.c" },
170 	{ .compatible = "xlnx,microblaze-5.00.b" },
171 	{ .compatible = "xlnx,microblaze-5.00.a" },
172 	{ }
173 };
174 
175 U_BOOT_DRIVER(microblaze_cpu) = {
176 	.name		= "microblaze_cpu",
177 	.id		= UCLASS_CPU,
178 	.of_match	= microblaze_cpu_ids,
179 	.probe		= microblaze_cpu_probe,
180 	.ops		= &microblaze_cpu_ops,
181 	.flags		= DM_FLAG_PRE_RELOC,
182 };
183