1config SYS_FSL_DDR 2 bool 3 help 4 Select Freescale General DDR driver, shared between most Freescale 5 PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based 6 Layerscape SoCs (such as ls2080a). 7 8config SYS_FSL_MMDC 9 bool 10 help 11 Select Freescale Multi Mode DDR controller (MMDC). 12 13config SYS_FSL_DDR_EMU 14 bool 15 help 16 Specify emulator support for DDR. Some DDR features such as deskew 17 training are not available. 18 19if SYS_FSL_DDR || SYS_FSL_MMDC 20 21config SYS_FSL_DDR_BE 22 bool 23 help 24 Access DDR registers in big-endian 25 26config SYS_FSL_DDR_LE 27 bool 28 help 29 Access DDR registers in little-endian 30 31config FSL_DDR_BIST 32 bool 33 34config FSL_DDR_INTERACTIVE 35 bool 36 37config FSL_DDR_SYNC_REFRESH 38 bool 39 40config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 41 bool 42 43config SYS_FSL_OTHER_DDR_NUM_CTRLS 44 bool 45 46menu "Freescale DDR controllers" 47 depends on SYS_FSL_DDR 48 49config SYS_NUM_DDR_CTLRS 50 int "Maximum DDR controllers" 51 default 3 if ARCH_LS2080A || \ 52 ARCH_T4240 53 default 2 if ARCH_B4860 || \ 54 ARCH_BSC9132 || \ 55 ARCH_P4080 || \ 56 ARCH_P5040 || \ 57 ARCH_LX2160A || \ 58 ARCH_LX2162A 59 default 1 60 61config CHIP_SELECTS_PER_CTRL 62 int "Number of chip selects per controller" 63 default 4 64 65config DIMM_SLOTS_PER_CTLR 66 int "Number of DIMM slots per controller" 67 default 1 68 69config SYS_FSL_DDR_MAIN_NUM_CTRLS 70 int "Number of controllers used as main memory" 71 default SYS_NUM_DDR_CTLRS 72 73config SYS_FSL_DDR_VER 74 int 75 default 50 if SYS_FSL_DDR_VER_50 76 default 47 if SYS_FSL_DDR_VER_47 77 default 46 if SYS_FSL_DDR_VER_46 78 default 44 if SYS_FSL_DDR_VER_44 79 80config SYS_FSL_DDR_VER_50 81 bool 82 83config SYS_FSL_DDR_VER_47 84 bool 85 86config SYS_FSL_DDR_VER_46 87 bool 88 89config SYS_FSL_DDR_VER_44 90 bool 91 92config SYS_FSL_DDRC_GEN1 93 bool 94 help 95 Enable Freescale DDR controller. 96 97config SYS_FSL_DDRC_GEN2 98 bool 99 depends on !MPC86xx 100 help 101 Enable Freescale DDR2 controller. 102 103config SYS_FSL_DDRC_GEN3 104 bool 105 depends on PPC 106 help 107 Enable Freescale DDR3 controller for PowerPC SoCs. 108 109config SYS_FSL_DDRC_ARM_GEN3 110 bool 111 depends on ARM 112 help 113 Enable Freescale DDR3 controller for ARM SoCs. 114 115config SYS_FSL_DDRC_GEN4 116 bool 117 help 118 Enable Freescale DDR4 controller. 119 120config SYS_FSL_HAS_DDR4 121 bool 122 123config SYS_FSL_HAS_DDR3 124 bool 125 126config SYS_FSL_HAS_DDR2 127 bool 128 129config SYS_FSL_HAS_DDR1 130 bool 131 132choice 133 prompt "DDR technology" 134 default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4 135 default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3 136 default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2 137 default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1 138 139config SYS_FSL_DDR4 140 bool "Freescale DDR4 controller" 141 depends on SYS_FSL_HAS_DDR4 142 imply DDR_SPD 143 select SYS_FSL_DDRC_GEN4 144 145config SYS_FSL_DDR3 146 bool "Freescale DDR3 controller" 147 depends on SYS_FSL_HAS_DDR3 148 imply DDR_SPD 149 select SYS_FSL_DDRC_GEN3 if PPC 150 select SYS_FSL_DDRC_ARM_GEN3 if ARM 151 152config SYS_FSL_DDR2 153 bool "Freescale DDR2 controller" 154 depends on SYS_FSL_HAS_DDR2 155 imply DDR_SPD 156 select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3) 157 158config SYS_FSL_DDR1 159 bool "Freescale DDR1 controller" 160 depends on SYS_FSL_HAS_DDR1 161 imply DDR_SPD 162 select SYS_FSL_DDRC_GEN1 163 164endchoice 165 166endmenu 167 168config FSL_DMA 169 def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER 170 171config DDR_ECC 172 bool "ECC DDR memory support" 173 174config DDR_ECC_CMD 175 bool "Access the ECC features of the memory controller" 176 depends on DDR_ECC && MPC83xx 177 default y 178 179config ECC_INIT_VIA_DDRCONTROLLER 180 bool "DDR Memory controller initializes memory." 181 help 182 Use the DDR controller to auto initialize memory. If not enabled, 183 the DMA controller is responsible for doing this. 184 185config SYS_DDR_RAW_TIMING 186 bool "Get DDR timing information from something other than SPD" 187 help 188 This is common with soldered DDR chips onboard without SPD. DDR raw 189 timing parameters are extracted from datasheet and hard-coded into 190 header files or board specific files. 191 192config SYS_FSL_DDR_INTLV_256B 193 bool "Enforce 256-byte interleave" 194 help 195 DDR controller interleaving on 256-byte. This is a special 196 interleaving mode, handled by Dickens for Freescale layerscape SoCs 197 with ARM core. 198 199endif 200 201menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)" 202 depends on MCF52x2 || MPC8xx || MPC83xx || MPC85xx 203 204config SYS_BR0_PRELIM_BOOL 205 bool "Define Bank 0" 206 207config SYS_BR0_PRELIM 208 hex "Preliminary value for BR0" 209 depends on SYS_BR0_PRELIM_BOOL 210 211config SYS_OR0_PRELIM 212 hex "Preliminary value for OR0" 213 depends on SYS_BR0_PRELIM_BOOL 214 215config SYS_BR1_PRELIM_BOOL 216 bool "Define Bank 1" 217 218config SYS_BR1_PRELIM 219 hex "Preliminary value for BR1" 220 depends on SYS_BR1_PRELIM_BOOL 221 222config SYS_OR1_PRELIM 223 hex "Preliminary value for OR1" 224 depends on SYS_BR1_PRELIM_BOOL 225 226config SYS_BR2_PRELIM_BOOL 227 bool "Define Bank 2" 228 229config SYS_BR2_PRELIM 230 hex "Preliminary value for BR2" 231 depends on SYS_BR2_PRELIM_BOOL 232 233config SYS_OR2_PRELIM 234 hex "Preliminary value for OR2" 235 depends on SYS_BR2_PRELIM_BOOL 236 237config SYS_BR3_PRELIM_BOOL 238 bool "Define Bank 3" 239 240config SYS_BR3_PRELIM 241 hex "Preliminary value for BR3" 242 depends on SYS_BR3_PRELIM_BOOL 243 244config SYS_OR3_PRELIM 245 hex "Preliminary value for OR3" 246 depends on SYS_BR3_PRELIM_BOOL 247 248config SYS_BR4_PRELIM_BOOL 249 bool "Define Bank 4" 250 251config SYS_BR4_PRELIM 252 hex "Preliminary value for BR4" 253 depends on SYS_BR4_PRELIM_BOOL 254 255config SYS_OR4_PRELIM 256 hex "Preliminary value for OR4" 257 depends on SYS_BR4_PRELIM_BOOL 258 259config SYS_BR5_PRELIM_BOOL 260 bool "Define Bank 5" 261 262config SYS_BR5_PRELIM 263 hex "Preliminary value for BR5" 264 depends on SYS_BR5_PRELIM_BOOL 265 266config SYS_OR5_PRELIM 267 hex "Preliminary value for OR5" 268 depends on SYS_BR5_PRELIM_BOOL 269 270config SYS_BR6_PRELIM_BOOL 271 bool "Define Bank 6" 272 273config SYS_BR6_PRELIM 274 hex "Preliminary value for BR6" 275 depends on SYS_BR6_PRELIM_BOOL 276 277config SYS_OR6_PRELIM 278 hex "Preliminary value for OR6" 279 depends on SYS_BR6_PRELIM_BOOL 280 281config SYS_BR7_PRELIM_BOOL 282 bool "Define Bank 7" 283 284config SYS_BR7_PRELIM 285 hex "Preliminary value for BR7" 286 depends on SYS_BR7_PRELIM_BOOL 287 288config SYS_OR7_PRELIM 289 hex "Preliminary value for OR7" 290 depends on SYS_BR7_PRELIM_BOOL 291endmenu 292 293if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB || TARGET_P1020RDB_PC || \ 294 TARGET_P1020RDB_PD || TARGET_P2020RDB 295 296config COMMON_INIT_DDR 297 bool "Do not have a TLB entry to cover common DDR init with serial presence detect (SPD)" 298 299config SPL_COMMON_INIT_DDR 300 bool "Do not have a TLB entry to cover common DDR init with SPD in SPL" 301 302config TPL_COMMON_INIT_DDR 303 bool "Do not have a TLB entry to cover common DDR init with SPD in TPL" 304 305endif 306 307config SYS_FSL_ERRATUM_A008378 308 bool 309 310config SYS_FSL_ERRATUM_A008109 311 bool 312 313config SYS_FSL_ERRATUM_A008511 314 bool 315 316config SYS_FSL_ERRATUM_A009663 317 bool 318 319config SYS_FSL_ERRATUM_A009801 320 bool 321 322config SYS_FSL_ERRATUM_A009803 323 bool 324 325config SYS_FSL_ERRATUM_A009942 326 bool 327 328config SYS_FSL_ERRATUM_A010165 329 bool 330 331config SYS_FSL_ERRATUM_NMG_DDR120 332 bool 333 334config SYS_FSL_ERRATUM_DDR_115 335 bool 336 337config SYS_FSL_ERRATUM_DDR111_DDR134 338 bool 339 340config SYS_FSL_ERRATUM_DDR_A003 341 bool 342 343config SYS_FSL_ERRATUM_DDR_A003474 344 bool 345