1menu "i.MX9 DDR controllers"
2	depends on ARCH_IMX9
3
4config IMX9_DRAM
5	bool "imx9 dram"
6	select IMX_SNPS_DDR_PHY
7
8config IMX9_LPDDR4X
9	bool "imx9 lpddr4 and lpddr4x"
10	select IMX9_DRAM
11	help
12	  Select the i.MX9 LPDDR4/4X driver support on i.MX9 SOC.
13
14config IMX9_DRAM_PM_COUNTER
15	bool "imx9 DDRC performance monitor counter"
16	default y
17	help
18	  Enable DDR controller performance monitor counter for reference events.
19
20config SAVED_DRAM_TIMING_BASE
21	hex "Define the base address for saved dram timing"
22	help
23	  after DRAM is trained, need to save the dram related timming
24	  info into memory for low power use.
25	default 0x2051C000
26
27endmenu
28