1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018 NXP
4 */
5
6 #include <common.h>
7 #include <binman_sym.h>
8 #include <log.h>
9 #include <spl.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <errno.h>
13 #include <asm/io.h>
14 #include <asm/arch/ddr.h>
15 #include <asm/arch/ddr.h>
16 #include <asm/sections.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 #define IMEM_LEN 32768 /* byte */
21 #define DMEM_LEN 16384 /* byte */
22 #define IMEM_2D_OFFSET 49152
23
24 #define IMEM_OFFSET_ADDR 0x00050000
25 #define DMEM_OFFSET_ADDR 0x00054000
26 #define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
27
28 binman_sym_declare(ulong, ddr_1d_imem_fw, image_pos);
29 binman_sym_declare(ulong, ddr_1d_imem_fw, size);
30
31 binman_sym_declare(ulong, ddr_1d_dmem_fw, image_pos);
32 binman_sym_declare(ulong, ddr_1d_dmem_fw, size);
33
34 #if !IS_ENABLED(CONFIG_IMX8M_DDR3L)
35 binman_sym_declare(ulong, ddr_2d_imem_fw, image_pos);
36 binman_sym_declare(ulong, ddr_2d_imem_fw, size);
37
38 binman_sym_declare(ulong, ddr_2d_dmem_fw, image_pos);
39 binman_sym_declare(ulong, ddr_2d_dmem_fw, size);
40 #endif
41
42 /* We need PHY iMEM PHY is 32KB padded */
ddr_load_train_firmware(enum fw_type type)43 void ddr_load_train_firmware(enum fw_type type)
44 {
45 u32 tmp32, i;
46 u32 error = 0;
47 unsigned long pr_to32, pr_from32;
48 uint32_t fw_offset = type ? IMEM_2D_OFFSET : 0;
49 unsigned long imem_start = (unsigned long)&_end + fw_offset;
50 unsigned long dmem_start;
51 unsigned long imem_len = IMEM_LEN, dmem_len = DMEM_LEN;
52
53 #ifdef CONFIG_SPL_OF_CONTROL
54 if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) {
55 imem_start = roundup((unsigned long)&_end +
56 fdt_totalsize(gd->fdt_blob), 4) +
57 fw_offset;
58 }
59 #endif
60
61 dmem_start = imem_start + imem_len;
62
63 if (BINMAN_SYMS_OK) {
64 switch (type) {
65 case FW_1D_IMAGE:
66 imem_start = binman_sym(ulong, ddr_1d_imem_fw, image_pos);
67 imem_len = binman_sym(ulong, ddr_1d_imem_fw, size);
68 dmem_start = binman_sym(ulong, ddr_1d_dmem_fw, image_pos);
69 dmem_len = binman_sym(ulong, ddr_1d_dmem_fw, size);
70 break;
71 case FW_2D_IMAGE:
72 #if !IS_ENABLED(CONFIG_IMX8M_DDR3L)
73 imem_start = binman_sym(ulong, ddr_2d_imem_fw, image_pos);
74 imem_len = binman_sym(ulong, ddr_2d_imem_fw, size);
75 dmem_start = binman_sym(ulong, ddr_2d_dmem_fw, image_pos);
76 dmem_len = binman_sym(ulong, ddr_2d_dmem_fw, size);
77 #endif
78 break;
79 }
80 }
81
82 pr_from32 = imem_start;
83 pr_to32 = IMEM_OFFSET_ADDR;
84 for (i = 0x0; i < imem_len; ) {
85 tmp32 = readl(pr_from32);
86 writew(tmp32 & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32));
87 pr_to32 += 1;
88 writew((tmp32 >> 16) & 0x0000ffff,
89 DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32));
90 pr_to32 += 1;
91 pr_from32 += 4;
92 i += 4;
93 }
94
95 pr_from32 = dmem_start;
96 pr_to32 = DMEM_OFFSET_ADDR;
97 for (i = 0x0; i < dmem_len; ) {
98 tmp32 = readl(pr_from32);
99 writew(tmp32 & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32));
100 pr_to32 += 1;
101 writew((tmp32 >> 16) & 0x0000ffff,
102 DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32));
103 pr_to32 += 1;
104 pr_from32 += 4;
105 i += 4;
106 }
107
108 debug("check ddr_pmu_train_imem code\n");
109 pr_from32 = imem_start;
110 pr_to32 = IMEM_OFFSET_ADDR;
111 for (i = 0x0; i < imem_len; ) {
112 tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff);
113 pr_to32 += 1;
114 tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR +
115 ddrphy_addr_remap(pr_to32)) & 0x0000ffff) << 16);
116
117 if (tmp32 != readl(pr_from32)) {
118 debug("%lx %lx\n", pr_from32, pr_to32);
119 error++;
120 }
121 pr_from32 += 4;
122 pr_to32 += 1;
123 i += 4;
124 }
125 if (error)
126 printf("check ddr_pmu_train_imem code fail=%d\n", error);
127 else
128 debug("check ddr_pmu_train_imem code pass\n");
129
130 debug("check ddr4_pmu_train_dmem code\n");
131 pr_from32 = dmem_start;
132 pr_to32 = DMEM_OFFSET_ADDR;
133 for (i = 0x0; i < dmem_len;) {
134 tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff);
135 pr_to32 += 1;
136 tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR +
137 ddrphy_addr_remap(pr_to32)) & 0x0000ffff) << 16);
138 if (tmp32 != readl(pr_from32)) {
139 debug("%lx %lx\n", pr_from32, pr_to32);
140 error++;
141 }
142 pr_from32 += 4;
143 pr_to32 += 1;
144 i += 4;
145 }
146
147 if (error)
148 printf("check ddr_pmu_train_dmem code fail=%d", error);
149 else
150 debug("check ddr_pmu_train_dmem code pass\n");
151 }
152
ddrphy_trained_csr_save(struct dram_cfg_param * ddrphy_csr,unsigned int num)153 void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr,
154 unsigned int num)
155 {
156 int i = 0;
157
158 /* enable the ddrphy apb */
159 dwc_ddrphy_apb_wr(0xd0000, 0x0);
160 dwc_ddrphy_apb_wr(0xc0080, 0x3);
161 for (i = 0; i < num; i++) {
162 ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg);
163 ddrphy_csr++;
164 }
165 /* disable the ddrphy apb */
166 dwc_ddrphy_apb_wr(0xc0080, 0x2);
167 dwc_ddrphy_apb_wr(0xd0000, 0x1);
168 }
169
dram_config_save(struct dram_timing_info * timing_info,unsigned long saved_timing_base)170 void *dram_config_save(struct dram_timing_info *timing_info, unsigned long saved_timing_base)
171 {
172 int i = 0;
173 struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base;
174 struct dram_cfg_param *cfg;
175
176 saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num;
177 saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num;
178 saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num;
179 saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num;
180
181 /* save the fsp table */
182 for (i = 0; i < 4; i++)
183 saved_timing->fsp_table[i] = timing_info->fsp_table[i];
184
185 cfg = (struct dram_cfg_param *)(saved_timing_base +
186 sizeof(*timing_info));
187
188 /* save ddrc config */
189 saved_timing->ddrc_cfg = cfg;
190 for (i = 0; i < timing_info->ddrc_cfg_num; i++) {
191 cfg->reg = timing_info->ddrc_cfg[i].reg;
192 cfg->val = timing_info->ddrc_cfg[i].val;
193 cfg++;
194 }
195
196 /* save ddrphy config */
197 saved_timing->ddrphy_cfg = cfg;
198 for (i = 0; i < timing_info->ddrphy_cfg_num; i++) {
199 cfg->reg = timing_info->ddrphy_cfg[i].reg;
200 cfg->val = timing_info->ddrphy_cfg[i].val;
201 cfg++;
202 }
203
204 /* save the ddrphy csr */
205 saved_timing->ddrphy_trained_csr = cfg;
206 for (i = 0; i < ddrphy_trained_csr_num; i++) {
207 cfg->reg = ddrphy_trained_csr[i].reg;
208 cfg->val = ddrphy_trained_csr[i].val;
209 cfg++;
210 }
211
212 /* save the ddrphy pie */
213 saved_timing->ddrphy_pie = cfg;
214 for (i = 0; i < timing_info->ddrphy_pie_num; i++) {
215 cfg->reg = timing_info->ddrphy_pie[i].reg;
216 cfg->val = timing_info->ddrphy_pie[i].val;
217 cfg++;
218 }
219
220 return (void *)cfg;
221 }
222