1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _DDR3_TRAINING_IP_H_ 7 #define _DDR3_TRAINING_IP_H_ 8 9 #include "ddr_topology_def.h" 10 11 #define TIP_ENG_LOCK 0x02000000 12 #define TIP_TX_DLL_RANGE_MAX 64 13 14 #define GET_MIN(arg1, arg2) ((arg1) < (arg2)) ? (arg1) : (arg2) 15 #define GET_MAX(arg1, arg2) ((arg1) < (arg2)) ? (arg2) : (arg1) 16 17 #define INIT_CONTROLLER_MASK_BIT 0x00000001 18 #define STATIC_LEVELING_MASK_BIT 0x00000002 19 #define SET_LOW_FREQ_MASK_BIT 0x00000004 20 #define LOAD_PATTERN_MASK_BIT 0x00000008 21 #define SET_MEDIUM_FREQ_MASK_BIT 0x00000010 22 #define WRITE_LEVELING_MASK_BIT 0x00000020 23 #define LOAD_PATTERN_2_MASK_BIT 0x00000040 24 #define READ_LEVELING_MASK_BIT 0x00000080 25 #define SW_READ_LEVELING_MASK_BIT 0x00000100 26 #define WRITE_LEVELING_SUPP_MASK_BIT 0x00000200 27 #define PBS_RX_MASK_BIT 0x00000400 28 #define PBS_TX_MASK_BIT 0x00000800 29 #define SET_TARGET_FREQ_MASK_BIT 0x00001000 30 #define ADJUST_DQS_MASK_BIT 0x00002000 31 #define WRITE_LEVELING_TF_MASK_BIT 0x00004000 32 #define LOAD_PATTERN_HIGH_MASK_BIT 0x00008000 33 #define READ_LEVELING_TF_MASK_BIT 0x00010000 34 #define WRITE_LEVELING_SUPP_TF_MASK_BIT 0x00020000 35 #define DM_PBS_TX_MASK_BIT 0x00040000 36 #define RL_DQS_BURST_MASK_BIT 0x00080000 37 #define CENTRALIZATION_RX_MASK_BIT 0x00100000 38 #define CENTRALIZATION_TX_MASK_BIT 0x00200000 39 #define TX_EMPHASIS_MASK_BIT 0x00400000 40 #define PER_BIT_READ_LEVELING_TF_MASK_BIT 0x00800000 41 #define VREF_CALIBRATION_MASK_BIT 0x01000000 42 #define WRITE_LEVELING_LF_MASK_BIT 0x02000000 43 44 /* DDR4 Specific Training Mask bits */ 45 #if defined (CONFIG_DDR4) 46 #define RECEIVER_CALIBRATION_MASK_BIT 0x04000000 47 #define WL_PHASE_CORRECTION_MASK_BIT 0x08000000 48 #define DQ_VREF_CALIBRATION_MASK_BIT 0x10000000 49 #define DQ_MAPPING_MASK_BIT 0x20000000 50 #define DM_TUNING_MASK_BIT 0x40000000 51 #endif /* CONFIG_DDR4 */ 52 53 enum hws_result { 54 TEST_FAILED = 0, 55 TEST_SUCCESS = 1, 56 NO_TEST_DONE = 2 57 }; 58 59 enum hws_training_result { 60 RESULT_PER_BIT, 61 RESULT_PER_BYTE 62 }; 63 64 enum auto_tune_stage { 65 INIT_CONTROLLER, 66 STATIC_LEVELING, 67 SET_LOW_FREQ, 68 LOAD_PATTERN, 69 SET_MEDIUM_FREQ, 70 WRITE_LEVELING, 71 LOAD_PATTERN_2, 72 READ_LEVELING, 73 #if defined(CONFIG_DDR4) 74 SW_READ_LEVELING, 75 #endif /* CONFIG_DDR4 */ 76 WRITE_LEVELING_SUPP, 77 PBS_RX, 78 PBS_TX, 79 SET_TARGET_FREQ, 80 ADJUST_DQS, 81 WRITE_LEVELING_TF, 82 READ_LEVELING_TF, 83 WRITE_LEVELING_SUPP_TF, 84 DM_PBS_TX, 85 VREF_CALIBRATION, 86 CENTRALIZATION_RX, 87 CENTRALIZATION_TX, 88 TX_EMPHASIS, 89 LOAD_PATTERN_HIGH, 90 PER_BIT_READ_LEVELING_TF, 91 #if defined(CONFIG_DDR4) 92 RECEIVER_CALIBRATION, 93 WL_PHASE_CORRECTION, 94 DQ_VREF_CALIBRATION, 95 DM_TUNING, 96 DQ_MAPPING, 97 #endif /* CONFIG_DDR4 */ 98 WRITE_LEVELING_LF, 99 MAX_STAGE_LIMIT 100 }; 101 102 enum hws_access_type { 103 ACCESS_TYPE_UNICAST = 0, 104 ACCESS_TYPE_MULTICAST = 1 105 }; 106 107 enum hws_algo_type { 108 ALGO_TYPE_DYNAMIC, 109 ALGO_TYPE_STATIC 110 }; 111 112 struct init_cntr_param { 113 int is_ctrl64_bit; 114 int do_mrs_phy; 115 int init_phy; 116 int msys_init; 117 }; 118 119 struct pattern_info { 120 u8 num_of_phases_tx; 121 u8 tx_burst_size; 122 u8 delay_between_bursts; 123 u8 num_of_phases_rx; 124 u32 start_addr; 125 u8 pattern_len; 126 }; 127 128 struct cs_element { 129 u8 cs_num; 130 u8 num_of_cs; 131 }; 132 133 struct hws_tip_freq_config_info { 134 u8 is_supported; 135 u8 bw_per_freq; 136 u8 rate_per_freq; 137 }; 138 139 struct hws_cs_config_info { 140 u32 cs_reg_value; 141 u32 cs_cbe_value; 142 }; 143 144 struct dfx_access { 145 u8 pipe; 146 u8 client; 147 }; 148 149 struct hws_xsb_info { 150 struct dfx_access *dfx_table; 151 }; 152 153 int ddr3_tip_register_dq_table(u32 dev_num, u32 *table); 154 int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable); 155 int hws_ddr3_tip_init_controller(u32 dev_num, 156 struct init_cntr_param *init_cntr_prm); 157 int hws_ddr3_tip_load_topology_map(u32 dev_num, 158 struct mv_ddr_topology_map *topology); 159 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type); 160 int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode); 161 u8 ddr3_tip_get_buf_min(u8 *buf_ptr); 162 u8 ddr3_tip_get_buf_max(u8 *buf_ptr); 163 #endif /* _DDR3_TRAINING_IP_H_ */ 164