1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _DDR3_TRAINING_IP_FLOW_H_ 7 #define _DDR3_TRAINING_IP_FLOW_H_ 8 9 #include "ddr3_training_ip.h" 10 #include "ddr3_training_ip_db.h" 11 #include "mv_ddr_plat.h" 12 13 #define KILLER_PATTERN_LENGTH 32 14 #define EXT_ACCESS_BURST_LENGTH 8 15 16 #define ECC_READ_BUS_0 0 17 #define ECC_PHY_ACCESS_3 3 18 #define ECC_PHY_ACCESS_4 4 19 #define ECC_PHY_ACCESS_8 8 20 #define BUS_WIDTH_IN_BITS 8 21 #define MAX_POLLING_ITERATIONS 1000000 22 #define ADLL_LENGTH 32 23 24 #define GP_RSVD0_REG 0x182e0 25 26 /* 27 * DFX address Space 28 * Table 2: DFX address space 29 * Address Bits Value Description 30 * [31 : 20] 0x? DFX base address bases PCIe mapping 31 * [19 : 15] 0...Number_of_client-1 Client Index inside pipe. 32 * See also Table 1 Multi_cast = 29 Broadcast = 28 33 * [14 : 13] 2'b01 Access to Client Internal Register 34 * [12 : 0] Client Internal Register offset See related Client Registers 35 * [14 : 13] 2'b00 Access to Ram Wrappers Internal Register 36 * [12 : 6] 0 Number_of_rams-1 Ram Index inside Client 37 * [5 : 0] Ram Wrapper Internal Register offset See related Ram Wrappers 38 * Registers 39 */ 40 41 /* nsec */ 42 #define AUTO_ZQC_TIMING 15384 43 44 enum mr_number { 45 MR_CMD0, 46 MR_CMD1, 47 MR_CMD2, 48 MR_CMD3, 49 #if defined(CONFIG_DDR4) 50 MR_CMD4, 51 MR_CMD5, 52 MR_CMD6, 53 #endif 54 MR_LAST 55 }; 56 57 struct mv_ddr_mr_data { 58 u32 cmd; 59 u32 reg_addr; 60 }; 61 62 struct write_supp_result { 63 enum hws_wl_supp stage; 64 int is_pup_fail; 65 }; 66 67 int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id, 68 enum mv_ddr_freq frequency, 69 u32 *round_trip_delay_arr); 70 int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id, 71 enum mv_ddr_freq frequency, 72 u32 *total_round_trip_delay_arr); 73 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access, 74 u32 if_id, u32 reg_addr, u32 data_value, u32 mask); 75 int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type, 76 u32 if_id, u32 exp_value, u32 mask, u32 offset, 77 u32 poll_tries); 78 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access, 79 u32 if_id, u32 reg_addr, u32 *data, u32 mask); 80 int ddr3_tip_bus_read_modify_write(u32 dev_num, 81 enum hws_access_type access_type, 82 u32 if_id, u32 phy_id, 83 enum hws_ddr_phy phy_type, 84 u32 reg_addr, u32 data_value, u32 reg_mask); 85 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access, 86 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, 87 u32 *data); 88 int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type e_interface_access, 89 u32 if_id, enum hws_access_type e_phy_access, u32 phy_id, 90 enum hws_ddr_phy e_phy_type, u32 reg_addr, 91 u32 data_value); 92 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id, 93 enum mv_ddr_freq memory_freq); 94 int ddr3_tip_adjust_dqs(u32 dev_num); 95 int ddr3_tip_init_controller(u32 dev_num); 96 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr, 97 u32 num_of_bursts, u32 *addr); 98 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr, 99 u32 num_of_bursts, u32 *addr); 100 int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 ui_freq); 101 int mv_ddr_rl_dqs_burst(u32 dev_num, u32 if_id, u32 freq); 102 int ddr3_tip_legacy_dynamic_read_leveling(u32 dev_num); 103 int ddr3_tip_dynamic_per_bit_read_leveling(u32 dev_num, u32 ui_freq); 104 int ddr3_tip_legacy_dynamic_write_leveling(u32 dev_num); 105 int ddr3_tip_dynamic_write_leveling(u32 dev_num, int phase_remove); 106 int ddr3_tip_dynamic_write_leveling_supp(u32 dev_num); 107 int ddr3_tip_static_init_controller(u32 dev_num); 108 int ddr3_tip_configure_phy(u32 dev_num); 109 int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type, 110 u32 if_id, enum hws_pattern pattern, 111 u32 load_addr); 112 int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern e_pattern); 113 int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type, 114 u32 if_id, enum hws_dir direction, u32 tx_phases, 115 u32 tx_burst_size, u32 rx_phases, 116 u32 delay_between_burst, u32 rd_mode, u32 cs_num, 117 u32 addr_stress_jump, u32 single_pattern); 118 int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask); 119 int ddr3_tip_write_cs_result(u32 dev_num, u32 offset); 120 int ddr3_tip_reset_fifo_ptr(u32 dev_num); 121 int ddr3_tip_read_adll_value(u32 dev_num, 122 u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], 123 u32 reg_addr, u32 mask); 124 int ddr3_tip_write_adll_value(u32 dev_num, 125 u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], 126 u32 reg_addr); 127 int ddr3_tip_tune_training_params(u32 dev_num, struct tune_train_params *params); 128 129 #endif /* _DDR3_TRAINING_IP_FLOW_H_ */ 130