1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) Marvell International Ltd. and its affiliates
4  */
5 
6 #ifndef _MV_DDR4_TRAINING_CALIBRATION_H
7 #define _MV_DDR4_TRAINING_CALIBRATION_H
8 
9 /* vref subphy calibration state */
10 enum mv_ddr4_vref_subphy_cal_state {
11 	MV_DDR4_VREF_SUBPHY_CAL_ABOVE,
12 	MV_DDR4_VREF_SUBPHY_CAL_UNDER,
13 	MV_DDR4_VREF_SUBPHY_CAL_INSIDE,
14 	MV_DDR4_VREF_SUBPHY_CAL_END
15 };
16 
17 /* calibrate DDR4 dq vref (tx) */
18 int mv_ddr4_dq_vref_calibration(u8 dev_num, u16 (*pbs_tap_factor)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS]);
19 
20 /* calibrate receiver (receiver duty cycle) */
21 int mv_ddr4_receiver_calibration(u8 dev_num);
22 
23 /* tune dm signal */
24 int mv_ddr4_dm_tuning(u32 cs, u16 (*pbs_tap_factor)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS]);
25 
26 #endif /* _MV_DDR4_TRAINING_CALIBRATION_H */
27