1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
5 * Keith Outwater, keith_outwater@mvis.com
6 *
7 * Copyright (c) 2019 SED Systems, a division of Calian Ltd.
8 */
9
10 /*
11 * Configuration support for Xilinx Virtex2 devices. Based
12 * on spartan2.c (Rich Ireland, rireland@enterasys.com).
13 */
14
15 #define LOG_CATEGORY UCLASS_FPGA
16
17 #include <common.h>
18 #include <console.h>
19 #include <log.h>
20 #include <virtex2.h>
21 #include <linux/delay.h>
22
23 /*
24 * If the SelectMap interface can be overrun by the processor, enable
25 * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CFG_FPGA_DELAY in the board
26 * configuration file and add board-specific support for checking BUSY status.
27 * By default, assume that the SelectMap interface cannot be overrun.
28 */
29
30 #ifndef CFG_FPGA_DELAY
31 #define CFG_FPGA_DELAY()
32 #endif
33
34 /*
35 * Check for errors during configuration by default
36 */
37 #ifndef CFG_SYS_FPGA_CHECK_ERROR
38 #define CFG_SYS_FPGA_CHECK_ERROR
39 #endif
40
41 /*
42 * The default timeout in mS for INIT_B to deassert after PROG_B has
43 * been deasserted. Per the latest Virtex II Handbook (page 347), the
44 * max time from PORG_B deassertion to INIT_B deassertion is 4uS per
45 * data frame for the XC2V8000. The XC2V8000 has 2860 data frames
46 * which yields 11.44 mS. So let's make it bigger in order to handle
47 * an XC2V1000, if anyone can ever get ahold of one.
48 */
49 #ifndef CFG_SYS_FPGA_WAIT_INIT
50 #define CFG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */
51 #endif
52
53 /*
54 * The default timeout for waiting for BUSY to deassert during configuration.
55 * This is normally not necessary since for most reasonable configuration
56 * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
57 */
58 #ifndef CFG_SYS_FPGA_WAIT_BUSY
59 #define CFG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/
60 #endif
61
62 /* Default timeout for waiting for FPGA to enter operational mode after
63 * configuration data has been written.
64 */
65 #ifndef CFG_SYS_FPGA_WAIT_CONFIG
66 #define CFG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */
67 #endif
68
69 static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
70 static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
71
72 static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
73 static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
74
virtex2_load(xilinx_desc * desc,const void * buf,size_t bsize,bitstream_type bstype,int flags)75 static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
76 bitstream_type bstype, int flags)
77 {
78 int ret_val = FPGA_FAIL;
79
80 switch (desc->iface) {
81 case slave_serial:
82 log_debug("Launching Slave Serial Load\n");
83 ret_val = virtex2_ss_load(desc, buf, bsize);
84 break;
85
86 case slave_selectmap:
87 log_debug("Launching Slave Parallel Load\n");
88 ret_val = virtex2_ssm_load(desc, buf, bsize);
89 break;
90
91 default:
92 printf("%s: Unsupported interface type, %d\n",
93 __func__, desc->iface);
94 }
95 return ret_val;
96 }
97
virtex2_dump(xilinx_desc * desc,const void * buf,size_t bsize)98 static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
99 {
100 int ret_val = FPGA_FAIL;
101
102 switch (desc->iface) {
103 case slave_serial:
104 log_debug("Launching Slave Serial Dump\n");
105 ret_val = virtex2_ss_dump(desc, buf, bsize);
106 break;
107
108 case slave_parallel:
109 log_debug("Launching Slave Parallel Dump\n");
110 ret_val = virtex2_ssm_dump(desc, buf, bsize);
111 break;
112
113 default:
114 printf("%s: Unsupported interface type, %d\n",
115 __func__, desc->iface);
116 }
117 return ret_val;
118 }
119
virtex2_info(xilinx_desc * desc)120 static int virtex2_info(xilinx_desc *desc)
121 {
122 return FPGA_SUCCESS;
123 }
124
125 /*
126 * Virtex-II Slave SelectMap or Serial configuration loader. Configuration
127 * is as follows:
128 * 1. Set the FPGA's PROG_B line low.
129 * 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high.
130 * 3. Write data to the SelectMap port. If INIT_B goes low at any time
131 * this process, a configuration error (most likely CRC failure) has
132 * ocurred. At this point a status word may be read from the
133 * SelectMap interface to determine the source of the problem (You
134 * could, for instance, put this in your 'abort' function handler).
135 * 4. After all data has been written, test the state of the FPGA
136 * INIT_B and DONE lines. If both are high, configuration has
137 * succeeded. Congratulations!
138 */
virtex2_slave_pre(xilinx_virtex2_slave_fns * fn,int cookie)139 static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
140 {
141 unsigned long ts;
142
143 log_debug("Start with interface functions @ 0x%p\n", fn);
144
145 if (!fn) {
146 printf("%s:%d: NULL Interface function table!\n",
147 __func__, __LINE__);
148 return FPGA_FAIL;
149 }
150
151 /* Gotta split this one up (so the stack won't blow??) */
152 log_debug("Function Table:\n"
153 " base 0x%p\n"
154 " struct 0x%p\n"
155 " pre 0x%p\n"
156 " prog 0x%p\n"
157 " init 0x%p\n"
158 " error 0x%p\n",
159 &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
160 log_debug(" clock 0x%p\n"
161 " cs 0x%p\n"
162 " write 0x%p\n"
163 " rdata 0x%p\n"
164 " wdata 0x%p\n"
165 " busy 0x%p\n"
166 " abort 0x%p\n"
167 " post 0x%p\n\n",
168 fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
169 fn->busy, fn->abort, fn->post);
170
171 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
172 printf("Initializing FPGA Device %d...\n", cookie);
173 #endif
174 /*
175 * Run the pre configuration function if there is one.
176 */
177 if (*fn->pre)
178 (*fn->pre)(cookie);
179
180 /*
181 * Assert the program line. The minimum pulse width for
182 * Virtex II devices is 300 nS (Tprogram parameter in datasheet).
183 * There is no maximum value for the pulse width. Check to make
184 * sure that INIT_B goes low after assertion of PROG_B
185 */
186 (*fn->pgm)(true, true, cookie);
187 udelay(10);
188 ts = get_timer(0);
189 do {
190 if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
191 printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
192 __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
193 (*fn->abort)(cookie);
194 return FPGA_FAIL;
195 }
196 } while (!(*fn->init)(cookie));
197
198 (*fn->pgm)(false, true, cookie);
199 CFG_FPGA_DELAY();
200 if (fn->clk)
201 (*fn->clk)(true, true, cookie);
202
203 /*
204 * Start a timer and wait for INIT_B to go high
205 */
206 ts = get_timer(0);
207 do {
208 CFG_FPGA_DELAY();
209 if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
210 printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
211 __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
212 (*fn->abort)(cookie);
213 return FPGA_FAIL;
214 }
215 } while ((*fn->init)(cookie) && (*fn->busy)(cookie));
216
217 if (fn->wr)
218 (*fn->wr)(true, true, cookie);
219 if (fn->cs)
220 (*fn->cs)(true, true, cookie);
221
222 mdelay(10);
223 return FPGA_SUCCESS;
224 }
225
virtex2_slave_post(xilinx_virtex2_slave_fns * fn,int cookie)226 static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
227 int cookie)
228 {
229 int ret_val = FPGA_SUCCESS;
230 int num_done = 0;
231 unsigned long ts;
232
233 /*
234 * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
235 */
236 CFG_FPGA_DELAY();
237 if (fn->cs)
238 (*fn->cs)(false, true, cookie);
239 if (fn->wr)
240 (*fn->wr)(false, true, cookie);
241
242 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
243 putc('\n');
244 #endif
245
246 /*
247 * Check for successful configuration. FPGA INIT_B and DONE
248 * should both be high upon successful configuration. Continue pulsing
249 * clock with data set to all ones until DONE is asserted and for 8
250 * clock cycles afterwards.
251 */
252 ts = get_timer(0);
253 while (true) {
254 if ((*fn->done)(cookie) == FPGA_SUCCESS &&
255 !((*fn->init)(cookie))) {
256 if (num_done++ >= 8)
257 break;
258 }
259
260 if (get_timer(ts) > CFG_SYS_FPGA_WAIT_CONFIG) {
261 printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
262 __func__, __LINE__, CFG_SYS_FPGA_WAIT_CONFIG);
263 (*fn->abort)(cookie);
264 ret_val = FPGA_FAIL;
265 break;
266 }
267 if (fn->wbulkdata) {
268 unsigned char dummy = 0xff;
269 (*fn->wbulkdata)(&dummy, 1, true, cookie);
270 } else {
271 (*fn->wdata)(0xff, true, cookie);
272 CFG_FPGA_DELAY();
273 (*fn->clk)(false, true, cookie);
274 CFG_FPGA_DELAY();
275 (*fn->clk)(true, true, cookie);
276 }
277 }
278
279 if (ret_val == FPGA_SUCCESS) {
280 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
281 printf("Initialization of FPGA device %d complete\n", cookie);
282 #endif
283 /*
284 * Run the post configuration function if there is one.
285 */
286 if (*fn->post)
287 (*fn->post)(cookie);
288 } else {
289 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
290 printf("** Initialization of FPGA device %d FAILED\n",
291 cookie);
292 #endif
293 }
294 return ret_val;
295 }
296
virtex2_ssm_load(xilinx_desc * desc,const void * buf,size_t bsize)297 static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
298 {
299 int ret_val = FPGA_FAIL;
300 xilinx_virtex2_slave_fns *fn = desc->iface_fns;
301 size_t bytecount = 0;
302 unsigned char *data = (unsigned char *)buf;
303 int cookie = desc->cookie;
304
305 ret_val = virtex2_slave_pre(fn, cookie);
306 if (ret_val != FPGA_SUCCESS)
307 return ret_val;
308
309 /*
310 * Load the data byte by byte
311 */
312 while (bytecount < bsize) {
313 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
314 if (ctrlc()) {
315 (*fn->abort)(cookie);
316 return FPGA_FAIL;
317 }
318 #endif
319
320 if ((*fn->done)(cookie) == FPGA_SUCCESS) {
321 log_debug("done went active early, bytecount = %zu\n",
322 bytecount);
323 break;
324 }
325
326 #ifdef CFG_SYS_FPGA_CHECK_ERROR
327 if ((*fn->init)(cookie)) {
328 printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
329 __func__, __LINE__);
330 printf("%zu = buffer offset, %zu = buffer size\n",
331 bytecount, bsize);
332 (*fn->abort)(cookie);
333 return FPGA_FAIL;
334 }
335 #endif
336
337 (*fn->wdata)(data[bytecount++], true, cookie);
338 CFG_FPGA_DELAY();
339
340 /*
341 * Cycle the clock pin
342 */
343 (*fn->clk)(false, true, cookie);
344 CFG_FPGA_DELAY();
345 (*fn->clk)(true, true, cookie);
346
347 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
348 ts = get_timer(0);
349 while ((*fn->busy)(cookie)) {
350 if (get_timer(ts) > CFG_SYS_FPGA_WAIT_BUSY) {
351 printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
352 __func__, __LINE__,
353 CFG_SYS_FPGA_WAIT_BUSY);
354 (*fn->abort)(cookie);
355 return FPGA_FAIL;
356 }
357 }
358 #endif
359
360 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
361 if (bytecount % (bsize / 40) == 0)
362 putc('.');
363 #endif
364 }
365
366 return virtex2_slave_post(fn, cookie);
367 }
368
369 /*
370 * Read the FPGA configuration data
371 */
virtex2_ssm_dump(xilinx_desc * desc,const void * buf,size_t bsize)372 static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
373 {
374 int ret_val = FPGA_FAIL;
375 xilinx_virtex2_slave_fns *fn = desc->iface_fns;
376
377 if (fn) {
378 unsigned char *data = (unsigned char *)buf;
379 size_t bytecount = 0;
380 int cookie = desc->cookie;
381
382 printf("Starting Dump of FPGA Device %d...\n", cookie);
383
384 (*fn->cs)(true, true, cookie);
385 (*fn->clk)(true, true, cookie);
386
387 while (bytecount < bsize) {
388 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
389 if (ctrlc()) {
390 (*fn->abort)(cookie);
391 return FPGA_FAIL;
392 }
393 #endif
394 /*
395 * Cycle the clock and read the data
396 */
397 (*fn->clk)(false, true, cookie);
398 (*fn->clk)(true, true, cookie);
399 (*fn->rdata)(&data[bytecount++], cookie);
400 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
401 if (bytecount % (bsize / 40) == 0)
402 putc('.');
403 #endif
404 }
405
406 /*
407 * Deassert CS_B and cycle the clock to deselect the device.
408 */
409 (*fn->cs)(false, false, cookie);
410 (*fn->clk)(false, true, cookie);
411 (*fn->clk)(true, true, cookie);
412
413 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
414 putc('\n');
415 #endif
416 puts("Done.\n");
417 } else {
418 printf("%s:%d: NULL Interface function table!\n",
419 __func__, __LINE__);
420 }
421 return ret_val;
422 }
423
virtex2_ss_load(xilinx_desc * desc,const void * buf,size_t bsize)424 static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
425 {
426 int ret_val = FPGA_FAIL;
427 xilinx_virtex2_slave_fns *fn = desc->iface_fns;
428 unsigned char *data = (unsigned char *)buf;
429 int cookie = desc->cookie;
430
431 ret_val = virtex2_slave_pre(fn, cookie);
432 if (ret_val != FPGA_SUCCESS)
433 return ret_val;
434
435 if (fn->wbulkdata) {
436 /* Load the data in a single chunk */
437 (*fn->wbulkdata)(data, bsize, true, cookie);
438 } else {
439 size_t bytecount = 0;
440
441 /*
442 * Load the data bit by bit
443 */
444 while (bytecount < bsize) {
445 unsigned char curr_data = data[bytecount++];
446 int bit;
447
448 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
449 if (ctrlc()) {
450 (*fn->abort) (cookie);
451 return FPGA_FAIL;
452 }
453 #endif
454
455 if ((*fn->done)(cookie) == FPGA_SUCCESS) {
456 log_debug("done went active early, bytecount = %zu\n",
457 bytecount);
458 break;
459 }
460
461 #ifdef CFG_SYS_FPGA_CHECK_ERROR
462 if ((*fn->init)(cookie)) {
463 printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
464 __func__, __LINE__);
465 printf("%zu = buffer offset, %zu = buffer size\n",
466 bytecount, bsize);
467 (*fn->abort)(cookie);
468 return FPGA_FAIL;
469 }
470 #endif
471
472 for (bit = 7; bit >= 0; --bit) {
473 unsigned char curr_bit = (curr_data >> bit) & 1;
474 (*fn->wdata)(curr_bit, true, cookie);
475 CFG_FPGA_DELAY();
476 (*fn->clk)(false, true, cookie);
477 CFG_FPGA_DELAY();
478 (*fn->clk)(true, true, cookie);
479 }
480
481 /* Slave serial never uses a busy pin */
482
483 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
484 if (bytecount % (bsize / 40) == 0)
485 putc('.');
486 #endif
487 }
488 }
489
490 return virtex2_slave_post(fn, cookie);
491 }
492
virtex2_ss_dump(xilinx_desc * desc,const void * buf,size_t bsize)493 static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
494 {
495 printf("%s: Slave Serial Dumping is unsupported\n", __func__);
496 return FPGA_FAIL;
497 }
498
499 /* vim: set ts=4 tw=78: */
500
501 struct xilinx_fpga_op virtex2_op = {
502 .load = virtex2_load,
503 .dump = virtex2_dump,
504 .info = virtex2_info,
505 };
506