1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2015 Google, Inc
4 *
5 * (C) Copyright 2008-2014 Rockchip Electronics
6 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <syscon.h>
12 #include <linux/errno.h>
13 #include <asm/gpio.h>
14 #include <asm/io.h>
15 #include <asm/arch-rockchip/clock.h>
16 #include <asm/arch-rockchip/hardware.h>
17 #include <asm/arch-rockchip/gpio.h>
18 #include <dm/pinctrl.h>
19 #include <dm/read.h>
20 #include <dt-bindings/pinctrl/rockchip.h>
21
22 #define SWPORT_DR 0x0000
23 #define SWPORT_DDR 0x0004
24 #define EXT_PORT 0x0050
25 #define SWPORT_DR_L 0x0000
26 #define SWPORT_DR_H 0x0004
27 #define SWPORT_DDR_L 0x0008
28 #define SWPORT_DDR_H 0x000C
29 #define EXT_PORT_V2 0x0070
30 #define VER_ID_V2 0x0078
31
32 enum {
33 ROCKCHIP_GPIOS_PER_BANK = 32,
34 };
35
36 struct rockchip_gpio_priv {
37 void __iomem *regs;
38 struct udevice *pinctrl;
39 int bank;
40 char name[2];
41 u32 version;
42 };
43
rockchip_gpio_get_value(struct udevice * dev,unsigned offset)44 static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset)
45 {
46 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
47 u32 mask = BIT(offset), data;
48
49 if (priv->version)
50 data = readl(priv->regs + EXT_PORT_V2);
51 else
52 data = readl(priv->regs + EXT_PORT);
53
54 return (data & mask) ? 1 : 0;
55 }
56
rockchip_gpio_set_value(struct udevice * dev,unsigned offset,int value)57 static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
58 int value)
59 {
60 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
61 u32 mask = BIT(offset), data = value ? mask : 0;
62
63 if (priv->version && offset >= 16)
64 rk_clrsetreg(priv->regs + SWPORT_DR_H, mask >> 16, data >> 16);
65 else if (priv->version)
66 rk_clrsetreg(priv->regs + SWPORT_DR_L, mask, data);
67 else
68 clrsetbits_le32(priv->regs + SWPORT_DR, mask, data);
69
70 return 0;
71 }
72
rockchip_gpio_direction_input(struct udevice * dev,unsigned offset)73 static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
74 {
75 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
76 u32 mask = BIT(offset);
77
78 if (priv->version && offset >= 16)
79 rk_clrreg(priv->regs + SWPORT_DDR_H, mask >> 16);
80 else if (priv->version)
81 rk_clrreg(priv->regs + SWPORT_DDR_L, mask);
82 else
83 clrbits_le32(priv->regs + SWPORT_DDR, mask);
84
85 return 0;
86 }
87
rockchip_gpio_direction_output(struct udevice * dev,unsigned offset,int value)88 static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
89 int value)
90 {
91 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
92 u32 mask = BIT(offset);
93
94 rockchip_gpio_set_value(dev, offset, value);
95
96 if (priv->version && offset >= 16)
97 rk_setreg(priv->regs + SWPORT_DDR_H, mask >> 16);
98 else if (priv->version)
99 rk_setreg(priv->regs + SWPORT_DDR_L, mask);
100 else
101 setbits_le32(priv->regs + SWPORT_DDR, mask);
102
103 return 0;
104 }
105
rockchip_gpio_get_function(struct udevice * dev,unsigned offset)106 static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
107 {
108 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
109 u32 mask = BIT(offset), data;
110 int ret;
111
112 if (CONFIG_IS_ENABLED(PINCTRL)) {
113 ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
114 if (ret < 0)
115 return ret;
116 else if (ret != RK_FUNC_GPIO)
117 return GPIOF_FUNC;
118 }
119
120 if (priv->version && offset >= 16)
121 data = readl(priv->regs + SWPORT_DDR_H) << 16;
122 else if (priv->version)
123 data = readl(priv->regs + SWPORT_DDR_L);
124 else
125 data = readl(priv->regs + SWPORT_DDR);
126
127 return (data & mask) ? GPIOF_OUTPUT : GPIOF_INPUT;
128 }
129
130 /* Simple SPL interface to GPIOs */
131 #ifdef CONFIG_SPL_BUILD
132
133 enum {
134 PULL_NONE_1V8 = 0,
135 PULL_DOWN_1V8 = 1,
136 PULL_UP_1V8 = 3,
137 };
138
spl_gpio_set_pull(void * vregs,uint gpio,int pull)139 int spl_gpio_set_pull(void *vregs, uint gpio, int pull)
140 {
141 u32 *regs = vregs;
142 uint val;
143
144 regs += gpio >> GPIO_BANK_SHIFT;
145 gpio &= GPIO_OFFSET_MASK;
146 switch (pull) {
147 case GPIO_PULL_UP:
148 val = PULL_UP_1V8;
149 break;
150 case GPIO_PULL_DOWN:
151 val = PULL_DOWN_1V8;
152 break;
153 case GPIO_PULL_NORMAL:
154 default:
155 val = PULL_NONE_1V8;
156 break;
157 }
158 clrsetbits_le32(regs, 3 << (gpio * 2), val << (gpio * 2));
159
160 return 0;
161 }
162
spl_gpio_output(void * vregs,uint gpio,int value)163 int spl_gpio_output(void *vregs, uint gpio, int value)
164 {
165 struct rockchip_gpio_regs * const regs = vregs;
166
167 clrsetbits_le32(®s->swport_dr, 1 << gpio, value << gpio);
168
169 /* Set direction */
170 clrsetbits_le32(®s->swport_ddr, 1 << gpio, 1 << gpio);
171
172 return 0;
173 }
174 #endif /* CONFIG_SPL_BUILD */
175
rockchip_gpio_probe(struct udevice * dev)176 static int rockchip_gpio_probe(struct udevice *dev)
177 {
178 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
179 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
180 struct ofnode_phandle_args args;
181 char *end;
182 int ret;
183
184 priv->regs = dev_read_addr_ptr(dev);
185
186 if (CONFIG_IS_ENABLED(PINCTRL)) {
187 ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
188 if (ret)
189 return ret;
190 }
191
192 /*
193 * If "gpio-ranges" is present in the devicetree use it to parse
194 * the GPIO bank ID, otherwise use the legacy method.
195 */
196 ret = ofnode_parse_phandle_with_args(dev_ofnode(dev),
197 "gpio-ranges", NULL, 3,
198 0, &args);
199 if (!ret || ret != -ENOENT) {
200 uc_priv->gpio_count = args.args[2];
201 priv->bank = args.args[1] / ROCKCHIP_GPIOS_PER_BANK;
202 } else {
203 uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
204 end = strrchr(dev->name, '@');
205 priv->bank = trailing_strtoln(dev->name, end);
206 }
207
208 priv->name[0] = 'A' + priv->bank;
209 uc_priv->bank_name = priv->name;
210
211 priv->version = readl(priv->regs + VER_ID_V2);
212
213 return 0;
214 }
215
216 static const struct dm_gpio_ops gpio_rockchip_ops = {
217 .direction_input = rockchip_gpio_direction_input,
218 .direction_output = rockchip_gpio_direction_output,
219 .get_value = rockchip_gpio_get_value,
220 .set_value = rockchip_gpio_set_value,
221 .get_function = rockchip_gpio_get_function,
222 };
223
224 static const struct udevice_id rockchip_gpio_ids[] = {
225 { .compatible = "rockchip,gpio-bank" },
226 { }
227 };
228
229 U_BOOT_DRIVER(rockchip_gpio_bank) = {
230 .name = "rockchip_gpio_bank",
231 .id = UCLASS_GPIO,
232 .of_match = rockchip_gpio_ids,
233 .ops = &gpio_rockchip_ops,
234 .priv_auto = sizeof(struct rockchip_gpio_priv),
235 .probe = rockchip_gpio_probe,
236 };
237