1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5 */
6
7 #define LOG_CATEGORY UCLASS_GPIO
8
9 #include <common.h>
10 #include <clk.h>
11 #include <dm.h>
12 #include <fdtdec.h>
13 #include <log.h>
14 #include <asm/arch/stm32.h>
15 #include <asm/gpio.h>
16 #include <asm/io.h>
17 #include <dm/device_compat.h>
18 #include <linux/bitops.h>
19 #include <linux/errno.h>
20 #include <linux/io.h>
21
22 #include "stm32_gpio_priv.h"
23
24 #define STM32_GPIOS_PER_BANK 16
25
26 #define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
27 #define MODE_BITS_MASK 3
28 #define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16))
29
30 #define PUPD_BITS(gpio_pin) ((gpio_pin) * 2)
31 #define PUPD_MASK 3
32
33 #define OTYPE_BITS(gpio_pin) (gpio_pin)
34 #define OTYPE_MSK 1
35
stm32_gpio_set_moder(struct stm32_gpio_regs * regs,int idx,int mode)36 static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
37 int idx,
38 int mode)
39 {
40 int bits_index;
41 int mask;
42
43 bits_index = MODE_BITS(idx);
44 mask = MODE_BITS_MASK << bits_index;
45
46 clrsetbits_le32(®s->moder, mask, mode << bits_index);
47 }
48
stm32_gpio_get_moder(struct stm32_gpio_regs * regs,int idx)49 static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
50 {
51 return (readl(®s->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
52 }
53
stm32_gpio_set_otype(struct stm32_gpio_regs * regs,int idx,enum stm32_gpio_otype otype)54 static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
55 int idx,
56 enum stm32_gpio_otype otype)
57 {
58 int bits;
59
60 bits = OTYPE_BITS(idx);
61 clrsetbits_le32(®s->otyper, OTYPE_MSK << bits, otype << bits);
62 }
63
stm32_gpio_get_otype(struct stm32_gpio_regs * regs,int idx)64 static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
65 int idx)
66 {
67 return (readl(®s->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
68 }
69
stm32_gpio_set_pupd(struct stm32_gpio_regs * regs,int idx,enum stm32_gpio_pupd pupd)70 static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
71 int idx,
72 enum stm32_gpio_pupd pupd)
73 {
74 int bits;
75
76 bits = PUPD_BITS(idx);
77 clrsetbits_le32(®s->pupdr, PUPD_MASK << bits, pupd << bits);
78 }
79
stm32_gpio_get_pupd(struct stm32_gpio_regs * regs,int idx)80 static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
81 int idx)
82 {
83 return (readl(®s->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
84 }
85
stm32_gpio_is_mapped(struct udevice * dev,int offset)86 static bool stm32_gpio_is_mapped(struct udevice *dev, int offset)
87 {
88 struct stm32_gpio_priv *priv = dev_get_priv(dev);
89
90 return !!(priv->gpio_range & BIT(offset));
91 }
92
stm32_gpio_direction_input(struct udevice * dev,unsigned offset)93 static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
94 {
95 struct stm32_gpio_priv *priv = dev_get_priv(dev);
96 struct stm32_gpio_regs *regs = priv->regs;
97
98 if (!stm32_gpio_is_mapped(dev, offset))
99 return -ENXIO;
100
101 stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_IN);
102
103 return 0;
104 }
105
stm32_gpio_direction_output(struct udevice * dev,unsigned offset,int value)106 static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
107 int value)
108 {
109 struct stm32_gpio_priv *priv = dev_get_priv(dev);
110 struct stm32_gpio_regs *regs = priv->regs;
111
112 if (!stm32_gpio_is_mapped(dev, offset))
113 return -ENXIO;
114
115 stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_OUT);
116
117 writel(BSRR_BIT(offset, value), ®s->bsrr);
118
119 return 0;
120 }
121
stm32_gpio_get_value(struct udevice * dev,unsigned offset)122 static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
123 {
124 struct stm32_gpio_priv *priv = dev_get_priv(dev);
125 struct stm32_gpio_regs *regs = priv->regs;
126
127 if (!stm32_gpio_is_mapped(dev, offset))
128 return -ENXIO;
129
130 return readl(®s->idr) & BIT(offset) ? 1 : 0;
131 }
132
stm32_gpio_set_value(struct udevice * dev,unsigned offset,int value)133 static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
134 {
135 struct stm32_gpio_priv *priv = dev_get_priv(dev);
136 struct stm32_gpio_regs *regs = priv->regs;
137
138 if (!stm32_gpio_is_mapped(dev, offset))
139 return -ENXIO;
140
141 writel(BSRR_BIT(offset, value), ®s->bsrr);
142
143 return 0;
144 }
145
stm32_gpio_get_function(struct udevice * dev,unsigned int offset)146 static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
147 {
148 struct stm32_gpio_priv *priv = dev_get_priv(dev);
149 struct stm32_gpio_regs *regs = priv->regs;
150 int bits_index;
151 int mask;
152 u32 mode;
153
154 if (!stm32_gpio_is_mapped(dev, offset))
155 return GPIOF_UNKNOWN;
156
157 bits_index = MODE_BITS(offset);
158 mask = MODE_BITS_MASK << bits_index;
159
160 mode = (readl(®s->moder) & mask) >> bits_index;
161 if (mode == STM32_GPIO_MODE_OUT)
162 return GPIOF_OUTPUT;
163 if (mode == STM32_GPIO_MODE_IN)
164 return GPIOF_INPUT;
165 if (mode == STM32_GPIO_MODE_AN)
166 return GPIOF_UNUSED;
167
168 return GPIOF_FUNC;
169 }
170
stm32_gpio_set_flags(struct udevice * dev,unsigned int offset,ulong flags)171 static int stm32_gpio_set_flags(struct udevice *dev, unsigned int offset,
172 ulong flags)
173 {
174 struct stm32_gpio_priv *priv = dev_get_priv(dev);
175 struct stm32_gpio_regs *regs = priv->regs;
176
177 if (!stm32_gpio_is_mapped(dev, offset))
178 return -ENXIO;
179
180 if (flags & GPIOD_IS_OUT) {
181 bool value = flags & GPIOD_IS_OUT_ACTIVE;
182
183 if (flags & GPIOD_OPEN_DRAIN)
184 stm32_gpio_set_otype(regs, offset, STM32_GPIO_OTYPE_OD);
185 else
186 stm32_gpio_set_otype(regs, offset, STM32_GPIO_OTYPE_PP);
187
188 stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_OUT);
189 writel(BSRR_BIT(offset, value), ®s->bsrr);
190
191 } else if (flags & GPIOD_IS_IN) {
192 stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_IN);
193 }
194 if (flags & GPIOD_PULL_UP)
195 stm32_gpio_set_pupd(regs, offset, STM32_GPIO_PUPD_UP);
196 else if (flags & GPIOD_PULL_DOWN)
197 stm32_gpio_set_pupd(regs, offset, STM32_GPIO_PUPD_DOWN);
198
199 return 0;
200 }
201
stm32_gpio_get_flags(struct udevice * dev,unsigned int offset,ulong * flagsp)202 static int stm32_gpio_get_flags(struct udevice *dev, unsigned int offset,
203 ulong *flagsp)
204 {
205 struct stm32_gpio_priv *priv = dev_get_priv(dev);
206 struct stm32_gpio_regs *regs = priv->regs;
207 ulong dir_flags = 0;
208
209 if (!stm32_gpio_is_mapped(dev, offset))
210 return -ENXIO;
211
212 switch (stm32_gpio_get_moder(regs, offset)) {
213 case STM32_GPIO_MODE_OUT:
214 dir_flags |= GPIOD_IS_OUT;
215 if (stm32_gpio_get_otype(regs, offset) == STM32_GPIO_OTYPE_OD)
216 dir_flags |= GPIOD_OPEN_DRAIN;
217 if (readl(®s->idr) & BIT(offset))
218 dir_flags |= GPIOD_IS_OUT_ACTIVE;
219 break;
220 case STM32_GPIO_MODE_IN:
221 dir_flags |= GPIOD_IS_IN;
222 break;
223 default:
224 break;
225 }
226 switch (stm32_gpio_get_pupd(regs, offset)) {
227 case STM32_GPIO_PUPD_UP:
228 dir_flags |= GPIOD_PULL_UP;
229 break;
230 case STM32_GPIO_PUPD_DOWN:
231 dir_flags |= GPIOD_PULL_DOWN;
232 break;
233 default:
234 break;
235 }
236 *flagsp = dir_flags;
237
238 return 0;
239 }
240
241 static const struct dm_gpio_ops gpio_stm32_ops = {
242 .direction_input = stm32_gpio_direction_input,
243 .direction_output = stm32_gpio_direction_output,
244 .get_value = stm32_gpio_get_value,
245 .set_value = stm32_gpio_set_value,
246 .get_function = stm32_gpio_get_function,
247 .set_flags = stm32_gpio_set_flags,
248 .get_flags = stm32_gpio_get_flags,
249 };
250
gpio_stm32_probe(struct udevice * dev)251 static int gpio_stm32_probe(struct udevice *dev)
252 {
253 struct stm32_gpio_priv *priv = dev_get_priv(dev);
254 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
255 struct ofnode_phandle_args args;
256 const char *name;
257 struct clk clk;
258 fdt_addr_t addr;
259 int ret, i;
260
261 addr = dev_read_addr(dev);
262 if (addr == FDT_ADDR_T_NONE)
263 return -EINVAL;
264
265 priv->regs = (struct stm32_gpio_regs *)addr;
266
267 name = dev_read_string(dev, "st,bank-name");
268 if (!name)
269 return -EINVAL;
270 uc_priv->bank_name = name;
271
272 i = 0;
273 ret = dev_read_phandle_with_args(dev, "gpio-ranges",
274 NULL, 3, i, &args);
275
276 if (!ret && args.args_count < 3)
277 return -EINVAL;
278
279 uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
280 if (ret == -ENOENT)
281 priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
282
283 while (ret != -ENOENT) {
284 priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
285 args.args[0]);
286
287 ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
288 ++i, &args);
289 if (!ret && args.args_count < 3)
290 return -EINVAL;
291 }
292
293 dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
294 (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
295 priv->gpio_range);
296
297 ret = clk_get_by_index(dev, 0, &clk);
298 if (ret < 0)
299 return ret;
300
301 ret = clk_enable(&clk);
302
303 if (ret) {
304 dev_err(dev, "failed to enable clock\n");
305 return ret;
306 }
307 dev_dbg(dev, "clock enabled\n");
308
309 return 0;
310 }
311
312 U_BOOT_DRIVER(gpio_stm32) = {
313 .name = "gpio_stm32",
314 .id = UCLASS_GPIO,
315 .probe = gpio_stm32_probe,
316 .ops = &gpio_stm32_ops,
317 .flags = DM_UC_FLAG_SEQ_ALIAS,
318 .priv_auto = sizeof(struct stm32_gpio_priv),
319 };
320