1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009
4 * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
5 * Copyright 2019 Google Inc
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <log.h>
11 #include <spl.h>
12 #include <acpi/acpigen.h>
13 #include <acpi/acpi_device.h>
14 #include <asm/lpss.h>
15 #include <dm/acpi.h>
16 #include <dm/device-internal.h>
17 #include <dm/uclass-internal.h>
18 #include "designware_i2c.h"
19
20 enum {
21 VANILLA = 0, /* standard I2C with no tweaks */
22 INTEL_APL, /* Apollo Lake I2C */
23 };
24
25 /* BayTrail HCNT/LCNT/SDA hold time */
26 static struct dw_scl_sda_cfg byt_config = {
27 .ss_hcnt = 0x200,
28 .fs_hcnt = 0x55,
29 .ss_lcnt = 0x200,
30 .fs_lcnt = 0x99,
31 .sda_hold = 0x6,
32 };
33
34 /* Have a weak function for now - possibly should be a new uclass */
35 __weak void lpss_reset_release(void *regs);
36
designware_i2c_pci_of_to_plat(struct udevice * dev)37 static int designware_i2c_pci_of_to_plat(struct udevice *dev)
38 {
39 struct dw_i2c *priv = dev_get_priv(dev);
40
41 if (spl_phase() < PHASE_SPL) {
42 u32 base;
43 int ret;
44
45 ret = dev_read_u32(dev, "early-regs", &base);
46 if (ret)
47 return log_msg_ret("early-regs", ret);
48
49 /* Set i2c base address */
50 dm_pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
51
52 /* Enable memory access and bus master */
53 dm_pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
54 PCI_COMMAND_MASTER);
55 }
56
57 if (spl_phase() < PHASE_BOARD_F) {
58 /* Handle early, fixed mapping into a different address space */
59 priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0);
60 } else {
61 priv->regs = (struct i2c_regs *)
62 dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
63 PCI_REGION_TYPE, PCI_REGION_MEM);
64 }
65 if (!priv->regs)
66 return -EINVAL;
67
68 /* Save base address from PCI BAR */
69 if (IS_ENABLED(CONFIG_INTEL_BAYTRAIL))
70 /* Use BayTrail specific timing values */
71 priv->scl_sda_cfg = &byt_config;
72 if (dev_get_driver_data(dev) == INTEL_APL)
73 priv->has_spk_cnt = true;
74
75 return designware_i2c_of_to_plat(dev);
76 }
77
designware_i2c_pci_probe(struct udevice * dev)78 static int designware_i2c_pci_probe(struct udevice *dev)
79 {
80 struct dw_i2c *priv = dev_get_priv(dev);
81
82 if (dev_get_driver_data(dev) == INTEL_APL) {
83 /* Ensure controller is in D0 state */
84 lpss_set_power_state(dev, STATE_D0);
85
86 lpss_reset_release(priv->regs);
87 }
88
89 return designware_i2c_probe(dev);
90 }
91
designware_i2c_pci_bind(struct udevice * dev)92 static int designware_i2c_pci_bind(struct udevice *dev)
93 {
94 char name[20];
95
96 if (dev_has_ofnode(dev))
97 return 0;
98
99 sprintf(name, "i2c_designware#%u", dev_seq(dev));
100 device_set_name(dev, name);
101
102 return 0;
103 }
104
105 /*
106 * Write ACPI object to describe speed configuration.
107 *
108 * ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold }
109 *
110 * SSCN: I2C_SPEED_STANDARD
111 * FMCN: I2C_SPEED_FAST
112 * FPCN: I2C_SPEED_FAST_PLUS
113 * HSCN: I2C_SPEED_HIGH
114 */
dw_i2c_acpi_write_speed_config(struct acpi_ctx * ctx,struct dw_i2c_speed_config * config)115 static void dw_i2c_acpi_write_speed_config(struct acpi_ctx *ctx,
116 struct dw_i2c_speed_config *config)
117 {
118 switch (config->speed_mode) {
119 case IC_SPEED_MODE_HIGH:
120 acpigen_write_name(ctx, "HSCN");
121 break;
122 case IC_SPEED_MODE_FAST_PLUS:
123 acpigen_write_name(ctx, "FPCN");
124 break;
125 case IC_SPEED_MODE_FAST:
126 acpigen_write_name(ctx, "FMCN");
127 break;
128 case IC_SPEED_MODE_STANDARD:
129 default:
130 acpigen_write_name(ctx, "SSCN");
131 }
132
133 /* Package () { scl_lcnt, scl_hcnt, sda_hold } */
134 acpigen_write_package(ctx, 3);
135 acpigen_write_word(ctx, config->scl_hcnt);
136 acpigen_write_word(ctx, config->scl_lcnt);
137 acpigen_write_dword(ctx, config->sda_hold);
138 acpigen_pop_len(ctx);
139 }
140
141 /*
142 * Generate I2C timing information into the SSDT for the OS driver to consume,
143 * optionally applying override values provided by the caller.
144 */
dw_i2c_acpi_fill_ssdt(const struct udevice * dev,struct acpi_ctx * ctx)145 static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev,
146 struct acpi_ctx *ctx)
147 {
148 struct dw_i2c_speed_config config;
149 char path[ACPI_PATH_MAX];
150 uint speed;
151 int ret;
152
153 /* If no device-tree node, ignore this since we assume it isn't used */
154 if (!dev_has_ofnode(dev))
155 return 0;
156
157 ret = acpi_device_path(dev, path, sizeof(path));
158 if (ret)
159 return log_msg_ret("path", ret);
160
161 speed = dev_read_u32_default(dev, "clock-frequency", 100000);
162 acpigen_write_scope(ctx, path);
163 ret = dw_i2c_gen_speed_config(dev, speed, &config);
164 if (ret)
165 return log_msg_ret("config", ret);
166 dw_i2c_acpi_write_speed_config(ctx, &config);
167 acpigen_pop_len(ctx);
168
169 return 0;
170 }
171
172 struct acpi_ops dw_i2c_acpi_ops = {
173 .fill_ssdt = dw_i2c_acpi_fill_ssdt,
174 };
175
176 static const struct udevice_id designware_i2c_pci_ids[] = {
177 { .compatible = "snps,designware-i2c-pci" },
178 { .compatible = "intel,apl-i2c", .data = INTEL_APL },
179 { }
180 };
181
182 DM_DRIVER_ALIAS(i2c_designware_pci, intel_apl_i2c)
183
184 U_BOOT_DRIVER(i2c_designware_pci) = {
185 .name = "i2c_designware_pci",
186 .id = UCLASS_I2C,
187 .of_match = designware_i2c_pci_ids,
188 .bind = designware_i2c_pci_bind,
189 .of_to_plat = designware_i2c_pci_of_to_plat,
190 .probe = designware_i2c_pci_probe,
191 .priv_auto = sizeof(struct dw_i2c),
192 .remove = designware_i2c_remove,
193 .flags = DM_FLAG_OS_PREPARE,
194 .ops = &designware_i2c_ops,
195 ACPI_OPS_PTR(&dw_i2c_acpi_ops)
196 };
197
198 static struct pci_device_id designware_pci_supported[] = {
199 /* Intel BayTrail has 7 I2C controller located on the PCI bus */
200 { PCI_VDEVICE(INTEL, 0x0f41) },
201 { PCI_VDEVICE(INTEL, 0x0f42) },
202 { PCI_VDEVICE(INTEL, 0x0f43) },
203 { PCI_VDEVICE(INTEL, 0x0f44) },
204 { PCI_VDEVICE(INTEL, 0x0f45) },
205 { PCI_VDEVICE(INTEL, 0x0f46) },
206 { PCI_VDEVICE(INTEL, 0x0f47) },
207 { PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL },
208 { PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL },
209 { PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL },
210 { PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL },
211 { PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL },
212 { PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL },
213 {},
214 };
215
216 U_BOOT_PCI_DEVICE(i2c_designware_pci, designware_pci_supported);
217