1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
4 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
5 *
6 * This file is based on: drivers/i2c/zynq_i2c.c,
7 * with added driver-model support and code cleanup.
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <log.h>
13 #include <linux/bitops.h>
14 #include <linux/delay.h>
15 #include <linux/types.h>
16 #include <linux/io.h>
17 #include <linux/errno.h>
18 #include <dm/device_compat.h>
19 #include <dm/root.h>
20 #include <i2c.h>
21 #include <fdtdec.h>
22 #include <mapmem.h>
23 #include <wait_bit.h>
24 #include <clk.h>
25
26 /* i2c register set */
27 struct cdns_i2c_regs {
28 u32 control;
29 u32 status;
30 u32 address;
31 u32 data;
32 u32 interrupt_status;
33 u32 transfer_size;
34 u32 slave_mon_pause;
35 u32 time_out;
36 u32 interrupt_mask;
37 u32 interrupt_enable;
38 u32 interrupt_disable;
39 };
40
41 /* Control register fields */
42 #define CDNS_I2C_CONTROL_RW 0x00000001
43 #define CDNS_I2C_CONTROL_MS 0x00000002
44 #define CDNS_I2C_CONTROL_NEA 0x00000004
45 #define CDNS_I2C_CONTROL_ACKEN 0x00000008
46 #define CDNS_I2C_CONTROL_HOLD 0x00000010
47 #define CDNS_I2C_CONTROL_SLVMON 0x00000020
48 #define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040
49 #define CDNS_I2C_CONTROL_DIV_B_SHIFT 8
50 #define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00
51 #define CDNS_I2C_CONTROL_DIV_A_SHIFT 14
52 #define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000
53
54 /* Status register values */
55 #define CDNS_I2C_STATUS_RXDV 0x00000020
56 #define CDNS_I2C_STATUS_TXDV 0x00000040
57 #define CDNS_I2C_STATUS_RXOVF 0x00000080
58 #define CDNS_I2C_STATUS_BA 0x00000100
59
60 /* Interrupt register fields */
61 #define CDNS_I2C_INTERRUPT_COMP 0x00000001
62 #define CDNS_I2C_INTERRUPT_DATA 0x00000002
63 #define CDNS_I2C_INTERRUPT_NACK 0x00000004
64 #define CDNS_I2C_INTERRUPT_TO 0x00000008
65 #define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010
66 #define CDNS_I2C_INTERRUPT_RXOVF 0x00000020
67 #define CDNS_I2C_INTERRUPT_TXOVF 0x00000040
68 #define CDNS_I2C_INTERRUPT_RXUNF 0x00000080
69 #define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200
70
71 #define CDNS_I2C_INTERRUPTS_MASK (CDNS_I2C_INTERRUPT_COMP | \
72 CDNS_I2C_INTERRUPT_DATA | \
73 CDNS_I2C_INTERRUPT_NACK | \
74 CDNS_I2C_INTERRUPT_TO | \
75 CDNS_I2C_INTERRUPT_SLVRDY | \
76 CDNS_I2C_INTERRUPT_RXOVF | \
77 CDNS_I2C_INTERRUPT_TXOVF | \
78 CDNS_I2C_INTERRUPT_RXUNF | \
79 CDNS_I2C_INTERRUPT_ARBLOST)
80
81 #define CDNS_I2C_FIFO_DEPTH_DEFAULT 16
82 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
83 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
84
85 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
86
87 #define CDNS_I2C_ARB_LOST_MAX_RETRIES 10
88
89 #ifdef DEBUG
cdns_i2c_debug_status(struct cdns_i2c_regs * cdns_i2c)90 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
91 {
92 int int_status;
93 int status;
94 int_status = readl(&cdns_i2c->interrupt_status);
95
96 status = readl(&cdns_i2c->status);
97 if (int_status || status) {
98 debug("Status: ");
99 if (int_status & CDNS_I2C_INTERRUPT_COMP)
100 debug("COMP ");
101 if (int_status & CDNS_I2C_INTERRUPT_DATA)
102 debug("DATA ");
103 if (int_status & CDNS_I2C_INTERRUPT_NACK)
104 debug("NACK ");
105 if (int_status & CDNS_I2C_INTERRUPT_TO)
106 debug("TO ");
107 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
108 debug("SLVRDY ");
109 if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
110 debug("RXOVF ");
111 if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
112 debug("TXOVF ");
113 if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
114 debug("RXUNF ");
115 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
116 debug("ARBLOST ");
117 if (status & CDNS_I2C_STATUS_RXDV)
118 debug("RXDV ");
119 if (status & CDNS_I2C_STATUS_TXDV)
120 debug("TXDV ");
121 if (status & CDNS_I2C_STATUS_RXOVF)
122 debug("RXOVF ");
123 if (status & CDNS_I2C_STATUS_BA)
124 debug("BA ");
125 debug("TS%d ", readl(&cdns_i2c->transfer_size));
126 debug("\n");
127 }
128 }
129 #endif
130
131 struct i2c_cdns_bus {
132 int id;
133 unsigned int input_freq;
134 struct cdns_i2c_regs __iomem *regs; /* register base */
135
136 int hold_flag;
137 u32 quirks;
138 u32 fifo_depth;
139 };
140
141 struct cdns_i2c_platform_data {
142 u32 quirks;
143 };
144
145 /* Wait for an interrupt */
cdns_i2c_wait(struct cdns_i2c_regs * cdns_i2c,u32 mask)146 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
147 {
148 int timeout, int_status;
149
150 for (timeout = 0; timeout < 100; timeout++) {
151 int_status = readl(&cdns_i2c->interrupt_status);
152 if (int_status & mask)
153 break;
154 udelay(100);
155 }
156
157 /* Clear interrupt status flags */
158 writel(int_status & mask, &cdns_i2c->interrupt_status);
159
160 return int_status & mask;
161 }
162
163 #define CDNS_I2C_DIVA_MAX 4
164 #define CDNS_I2C_DIVB_MAX 64
165
cdns_i2c_calc_divs(unsigned long * f,unsigned long input_clk,unsigned int * a,unsigned int * b)166 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
167 unsigned int *a, unsigned int *b)
168 {
169 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
170 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
171 unsigned int last_error, current_error;
172
173 /* calculate (divisor_a+1) x (divisor_b+1) */
174 temp = input_clk / (22 * fscl);
175
176 /*
177 * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
178 * the fscl input is out of range. Return error.
179 */
180 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
181 return -EINVAL;
182
183 last_error = -1;
184 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
185 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
186
187 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
188 continue;
189 div_b--;
190
191 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
192
193 if (actual_fscl > fscl)
194 continue;
195
196 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
197 (fscl - actual_fscl));
198
199 if (last_error > current_error) {
200 calc_div_a = div_a;
201 calc_div_b = div_b;
202 best_fscl = actual_fscl;
203 last_error = current_error;
204 }
205 }
206
207 *a = calc_div_a;
208 *b = calc_div_b;
209 *f = best_fscl;
210
211 return 0;
212 }
213
cdns_i2c_set_bus_speed(struct udevice * dev,unsigned int speed)214 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
215 {
216 struct i2c_cdns_bus *bus = dev_get_priv(dev);
217 u32 div_a = 0, div_b = 0;
218 unsigned long speed_p = speed;
219 int ret = 0;
220
221 if (speed > I2C_SPEED_FAST_RATE) {
222 debug("%s, failed to set clock speed to %u\n", __func__,
223 speed);
224 return -EINVAL;
225 }
226
227 ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
228 if (ret)
229 return ret;
230
231 debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
232 __func__, div_a, div_b, bus->input_freq, speed, speed_p);
233
234 writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
235 (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
236
237 /* Enable master mode, ack, and 7-bit addressing */
238 setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
239 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
240
241 return 0;
242 }
243
is_arbitration_lost(struct cdns_i2c_regs * regs)244 static inline u32 is_arbitration_lost(struct cdns_i2c_regs *regs)
245 {
246 return (readl(®s->interrupt_status) & CDNS_I2C_INTERRUPT_ARBLOST);
247 }
248
cdns_i2c_write_data(struct i2c_cdns_bus * i2c_bus,u32 addr,u8 * data,u32 len)249 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
250 u32 len)
251 {
252 u8 *cur_data = data;
253 struct cdns_i2c_regs *regs = i2c_bus->regs;
254 u32 ret;
255 bool start = 1;
256
257 /* Set the controller in Master transmit mode and clear FIFO */
258 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO);
259 clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW);
260
261 /*
262 * For sequential data load hold the bus.
263 */
264 if (len > 1)
265 setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
266
267 /* Clear the interrupts in status register */
268 writel(CDNS_I2C_INTERRUPTS_MASK, ®s->interrupt_status);
269
270 /* In case of Probe (i.e no data), start the transfer */
271 if (!len)
272 writel(addr, ®s->address);
273
274 while (len-- && !is_arbitration_lost(regs)) {
275 writel(*(cur_data++), ®s->data);
276 /* Trigger write only after loading data */
277 if (start) {
278 writel(addr, ®s->address);
279 start = 0;
280 }
281 if (len && readl(®s->transfer_size) == i2c_bus->fifo_depth) {
282 ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
283 CDNS_I2C_INTERRUPT_ARBLOST);
284 if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
285 return -EAGAIN;
286 if (ret & CDNS_I2C_INTERRUPT_COMP)
287 continue;
288 /* Release the bus */
289 clrbits_le32(®s->control,
290 CDNS_I2C_CONTROL_HOLD);
291 return -ETIMEDOUT;
292 }
293 }
294
295 if (len && is_arbitration_lost(regs))
296 return -EAGAIN;
297
298 /* All done... release the bus */
299 if (!i2c_bus->hold_flag)
300 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
301
302 /* Wait for the address and data to be sent */
303 ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
304 CDNS_I2C_INTERRUPT_ARBLOST);
305 if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
306 CDNS_I2C_INTERRUPT_COMP)))
307 return -ETIMEDOUT;
308 if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
309 return -EAGAIN;
310
311 return 0;
312 }
313
cdns_is_hold_quirk(struct i2c_cdns_bus * i2c_bus,int hold_quirk,int curr_recv_count)314 static inline bool cdns_is_hold_quirk(struct i2c_cdns_bus *i2c_bus, int hold_quirk,
315 int curr_recv_count)
316 {
317 return hold_quirk && (curr_recv_count == i2c_bus->fifo_depth + 1);
318 }
319
cdns_i2c_read_data(struct i2c_cdns_bus * i2c_bus,u32 addr,u8 * data,u32 recv_count)320 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
321 u32 recv_count)
322 {
323 u8 *cur_data = data;
324 struct cdns_i2c_regs *regs = i2c_bus->regs;
325 u32 curr_recv_count;
326 int updatetx, hold_quirk;
327 u32 ret;
328
329 curr_recv_count = recv_count;
330
331 /* Check for the message size against the FIFO depth */
332 if (recv_count > i2c_bus->fifo_depth)
333 setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
334
335 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
336 CDNS_I2C_CONTROL_RW);
337
338 if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
339 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
340 writel(curr_recv_count, ®s->transfer_size);
341 } else {
342 writel(recv_count, ®s->transfer_size);
343 }
344
345 /* Start reading data */
346 writel(addr, ®s->address);
347
348 updatetx = recv_count > curr_recv_count;
349
350 hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
351
352 while (recv_count && !is_arbitration_lost(regs)) {
353 while (readl(®s->status) & CDNS_I2C_STATUS_RXDV) {
354 if (recv_count < i2c_bus->fifo_depth &&
355 !i2c_bus->hold_flag) {
356 clrbits_le32(®s->control,
357 CDNS_I2C_CONTROL_HOLD);
358 }
359 *(cur_data)++ = readl(®s->data);
360 recv_count--;
361 curr_recv_count--;
362
363 if (cdns_is_hold_quirk(i2c_bus, hold_quirk, curr_recv_count))
364 break;
365 }
366
367 if (cdns_is_hold_quirk(i2c_bus, hold_quirk, curr_recv_count)) {
368 /* wait while fifo is full */
369 while (readl(®s->transfer_size) !=
370 (curr_recv_count - i2c_bus->fifo_depth))
371 ;
372 /*
373 * Check number of bytes to be received against maximum
374 * transfer size and update register accordingly.
375 */
376 if ((recv_count - i2c_bus->fifo_depth) >
377 CDNS_I2C_TRANSFER_SIZE) {
378 writel(CDNS_I2C_TRANSFER_SIZE,
379 ®s->transfer_size);
380 curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
381 i2c_bus->fifo_depth;
382 } else {
383 writel(recv_count - i2c_bus->fifo_depth,
384 ®s->transfer_size);
385 curr_recv_count = recv_count;
386 }
387 } else if (recv_count && !hold_quirk && !curr_recv_count) {
388 if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
389 writel(CDNS_I2C_TRANSFER_SIZE,
390 ®s->transfer_size);
391 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
392 } else {
393 writel(recv_count, ®s->transfer_size);
394 curr_recv_count = recv_count;
395 }
396 writel(addr, ®s->address);
397 }
398 }
399
400 /* Wait for the address and data to be sent */
401 ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
402 CDNS_I2C_INTERRUPT_ARBLOST);
403 if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
404 CDNS_I2C_INTERRUPT_COMP)))
405 return -ETIMEDOUT;
406 if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
407 return -EAGAIN;
408
409 return 0;
410 }
411
cdns_i2c_xfer(struct udevice * dev,struct i2c_msg * msg,int nmsgs)412 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
413 int nmsgs)
414 {
415 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
416 int ret = 0;
417 int count;
418 bool hold_quirk;
419 struct i2c_msg *message = msg;
420 int num_msgs = nmsgs;
421
422 hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
423
424 if (nmsgs > 1) {
425 /*
426 * This controller does not give completion interrupt after a
427 * master receive message if HOLD bit is set (repeated start),
428 * resulting in SW timeout. Hence, if a receive message is
429 * followed by any other message, an error is returned
430 * indicating that this sequence is not supported.
431 */
432 for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
433 if (msg[count].flags & I2C_M_RD) {
434 printf("Can't do repeated start after a receive message\n");
435 return -EOPNOTSUPP;
436 }
437 }
438
439 i2c_bus->hold_flag = 1;
440 setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
441 } else {
442 i2c_bus->hold_flag = 0;
443 }
444
445 debug("i2c_xfer: %d messages\n", nmsgs);
446 for (u8 retry = 0; retry < CDNS_I2C_ARB_LOST_MAX_RETRIES &&
447 nmsgs > 0;) {
448 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
449 if (msg->flags & I2C_M_RD) {
450 ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
451 msg->len);
452 } else {
453 ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
454 msg->len);
455 }
456 if (ret == -EAGAIN) {
457 msg = message;
458 nmsgs = num_msgs;
459 retry++;
460 printf("%s,arbitration lost, retrying:%d\n", __func__,
461 retry);
462 continue;
463 }
464 nmsgs--;
465 msg++;
466 if (ret) {
467 debug("i2c_write: error sending\n");
468 return -EREMOTEIO;
469 }
470 }
471
472 return ret;
473 }
474
cdns_i2c_of_to_plat(struct udevice * dev)475 static int cdns_i2c_of_to_plat(struct udevice *dev)
476 {
477 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
478 struct cdns_i2c_platform_data *pdata =
479 (struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
480 struct clk clk;
481 int ret;
482
483 i2c_bus->regs = dev_read_addr_ptr(dev);
484 if (!i2c_bus->regs)
485 return -EINVAL;
486
487 if (pdata)
488 i2c_bus->quirks = pdata->quirks;
489
490 ret = clk_get_by_index(dev, 0, &clk);
491 if (ret)
492 return ret;
493
494 i2c_bus->input_freq = clk_get_rate(&clk);
495
496 ret = clk_enable(&clk);
497 if (ret) {
498 dev_err(dev, "failed to enable clock\n");
499 return ret;
500 }
501
502 /* Update FIFO depth based on device tree entry */
503 i2c_bus->fifo_depth = dev_read_u32_default(dev, "fifo-depth",
504 CDNS_I2C_FIFO_DEPTH_DEFAULT);
505
506 return 0;
507 }
508
509 static const struct dm_i2c_ops cdns_i2c_ops = {
510 .xfer = cdns_i2c_xfer,
511 .set_bus_speed = cdns_i2c_set_bus_speed,
512 };
513
514 static const struct cdns_i2c_platform_data r1p10_i2c_def = {
515 .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
516 };
517
518 static const struct udevice_id cdns_i2c_of_match[] = {
519 { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
520 { .compatible = "cdns,i2c-r1p14" },
521 { /* end of table */ }
522 };
523
524 U_BOOT_DRIVER(cdns_i2c) = {
525 .name = "i2c_cdns",
526 .id = UCLASS_I2C,
527 .of_match = cdns_i2c_of_match,
528 .of_to_plat = cdns_i2c_of_to_plat,
529 .priv_auto = sizeof(struct i2c_cdns_bus),
530 .ops = &cdns_i2c_ops,
531 };
532