1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2022 MediaTek Inc. All Rights Reserved.
4 *
5 * Author: Mingming Lee <Mingming.Lee@mediatek.com>
6 *
7 * MediaTek I2C Interface driver
8 */
9
10 #include <clk.h>
11 #include <cpu_func.h>
12 #include <dm.h>
13 #include <i2c.h>
14 #include <log.h>
15 #include <asm/cache.h>
16 #include <asm/io.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19
20 #define I2C_RS_TRANSFER BIT(4)
21 #define I2C_HS_NACKERR BIT(2)
22 #define I2C_ACKERR BIT(1)
23 #define I2C_TRANSAC_COMP BIT(0)
24 #define I2C_TRANSAC_START BIT(0)
25 #define I2C_RS_MUL_CNFG BIT(15)
26 #define I2C_RS_MUL_TRIG BIT(14)
27 #define I2C_DCM_DISABLE 0x0000
28 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
29 #define I2C_IO_CONFIG_PUSH_PULL 0x0000
30 #define I2C_SOFT_RST 0x0001
31 #define I2C_FIFO_ADDR_CLR 0x0001
32 #define I2C_DELAY_LEN 0x0002
33 #define I2C_ST_START_CON 0x8001
34 #define I2C_FS_START_CON 0x1800
35 #define I2C_TIME_CLR_VALUE 0x0000
36 #define I2C_TIME_DEFAULT_VALUE 0x0003
37 #define I2C_WRRD_TRANAC_VALUE 0x0002
38 #define I2C_RD_TRANAC_VALUE 0x0001
39
40 #define I2C_DMA_CON_TX 0x0000
41 #define I2C_DMA_CON_RX 0x0001
42 #define I2C_DMA_START_EN 0x0001
43 #define I2C_DMA_INT_FLAG_NONE 0x0000
44 #define I2C_DMA_CLR_FLAG 0x0000
45 #define I2C_DMA_TX_RX 0x0000
46 #define I2C_DMA_HARD_RST 0x0002
47
48 #define MAX_ST_MODE_SPEED 100000
49 #define MAX_FS_MODE_SPEED 400000
50 #define MAX_HS_MODE_SPEED 3400000
51 #define MAX_SAMPLE_CNT_DIV 8
52 #define MAX_STEP_CNT_DIV 64
53 #define MAX_HS_STEP_CNT_DIV 8
54 #define I2C_DEFAULT_CLK_DIV 4
55
56 #define MAX_I2C_ADDR 0x7f
57 #define MAX_I2C_LEN 0xff
58 #define TRANS_ADDR_ONLY BIT(8)
59 #define TRANSFER_TIMEOUT 50000 /* us */
60 #define I2C_FIFO_STAT1_MASK 0x001f
61 #define TIMING_SAMPLE_OFFSET 8
62 #define HS_SAMPLE_OFFSET 12
63 #define HS_STEP_OFFSET 8
64
65 #define I2C_CONTROL_WRAPPER BIT(0)
66 #define I2C_CONTROL_RS BIT(1)
67 #define I2C_CONTROL_DMA_EN BIT(2)
68 #define I2C_CONTROL_CLK_EXT_EN BIT(3)
69 #define I2C_CONTROL_DIR_CHANGE BIT(4)
70 #define I2C_CONTROL_ACKERR_DET_EN BIT(5)
71 #define I2C_CONTROL_TRANSFER_LEN_CHANGE BIT(6)
72 #define I2C_CONTROL_DMAACK BIT(8)
73 #define I2C_CONTROL_ASYNC BIT(9)
74
75 #define I2C_MASTER_WR BIT(0)
76 #define I2C_MASTER_RD BIT(1)
77 #define I2C_MASTER_WRRD (I2C_MASTER_WR | I2C_MASTER_RD)
78
79 enum I2C_REGS_OFFSET {
80 REG_PORT,
81 REG_SLAVE_ADDR,
82 REG_INTR_MASK,
83 REG_INTR_STAT,
84 REG_CONTROL,
85 REG_TRANSFER_LEN,
86 REG_TRANSAC_LEN,
87 REG_DELAY_LEN,
88 REG_TIMING,
89 REG_START,
90 REG_EXT_CONF,
91 REG_FIFO_STAT1,
92 REG_LTIMING,
93 REG_FIFO_STAT,
94 REG_FIFO_THRESH,
95 REG_FIFO_ADDR_CLR,
96 REG_IO_CONFIG,
97 REG_RSV_DEBUG,
98 REG_HS,
99 REG_SOFTRESET,
100 REG_DCM_EN,
101 REG_PATH_DIR,
102 REG_DEBUGSTAT,
103 REG_DEBUGCTRL,
104 REG_TRANSFER_LEN_AUX,
105 REG_CLOCK_DIV,
106 REG_SCL_HL_RATIO,
107 REG_SCL_HS_HL_RATIO,
108 REG_SCL_MIS_COMP_POINT,
109 REG_STA_STOP_AC_TIME,
110 REG_HS_STA_STOP_AC_TIME,
111 REG_DATA_TIME,
112 };
113
114 enum DMA_REGS_OFFSET {
115 REG_INT_FLAG = 0x0,
116 REG_INT_EN = 0x04,
117 REG_EN = 0x08,
118 REG_RST = 0x0c,
119 REG_CON = 0x18,
120 REG_TX_MEM_ADDR = 0x1c,
121 REG_RX_MEM_ADDR = 0x20,
122 REG_TX_LEN = 0x24,
123 REG_RX_LEN = 0x28,
124 };
125
126 static const uint mt_i2c_regs_v1[] = {
127 [REG_PORT] = 0x0,
128 [REG_SLAVE_ADDR] = 0x4,
129 [REG_INTR_MASK] = 0x8,
130 [REG_INTR_STAT] = 0xc,
131 [REG_CONTROL] = 0x10,
132 [REG_TRANSFER_LEN] = 0x14,
133 [REG_TRANSAC_LEN] = 0x18,
134 [REG_DELAY_LEN] = 0x1c,
135 [REG_TIMING] = 0x20,
136 [REG_START] = 0x24,
137 [REG_EXT_CONF] = 0x28,
138 [REG_FIFO_STAT1] = 0x2c,
139 [REG_FIFO_STAT] = 0x30,
140 [REG_FIFO_THRESH] = 0x34,
141 [REG_FIFO_ADDR_CLR] = 0x38,
142 [REG_IO_CONFIG] = 0x40,
143 [REG_RSV_DEBUG] = 0x44,
144 [REG_HS] = 0x48,
145 [REG_SOFTRESET] = 0x50,
146 [REG_SOFTRESET] = 0x50,
147 [REG_DCM_EN] = 0x54,
148 [REG_DEBUGSTAT] = 0x64,
149 [REG_DEBUGCTRL] = 0x68,
150 [REG_TRANSFER_LEN_AUX] = 0x6c,
151 [REG_CLOCK_DIV] = 0x70,
152 [REG_SCL_HL_RATIO] = 0x74,
153 [REG_SCL_HS_HL_RATIO] = 0x78,
154 [REG_SCL_MIS_COMP_POINT] = 0x7c,
155 [REG_STA_STOP_AC_TIME] = 0x80,
156 [REG_HS_STA_STOP_AC_TIME] = 0x84,
157 [REG_DATA_TIME] = 0x88,
158 };
159
160 static const uint mt_i2c_regs_v2[] = {
161 [REG_PORT] = 0x0,
162 [REG_SLAVE_ADDR] = 0x4,
163 [REG_INTR_MASK] = 0x8,
164 [REG_INTR_STAT] = 0xc,
165 [REG_CONTROL] = 0x10,
166 [REG_TRANSFER_LEN] = 0x14,
167 [REG_TRANSAC_LEN] = 0x18,
168 [REG_DELAY_LEN] = 0x1c,
169 [REG_TIMING] = 0x20,
170 [REG_START] = 0x24,
171 [REG_EXT_CONF] = 0x28,
172 [REG_LTIMING] = 0x2c,
173 [REG_HS] = 0x30,
174 [REG_IO_CONFIG] = 0x34,
175 [REG_FIFO_ADDR_CLR] = 0x38,
176 [REG_TRANSFER_LEN_AUX] = 0x44,
177 [REG_CLOCK_DIV] = 0x48,
178 [REG_SOFTRESET] = 0x50,
179 [REG_DEBUGSTAT] = 0xe0,
180 [REG_DEBUGCTRL] = 0xe8,
181 [REG_FIFO_STAT] = 0xf4,
182 [REG_FIFO_THRESH] = 0xf8,
183 [REG_DCM_EN] = 0xf88,
184 };
185
186 struct mtk_i2c_soc_data {
187 const uint *regs;
188 uint dma_sync: 1;
189 };
190
191 struct mtk_i2c_priv {
192 /* set in i2c probe */
193 void __iomem *base; /* i2c base addr */
194 void __iomem *pdmabase; /* dma base address*/
195 struct clk clk_main; /* main clock for i2c bus */
196 struct clk clk_dma; /* DMA clock for i2c via DMA */
197 const struct mtk_i2c_soc_data *soc_data; /* Compatible data for different IC */
198 int op; /* operation mode */
199 bool zero_len; /* Only transfer slave address, no data */
200 bool pushpull; /* push pull mode or open drain mode */
201 bool filter_msg; /* filter msg error log */
202 bool auto_restart; /* restart mode */
203 bool ignore_restart_irq; /* ignore restart IRQ */
204 uint speed; /* i2c speed, unit: hz */
205 };
206
i2c_writel(struct mtk_i2c_priv * priv,uint reg,uint value)207 static inline void i2c_writel(struct mtk_i2c_priv *priv, uint reg, uint value)
208 {
209 u32 offset = priv->soc_data->regs[reg];
210
211 writel(value, priv->base + offset);
212 }
213
i2c_readl(struct mtk_i2c_priv * priv,uint offset)214 static inline uint i2c_readl(struct mtk_i2c_priv *priv, uint offset)
215 {
216 return readl(priv->base + priv->soc_data->regs[offset]);
217 }
218
mtk_i2c_clk_enable(struct mtk_i2c_priv * priv)219 static int mtk_i2c_clk_enable(struct mtk_i2c_priv *priv)
220 {
221 int ret;
222
223 ret = clk_enable(&priv->clk_main);
224 if (ret)
225 return log_msg_ret("enable clk_main", ret);
226
227 ret = clk_enable(&priv->clk_dma);
228 if (ret)
229 return log_msg_ret("enable clk_dma", ret);
230
231 return 0;
232 }
233
mtk_i2c_clk_disable(struct mtk_i2c_priv * priv)234 static int mtk_i2c_clk_disable(struct mtk_i2c_priv *priv)
235 {
236 int ret;
237
238 ret = clk_disable(&priv->clk_dma);
239 if (ret)
240 return log_msg_ret("disable clk_dma", ret);
241
242 ret = clk_disable(&priv->clk_main);
243 if (ret)
244 return log_msg_ret("disable clk_main", ret);
245
246 return 0;
247 }
248
mtk_i2c_init_hw(struct mtk_i2c_priv * priv)249 static void mtk_i2c_init_hw(struct mtk_i2c_priv *priv)
250 {
251 uint control_reg;
252
253 writel(I2C_DMA_HARD_RST, priv->pdmabase + REG_RST);
254 writel(I2C_DMA_CLR_FLAG, priv->pdmabase + REG_RST);
255 i2c_writel(priv, REG_SOFTRESET, I2C_SOFT_RST);
256 /* set ioconfig */
257 if (priv->pushpull)
258 i2c_writel(priv, REG_IO_CONFIG, I2C_IO_CONFIG_PUSH_PULL);
259 else
260 i2c_writel(priv, REG_IO_CONFIG, I2C_IO_CONFIG_OPEN_DRAIN);
261
262 i2c_writel(priv, REG_DCM_EN, I2C_DCM_DISABLE);
263 control_reg = I2C_CONTROL_ACKERR_DET_EN | I2C_CONTROL_CLK_EXT_EN;
264 if (priv->soc_data->dma_sync)
265 control_reg |= I2C_CONTROL_DMAACK | I2C_CONTROL_ASYNC;
266 i2c_writel(priv, REG_CONTROL, control_reg);
267 i2c_writel(priv, REG_DELAY_LEN, I2C_DELAY_LEN);
268 }
269
270 /*
271 * Calculate i2c port speed
272 *
273 * Hardware design:
274 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
275 * clock_div: fixed in hardware, but may be various in different SoCs
276 *
277 * The calculation want to pick the highest bus frequency that is still
278 * less than or equal to target_speed. The calculation try to get
279 * sample_cnt and step_cn
280 * @param[in]
281 * clk_src: i2c clock source
282 * @param[out]
283 * timing_step_cnt: step cnt calculate result
284 * @param[out]
285 * timing_sample_cnt: sample cnt calculate result
286 * @return
287 * 0, set speed successfully.
288 * -EINVAL, Unsupported speed.
289 */
mtk_i2c_calculate_speed(uint clk_src,uint target_speed,uint * timing_step_cnt,uint * timing_sample_cnt)290 static int mtk_i2c_calculate_speed(uint clk_src,
291 uint target_speed,
292 uint *timing_step_cnt,
293 uint *timing_sample_cnt)
294 {
295 uint base_sample_cnt = MAX_SAMPLE_CNT_DIV;
296 uint base_step_cnt;
297 uint max_step_cnt;
298 uint sample_cnt;
299 uint step_cnt;
300 uint opt_div;
301 uint best_mul;
302 uint cnt_mul;
303
304 if (target_speed > MAX_HS_MODE_SPEED)
305 target_speed = MAX_HS_MODE_SPEED;
306
307 if (target_speed > MAX_FS_MODE_SPEED)
308 max_step_cnt = MAX_HS_STEP_CNT_DIV;
309 else
310 max_step_cnt = MAX_STEP_CNT_DIV;
311
312 base_step_cnt = max_step_cnt;
313 /* Find the best combination */
314 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
315 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
316
317 /*
318 * Search for the best pair (sample_cnt, step_cnt) with
319 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
320 * 0 < step_cnt < max_step_cnt
321 * sample_cnt * step_cnt >= opt_div
322 * optimizing for sample_cnt * step_cnt being minimal
323 */
324 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
325 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
326 cnt_mul = step_cnt * sample_cnt;
327 if (step_cnt > max_step_cnt)
328 continue;
329
330 if (cnt_mul < best_mul) {
331 best_mul = cnt_mul;
332 base_sample_cnt = sample_cnt;
333 base_step_cnt = step_cnt;
334 if (best_mul == opt_div)
335 break;
336 }
337 }
338
339 sample_cnt = base_sample_cnt;
340 step_cnt = base_step_cnt;
341
342 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
343 /*
344 * In this case, hardware can't support such
345 * low i2c_bus_freq
346 */
347 debug("Unsupported speed(%uhz)\n", target_speed);
348 return log_msg_ret("calculate speed", -EINVAL);
349 }
350
351 *timing_step_cnt = step_cnt - 1;
352 *timing_sample_cnt = sample_cnt - 1;
353
354 return 0;
355 }
356
357 /*
358 * mtk_i2c_set_speed
359 *
360 * @par Description
361 * Calculate i2c speed and write sample_cnt, step_cnt to TIMING register.
362 * @param[in]
363 * dev: udevice pointer, struct udevice contains i2c source clock,
364 * clock divide and speed.
365 * @return
366 * 0, set speed successfully.\n
367 * error code from mtk_i2c_calculate_speed().
368 */
mtk_i2c_set_speed(struct udevice * dev,uint speed)369 static int mtk_i2c_set_speed(struct udevice *dev, uint speed)
370 {
371 struct mtk_i2c_priv *priv = dev_get_priv(dev);
372 uint high_speed_reg;
373 uint sample_cnt;
374 uint timing_reg;
375 uint step_cnt;
376 uint clk_src;
377 int ret = 0;
378
379 priv->speed = speed;
380 if (mtk_i2c_clk_enable(priv))
381 return log_msg_ret("set_speed enable clk", -1);
382
383 clk_src = clk_get_rate(&priv->clk_main) / I2C_DEFAULT_CLK_DIV;
384 i2c_writel(priv, REG_CLOCK_DIV, (I2C_DEFAULT_CLK_DIV - 1));
385 if (priv->speed > MAX_FS_MODE_SPEED) {
386 /* Set master code speed register */
387 ret = mtk_i2c_calculate_speed(clk_src, MAX_FS_MODE_SPEED,
388 &step_cnt, &sample_cnt);
389 if (ret < 0)
390 goto exit;
391
392 timing_reg = (sample_cnt << TIMING_SAMPLE_OFFSET) | step_cnt;
393 i2c_writel(priv, REG_TIMING, timing_reg);
394 /* Set the high speed mode register */
395 ret = mtk_i2c_calculate_speed(clk_src, priv->speed,
396 &step_cnt, &sample_cnt);
397 if (ret < 0)
398 goto exit;
399
400 high_speed_reg = I2C_TIME_DEFAULT_VALUE |
401 (sample_cnt << HS_SAMPLE_OFFSET) |
402 (step_cnt << HS_STEP_OFFSET);
403 i2c_writel(priv, REG_HS, high_speed_reg);
404 } else {
405 ret = mtk_i2c_calculate_speed(clk_src, priv->speed,
406 &step_cnt, &sample_cnt);
407 if (ret < 0)
408 goto exit;
409
410 timing_reg = (sample_cnt << TIMING_SAMPLE_OFFSET) | step_cnt;
411 /* Disable the high speed transaction */
412 high_speed_reg = I2C_TIME_CLR_VALUE;
413 i2c_writel(priv, REG_TIMING, timing_reg);
414 i2c_writel(priv, REG_HS, high_speed_reg);
415 }
416 exit:
417 if (mtk_i2c_clk_disable(priv))
418 return log_msg_ret("set_speed disable clk", -1);
419
420 return ret;
421 }
422
423 /*
424 * mtk_i2c_do_transfer
425 *
426 * @par Description
427 * Configure i2c register and trigger transfer.
428 * @param[in]
429 * priv: mtk_i2cmtk_i2c_priv pointer, struct mtk_i2c_priv contains register base\n
430 * address, operation mode, interrupt status and i2c driver data.
431 * @param[in]
432 * msgs: i2c_msg pointer, struct i2c_msg contains slave\n
433 * address, operation mode, msg length and data buffer.
434 * @param[in]
435 * num: i2c_msg number.
436 * @param[in]
437 * left_num: left i2c_msg number.
438 * @return
439 * 0, i2c transfer successfully.\n
440 * -ETIMEDOUT, i2c transfer timeout.\n
441 * -EREMOTEIO, i2c transfer ack error.
442 */
mtk_i2c_do_transfer(struct mtk_i2c_priv * priv,struct i2c_msg * msgs,int num,int left_num)443 static int mtk_i2c_do_transfer(struct mtk_i2c_priv *priv,
444 struct i2c_msg *msgs,
445 int num, int left_num)
446 {
447 struct i2c_msg *msg_rx = NULL;
448 uint restart_flag = 0;
449 uint trans_error = 0;
450 uint irq_stat = 0;
451 uint tmo_poll = 0;
452 uint control_reg;
453 bool tmo = false;
454 uint start_reg;
455 uint addr_reg;
456 int ret = 0;
457
458 if (priv->auto_restart)
459 restart_flag = I2C_RS_TRANSFER;
460
461 control_reg = i2c_readl(priv, REG_CONTROL) &
462 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
463
464 if (priv->speed > MAX_FS_MODE_SPEED || num > 1)
465 control_reg |= I2C_CONTROL_RS;
466
467 if (priv->op == I2C_MASTER_WRRD)
468 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
469
470 control_reg |= I2C_CONTROL_DMA_EN;
471 i2c_writel(priv, REG_CONTROL, control_reg);
472
473 /* set start condition */
474 if (priv->speed <= MAX_ST_MODE_SPEED)
475 i2c_writel(priv, REG_EXT_CONF, I2C_ST_START_CON);
476 else
477 i2c_writel(priv, REG_EXT_CONF, I2C_FS_START_CON);
478
479 addr_reg = msgs->addr << 1;
480 if (priv->op == I2C_MASTER_RD)
481 addr_reg |= I2C_M_RD;
482 if (priv->zero_len)
483 i2c_writel(priv, REG_SLAVE_ADDR, addr_reg | TRANS_ADDR_ONLY);
484 else
485 i2c_writel(priv, REG_SLAVE_ADDR, addr_reg);
486
487 /* clear interrupt status */
488 i2c_writel(priv, REG_INTR_STAT, restart_flag | I2C_HS_NACKERR |
489 I2C_ACKERR | I2C_TRANSAC_COMP);
490 i2c_writel(priv, REG_FIFO_ADDR_CLR, I2C_FIFO_ADDR_CLR);
491
492 /* enable interrupt */
493 i2c_writel(priv, REG_INTR_MASK, restart_flag | I2C_HS_NACKERR |
494 I2C_ACKERR | I2C_TRANSAC_COMP);
495
496 /* set transfer and transaction len */
497 if (priv->op == I2C_MASTER_WRRD) {
498 i2c_writel(priv, REG_TRANSFER_LEN, msgs->len);
499 i2c_writel(priv, REG_TRANSFER_LEN_AUX, (msgs + 1)->len);
500 i2c_writel(priv, REG_TRANSAC_LEN, I2C_WRRD_TRANAC_VALUE);
501 } else {
502 i2c_writel(priv, REG_TRANSFER_LEN, msgs->len);
503 i2c_writel(priv, REG_TRANSAC_LEN, num);
504 }
505
506 /* Clear DMA interrupt flag */
507 writel(I2C_DMA_INT_FLAG_NONE, priv->pdmabase + REG_INT_FLAG);
508
509 /* Flush cache for first msg */
510 flush_cache((ulong)msgs->buf, msgs->len);
511
512 /*
513 * prepare buffer data to start transfer
514 * three cases here: read, write, write then read
515 */
516 if (priv->op & I2C_MASTER_WR) {
517 /* Set DMA direction TX (w/ or w/o RX) */
518 writel(I2C_DMA_CON_TX, priv->pdmabase + REG_CON);
519
520 /* Write the tx buffer address to dma register */
521 writel((ulong)msgs->buf, priv->pdmabase + REG_TX_MEM_ADDR);
522 /* Write the tx length to dma register */
523 writel(msgs->len, priv->pdmabase + REG_TX_LEN);
524
525 if (priv->op & I2C_MASTER_RD) {
526 /* write then read */
527 msg_rx = msgs + 1;
528
529 /* Flush cache for second msg */
530 flush_cache((ulong)msg_rx->buf, msg_rx->len);
531 }
532 }
533
534 if (priv->op & I2C_MASTER_RD) {
535 if (!msg_rx) {
536 /* Set DMA direction RX */
537 writel(I2C_DMA_CON_RX, priv->pdmabase + REG_CON);
538
539 msg_rx = msgs;
540 }
541
542 /* Write the rx buffer address to dma register */
543 writel((ulong)msg_rx->buf, priv->pdmabase + REG_RX_MEM_ADDR);
544 /* Write the rx length to dma register */
545 writel(msg_rx->len, priv->pdmabase + REG_RX_LEN);
546 }
547
548 writel(I2C_DMA_START_EN, priv->pdmabase + REG_EN);
549
550 if (!priv->auto_restart) {
551 start_reg = I2C_TRANSAC_START;
552 } else {
553 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
554 if (left_num >= 1)
555 start_reg |= I2C_RS_MUL_CNFG;
556 }
557 i2c_writel(priv, REG_START, start_reg);
558
559 for (;;) {
560 irq_stat = i2c_readl(priv, REG_INTR_STAT);
561
562 /* ignore the first restart irq after the master code */
563 if (priv->ignore_restart_irq && (irq_stat & restart_flag)) {
564 priv->ignore_restart_irq = false;
565 irq_stat = 0;
566 i2c_writel(priv, REG_START, I2C_RS_MUL_CNFG |
567 I2C_RS_MUL_TRIG | I2C_TRANSAC_START);
568 }
569
570 if (irq_stat & (I2C_TRANSAC_COMP | restart_flag)) {
571 tmo = false;
572 if (irq_stat & (I2C_HS_NACKERR | I2C_ACKERR))
573 trans_error = 1;
574
575 break;
576 }
577 udelay(1);
578 if (tmo_poll++ >= TRANSFER_TIMEOUT) {
579 tmo = true;
580 break;
581 }
582 }
583
584 /* clear interrupt mask */
585 i2c_writel(priv, REG_INTR_MASK, ~(restart_flag | I2C_HS_NACKERR |
586 I2C_ACKERR | I2C_TRANSAC_COMP));
587
588 if (!tmo && trans_error != 0) {
589 if (tmo) {
590 ret = -ETIMEDOUT;
591 if (!priv->filter_msg)
592 debug("I2C timeout! addr: 0x%x,\n", msgs->addr);
593 } else {
594 ret = -EREMOTEIO;
595 if (!priv->filter_msg)
596 debug("I2C ACKERR! addr: 0x%x,IRQ:0x%x\n",
597 msgs->addr, irq_stat);
598 }
599 mtk_i2c_init_hw(priv);
600 }
601
602 return ret;
603 }
604
605 /*
606 * mtk_i2c_transfer
607 *
608 * @par Description
609 * Common i2c transfer API. Set i2c transfer mode according to i2c_msg\n
610 * information, then call mtk_i2c_do_transfer() to configure i2c register\n
611 * and trigger transfer.
612 * @param[in]
613 * dev: udevice pointer, struct udevice contains struct mtk_i2c_priv, \n
614 * struct mtk_i2c_priv contains register base\n
615 * address, operation mode, interrupt status and i2c driver data.
616 * @param[in]
617 * msgs: i2c_msg pointer, struct i2c_msg contains slave\n
618 * address, operation mode, msg length and data buffer.
619 * @param[in]
620 * num: i2c_msg number.
621 * @return
622 * i2c_msg number, i2c transfer successfully.\n
623 * -EINVAL, msg length is more than 16\n
624 * use DMA MODE or slave address more than 0x7f.\n
625 * error code from mtk_i2c_init_base().\n
626 * error code from mtk_i2c_set_speed().\n
627 * error code from mtk_i2c_do_transfer().
628 */
mtk_i2c_transfer(struct udevice * dev,struct i2c_msg * msg,int nmsgs)629 static int mtk_i2c_transfer(struct udevice *dev, struct i2c_msg *msg,
630 int nmsgs)
631 {
632 struct mtk_i2c_priv *priv = dev_get_priv(dev);
633 int left_num;
634 uint num_cnt;
635 int ret;
636
637 priv->auto_restart = true;
638 left_num = nmsgs;
639 if (mtk_i2c_clk_enable(priv))
640 return log_msg_ret("transfer enable clk", -1);
641
642 for (num_cnt = 0; num_cnt < nmsgs; num_cnt++) {
643 if (((msg + num_cnt)->addr) > MAX_I2C_ADDR) {
644 ret = -EINVAL;
645 goto err_exit;
646 }
647 if ((msg + num_cnt)->len > MAX_I2C_LEN) {
648 ret = -EINVAL;
649 goto err_exit;
650 }
651 }
652
653 /* check if we can skip restart and optimize using WRRD mode */
654 if (priv->auto_restart && nmsgs == 2) {
655 if (!(msg[0].flags & I2C_M_RD) && (msg[1].flags & I2C_M_RD) &&
656 msg[0].addr == msg[1].addr) {
657 priv->auto_restart = false;
658 }
659 }
660
661 if (priv->auto_restart && nmsgs >= 2 && priv->speed > MAX_FS_MODE_SPEED)
662 /* ignore the first restart irq after the master code,
663 * otherwise the first transfer will be discarded.
664 */
665 priv->ignore_restart_irq = true;
666 else
667 priv->ignore_restart_irq = false;
668
669 while (left_num--) {
670 /* transfer slave address only to support devices detect */
671 if (!msg->buf)
672 priv->zero_len = true;
673 else
674 priv->zero_len = false;
675
676 if (msg->flags & I2C_M_RD)
677 priv->op = I2C_MASTER_RD;
678 else
679 priv->op = I2C_MASTER_WR;
680
681 if (!priv->auto_restart) {
682 if (nmsgs > 1) {
683 /* combined two messages into one transaction */
684 priv->op = I2C_MASTER_WRRD;
685 left_num--;
686 }
687 }
688 ret = mtk_i2c_do_transfer(priv, msg, nmsgs, left_num);
689 if (ret < 0)
690 goto err_exit;
691 msg++;
692 }
693 ret = 0;
694
695 err_exit:
696 if (mtk_i2c_clk_disable(priv))
697 return log_msg_ret("transfer disable clk", -1);
698
699 return ret;
700 }
701
mtk_i2c_of_to_plat(struct udevice * dev)702 static int mtk_i2c_of_to_plat(struct udevice *dev)
703 {
704 struct mtk_i2c_priv *priv = dev_get_priv(dev);
705 int ret;
706
707 priv->base = dev_remap_addr_index(dev, 0);
708 priv->pdmabase = dev_remap_addr_index(dev, 1);
709 ret = clk_get_by_index(dev, 0, &priv->clk_main);
710 if (ret)
711 return log_msg_ret("clk_get_by_index 0", ret);
712
713 ret = clk_get_by_index(dev, 1, &priv->clk_dma);
714
715 return ret;
716 }
717
mtk_i2c_probe(struct udevice * dev)718 static int mtk_i2c_probe(struct udevice *dev)
719 {
720 struct mtk_i2c_priv *priv = dev_get_priv(dev);
721
722 priv->soc_data = (struct mtk_i2c_soc_data *)dev_get_driver_data(dev);
723
724 if (mtk_i2c_clk_enable(priv))
725 return log_msg_ret("probe enable clk", -1);
726
727 mtk_i2c_init_hw(priv);
728
729 if (mtk_i2c_clk_disable(priv))
730 return log_msg_ret("probe disable clk", -1);
731
732 return 0;
733 }
734
mtk_i2c_deblock(struct udevice * dev)735 static int mtk_i2c_deblock(struct udevice *dev)
736 {
737 struct mtk_i2c_priv *priv = dev_get_priv(dev);
738
739 if (mtk_i2c_clk_enable(priv))
740 return log_msg_ret("deblock enable clk", -1);
741
742 mtk_i2c_init_hw(priv);
743
744 if (mtk_i2c_clk_disable(priv))
745 return log_msg_ret("deblock disable clk", -1);
746
747 return 0;
748 }
749
750 static const struct mtk_i2c_soc_data mt76xx_soc_data = {
751 .regs = mt_i2c_regs_v1,
752 .dma_sync = 0,
753 };
754
755 static const struct mtk_i2c_soc_data mt7981_soc_data = {
756 .regs = mt_i2c_regs_v1,
757 .dma_sync = 1,
758 };
759
760 static const struct mtk_i2c_soc_data mt7986_soc_data = {
761 .regs = mt_i2c_regs_v1,
762 .dma_sync = 1,
763 };
764
765 static const struct mtk_i2c_soc_data mt8183_soc_data = {
766 .regs = mt_i2c_regs_v2,
767 .dma_sync = 1,
768 };
769
770 static const struct mtk_i2c_soc_data mt8518_soc_data = {
771 .regs = mt_i2c_regs_v1,
772 .dma_sync = 0,
773 };
774
775 static const struct mtk_i2c_soc_data mt8512_soc_data = {
776 .regs = mt_i2c_regs_v1,
777 .dma_sync = 1,
778 };
779
780 static const struct dm_i2c_ops mtk_i2c_ops = {
781 .xfer = mtk_i2c_transfer,
782 .set_bus_speed = mtk_i2c_set_speed,
783 .deblock = mtk_i2c_deblock,
784 };
785
786 static const struct udevice_id mtk_i2c_ids[] = {
787 {
788 .compatible = "mediatek,mt7622-i2c",
789 .data = (ulong)&mt76xx_soc_data,
790 }, {
791 .compatible = "mediatek,mt7623-i2c",
792 .data = (ulong)&mt76xx_soc_data,
793 }, {
794 .compatible = "mediatek,mt7629-i2c",
795 .data = (ulong)&mt76xx_soc_data,
796 }, {
797 .compatible = "mediatek,mt7981-i2c",
798 .data = (ulong)&mt7981_soc_data,
799 }, {
800 .compatible = "mediatek,mt7986-i2c",
801 .data = (ulong)&mt7986_soc_data,
802 }, {
803 .compatible = "mediatek,mt8183-i2c",
804 .data = (ulong)&mt8183_soc_data,
805 }, {
806 .compatible = "mediatek,mt8512-i2c",
807 .data = (ulong)&mt8512_soc_data,
808 }, {
809 .compatible = "mediatek,mt8518-i2c",
810 .data = (ulong)&mt8518_soc_data,
811 }
812 };
813
814 U_BOOT_DRIVER(mtk_i2c) = {
815 .name = "mtk_i2c",
816 .id = UCLASS_I2C,
817 .of_match = mtk_i2c_ids,
818 .of_to_plat = mtk_i2c_of_to_plat,
819 .probe = mtk_i2c_probe,
820 .priv_auto = sizeof(struct mtk_i2c_priv),
821 .ops = &mtk_i2c_ops,
822 };
823