1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000
4 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
5 *
6 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2003 Pengutronix e.K.
10 * Robert Schwebel <r.schwebel@pengutronix.de>
11 *
12 * (C) Copyright 2011 Marvell Inc.
13 * Lei Wen <leiwen@marvell.com>
14 *
15 * Back ported to the 8xx platform (from the 8260 platform) by
16 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
17 */
18
19 #include <common.h>
20 #include <dm.h>
21 #include <i2c.h>
22 #include <log.h>
23 #include <asm/io.h>
24 #include <linux/delay.h>
25 #include "mv_i2c.h"
26
27 /* All transfers are described by this data structure */
28 struct mv_i2c_msg {
29 u8 condition;
30 u8 acknack;
31 u8 direction;
32 u8 data;
33 };
34
35 #ifdef CONFIG_ARMADA_3700
36 /* Armada 3700 has no padding between the registers */
37 struct mv_i2c {
38 u32 ibmr;
39 u32 idbr;
40 u32 icr;
41 u32 isr;
42 u32 isar;
43 };
44 #else
45 struct mv_i2c {
46 u32 ibmr;
47 u32 pad0;
48 u32 idbr;
49 u32 pad1;
50 u32 icr;
51 u32 pad2;
52 u32 isr;
53 u32 pad3;
54 u32 isar;
55 };
56 #endif
57
58 /*
59 * Dummy implementation that can be overwritten by a board
60 * specific function
61 */
i2c_clk_enable(void)62 __weak void i2c_clk_enable(void)
63 {
64 }
65
66 /*
67 * i2c_reset: - reset the host controller
68 *
69 */
i2c_reset(struct mv_i2c * base)70 static void i2c_reset(struct mv_i2c *base)
71 {
72 u32 icr_mode;
73
74 /* Save bus mode (standard or fast speed) for later use */
75 icr_mode = readl(&base->icr) & ICR_MODE_MASK;
76 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
77 writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */
78 udelay(100);
79 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
80
81 i2c_clk_enable();
82
83 writel(0x0, &base->isar); /* set our slave address */
84 /* set control reg values */
85 writel(I2C_ICR_INIT | icr_mode, &base->icr);
86 writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */
87 writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */
88 udelay(100);
89 }
90
91 /*
92 * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
93 * are set and cleared
94 *
95 * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
96 */
i2c_isr_set_cleared(struct mv_i2c * base,unsigned long set_mask,unsigned long cleared_mask)97 static int i2c_isr_set_cleared(struct mv_i2c *base, unsigned long set_mask,
98 unsigned long cleared_mask)
99 {
100 int timeout = 1000, isr;
101
102 do {
103 isr = readl(&base->isr);
104 udelay(10);
105 if (timeout-- < 0)
106 return 0;
107 } while (((isr & set_mask) != set_mask)
108 || ((isr & cleared_mask) != 0));
109
110 return 1;
111 }
112
113 /*
114 * i2c_transfer: - Transfer one byte over the i2c bus
115 *
116 * This function can tranfer a byte over the i2c bus in both directions.
117 * It is used by the public API functions.
118 *
119 * @return: 0: transfer successful
120 * -1: message is empty
121 * -2: transmit timeout
122 * -3: ACK missing
123 * -4: receive timeout
124 * -5: illegal parameters
125 * -6: bus is busy and couldn't be aquired
126 */
i2c_transfer(struct mv_i2c * base,struct mv_i2c_msg * msg)127 static int i2c_transfer(struct mv_i2c *base, struct mv_i2c_msg *msg)
128 {
129 int ret;
130
131 if (!msg)
132 goto transfer_error_msg_empty;
133
134 switch (msg->direction) {
135 case I2C_WRITE:
136 /* check if bus is not busy */
137 if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
138 goto transfer_error_bus_busy;
139
140 /* start transmission */
141 writel(readl(&base->icr) & ~ICR_START, &base->icr);
142 writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
143 writel(msg->data, &base->idbr);
144 if (msg->condition == I2C_COND_START)
145 writel(readl(&base->icr) | ICR_START, &base->icr);
146 if (msg->condition == I2C_COND_STOP)
147 writel(readl(&base->icr) | ICR_STOP, &base->icr);
148 if (msg->acknack == I2C_ACKNAK_SENDNAK)
149 writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
150 if (msg->acknack == I2C_ACKNAK_SENDACK)
151 writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
152 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
153 writel(readl(&base->icr) | ICR_TB, &base->icr);
154
155 /* transmit register empty? */
156 if (!i2c_isr_set_cleared(base, ISR_ITE, 0))
157 goto transfer_error_transmit_timeout;
158
159 /* clear 'transmit empty' state */
160 writel(readl(&base->isr) | ISR_ITE, &base->isr);
161
162 /* wait for ACK from slave */
163 if (msg->acknack == I2C_ACKNAK_WAITACK)
164 if (!i2c_isr_set_cleared(base, 0, ISR_ACKNAK))
165 goto transfer_error_ack_missing;
166 break;
167
168 case I2C_READ:
169
170 /* check if bus is not busy */
171 if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
172 goto transfer_error_bus_busy;
173
174 /* start receive */
175 writel(readl(&base->icr) & ~ICR_START, &base->icr);
176 writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
177 if (msg->condition == I2C_COND_START)
178 writel(readl(&base->icr) | ICR_START, &base->icr);
179 if (msg->condition == I2C_COND_STOP)
180 writel(readl(&base->icr) | ICR_STOP, &base->icr);
181 if (msg->acknack == I2C_ACKNAK_SENDNAK)
182 writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
183 if (msg->acknack == I2C_ACKNAK_SENDACK)
184 writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
185 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
186 writel(readl(&base->icr) | ICR_TB, &base->icr);
187
188 /* receive register full? */
189 if (!i2c_isr_set_cleared(base, ISR_IRF, 0))
190 goto transfer_error_receive_timeout;
191
192 msg->data = readl(&base->idbr);
193
194 /* clear 'receive empty' state */
195 writel(readl(&base->isr) | ISR_IRF, &base->isr);
196 break;
197 default:
198 goto transfer_error_illegal_param;
199 }
200
201 return 0;
202
203 transfer_error_msg_empty:
204 debug("i2c_transfer: error: 'msg' is empty\n");
205 ret = -1;
206 goto i2c_transfer_finish;
207
208 transfer_error_transmit_timeout:
209 debug("i2c_transfer: error: transmit timeout\n");
210 ret = -2;
211 goto i2c_transfer_finish;
212
213 transfer_error_ack_missing:
214 debug("i2c_transfer: error: ACK missing\n");
215 ret = -3;
216 goto i2c_transfer_finish;
217
218 transfer_error_receive_timeout:
219 debug("i2c_transfer: error: receive timeout\n");
220 ret = -4;
221 goto i2c_transfer_finish;
222
223 transfer_error_illegal_param:
224 debug("i2c_transfer: error: illegal parameters\n");
225 ret = -5;
226 goto i2c_transfer_finish;
227
228 transfer_error_bus_busy:
229 debug("i2c_transfer: error: bus is busy\n");
230 ret = -6;
231 goto i2c_transfer_finish;
232
233 i2c_transfer_finish:
234 debug("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr));
235 i2c_reset(base);
236 return ret;
237 }
238
__i2c_read(struct mv_i2c * base,uchar chip,u8 * addr,int alen,uchar * buffer,int len)239 static int __i2c_read(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
240 uchar *buffer, int len)
241 {
242 struct mv_i2c_msg msg;
243
244 debug("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
245 "len=0x%02x)\n", chip, *addr, alen, len);
246
247 if (len == 0) {
248 printf("reading zero byte is invalid\n");
249 return -EINVAL;
250 }
251
252 i2c_reset(base);
253
254 /* dummy chip address write */
255 debug("i2c_read: dummy chip address write\n");
256 msg.condition = I2C_COND_START;
257 msg.acknack = I2C_ACKNAK_WAITACK;
258 msg.direction = I2C_WRITE;
259 msg.data = (chip << 1);
260 msg.data &= 0xFE;
261 if (i2c_transfer(base, &msg))
262 return -1;
263
264 /*
265 * send memory address bytes;
266 * alen defines how much bytes we have to send.
267 */
268 while (--alen >= 0) {
269 debug("i2c_read: send address byte %02x (alen=%d)\n",
270 *addr, alen);
271 msg.condition = I2C_COND_NORMAL;
272 msg.acknack = I2C_ACKNAK_WAITACK;
273 msg.direction = I2C_WRITE;
274 msg.data = addr[alen];
275 if (i2c_transfer(base, &msg))
276 return -1;
277 }
278
279 /* start read sequence */
280 debug("i2c_read: start read sequence\n");
281 msg.condition = I2C_COND_START;
282 msg.acknack = I2C_ACKNAK_WAITACK;
283 msg.direction = I2C_WRITE;
284 msg.data = (chip << 1);
285 msg.data |= 0x01;
286 if (i2c_transfer(base, &msg))
287 return -1;
288
289 /* read bytes; send NACK at last byte */
290 while (len--) {
291 if (len == 0) {
292 msg.condition = I2C_COND_STOP;
293 msg.acknack = I2C_ACKNAK_SENDNAK;
294 } else {
295 msg.condition = I2C_COND_NORMAL;
296 msg.acknack = I2C_ACKNAK_SENDACK;
297 }
298
299 msg.direction = I2C_READ;
300 msg.data = 0x00;
301 if (i2c_transfer(base, &msg))
302 return -1;
303
304 *buffer = msg.data;
305 debug("i2c_read: reading byte (%p)=0x%02x\n",
306 buffer, *buffer);
307 buffer++;
308 }
309
310 i2c_reset(base);
311
312 return 0;
313 }
314
__i2c_write(struct mv_i2c * base,uchar chip,u8 * addr,int alen,uchar * buffer,int len)315 static int __i2c_write(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
316 uchar *buffer, int len)
317 {
318 struct mv_i2c_msg msg;
319
320 debug("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
321 "len=0x%02x)\n", chip, *addr, alen, len);
322
323 i2c_reset(base);
324
325 /* chip address write */
326 debug("i2c_write: chip address write\n");
327 msg.condition = I2C_COND_START;
328 msg.acknack = I2C_ACKNAK_WAITACK;
329 msg.direction = I2C_WRITE;
330 msg.data = (chip << 1);
331 msg.data &= 0xFE;
332 if (i2c_transfer(base, &msg))
333 return -1;
334
335 /*
336 * send memory address bytes;
337 * alen defines how much bytes we have to send.
338 */
339 while (--alen >= 0) {
340 debug("i2c_read: send address byte %02x (alen=%d)\n",
341 *addr, alen);
342 msg.condition = I2C_COND_NORMAL;
343 msg.acknack = I2C_ACKNAK_WAITACK;
344 msg.direction = I2C_WRITE;
345 msg.data = addr[alen];
346 if (i2c_transfer(base, &msg))
347 return -1;
348 }
349
350 /* write bytes; send NACK at last byte */
351 while (len--) {
352 debug("i2c_write: writing byte (%p)=0x%02x\n",
353 buffer, *buffer);
354
355 if (len == 0)
356 msg.condition = I2C_COND_STOP;
357 else
358 msg.condition = I2C_COND_NORMAL;
359
360 msg.acknack = I2C_ACKNAK_WAITACK;
361 msg.direction = I2C_WRITE;
362 msg.data = *(buffer++);
363
364 if (i2c_transfer(base, &msg))
365 return -1;
366 }
367
368 i2c_reset(base);
369
370 return 0;
371 }
372
373 #if !CONFIG_IS_ENABLED(DM_I2C)
374
375 static struct mv_i2c *base_glob;
376
377 /* API Functions */
i2c_init(int speed,int slaveaddr)378 void i2c_init(int speed, int slaveaddr)
379 {
380 u32 val;
381
382 base_glob = (struct mv_i2c *)CONFIG_MV_I2C_REG;
383
384 if (speed > I2C_SPEED_STANDARD_RATE)
385 val = ICR_FM;
386 else
387 val = ICR_SM;
388 clrsetbits_le32(&base_glob->icr, ICR_MODE_MASK, val);
389 }
390
__i2c_probe_chip(struct mv_i2c * base,uchar chip)391 static int __i2c_probe_chip(struct mv_i2c *base, uchar chip)
392 {
393 struct mv_i2c_msg msg;
394
395 i2c_reset(base);
396
397 msg.condition = I2C_COND_START;
398 msg.acknack = I2C_ACKNAK_WAITACK;
399 msg.direction = I2C_WRITE;
400 msg.data = (chip << 1) + 1;
401 if (i2c_transfer(base, &msg))
402 return -1;
403
404 msg.condition = I2C_COND_STOP;
405 msg.acknack = I2C_ACKNAK_SENDNAK;
406 msg.direction = I2C_READ;
407 msg.data = 0x00;
408 if (i2c_transfer(base, &msg))
409 return -1;
410
411 return 0;
412 }
413
414 /*
415 * i2c_probe: - Test if a chip answers for a given i2c address
416 *
417 * @chip: address of the chip which is searched for
418 * @return: 0 if a chip was found, -1 otherwhise
419 */
i2c_probe(uchar chip)420 int i2c_probe(uchar chip)
421 {
422 return __i2c_probe_chip(base_glob, chip);
423 }
424
425 /*
426 * i2c_read: - Read multiple bytes from an i2c device
427 *
428 * The higher level routines take into account that this function is only
429 * called with len < page length of the device (see configuration file)
430 *
431 * @chip: address of the chip which is to be read
432 * @addr: i2c data address within the chip
433 * @alen: length of the i2c data address (1..2 bytes)
434 * @buffer: where to write the data
435 * @len: how much byte do we want to read
436 * @return: 0 in case of success
437 */
i2c_read(uchar chip,uint addr,int alen,uchar * buffer,int len)438 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
439 {
440 u8 addr_bytes[4];
441
442 addr_bytes[0] = (addr >> 0) & 0xFF;
443 addr_bytes[1] = (addr >> 8) & 0xFF;
444 addr_bytes[2] = (addr >> 16) & 0xFF;
445 addr_bytes[3] = (addr >> 24) & 0xFF;
446
447 return __i2c_read(base_glob, chip, addr_bytes, alen, buffer, len);
448 }
449
450 /*
451 * i2c_write: - Write multiple bytes to an i2c device
452 *
453 * The higher level routines take into account that this function is only
454 * called with len < page length of the device (see configuration file)
455 *
456 * @chip: address of the chip which is to be written
457 * @addr: i2c data address within the chip
458 * @alen: length of the i2c data address (1..2 bytes)
459 * @buffer: where to find the data to be written
460 * @len: how much byte do we want to read
461 * @return: 0 in case of success
462 */
i2c_write(uchar chip,uint addr,int alen,uchar * buffer,int len)463 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
464 {
465 u8 addr_bytes[4];
466
467 addr_bytes[0] = (addr >> 0) & 0xFF;
468 addr_bytes[1] = (addr >> 8) & 0xFF;
469 addr_bytes[2] = (addr >> 16) & 0xFF;
470 addr_bytes[3] = (addr >> 24) & 0xFF;
471
472 return __i2c_write(base_glob, chip, addr_bytes, alen, buffer, len);
473 }
474
475 #else /* CONFIG_DM_I2C */
476
477 struct mv_i2c_priv {
478 struct mv_i2c *base;
479 };
480
mv_i2c_xfer(struct udevice * bus,struct i2c_msg * msg,int nmsgs)481 static int mv_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
482 {
483 struct mv_i2c_priv *i2c = dev_get_priv(bus);
484 struct i2c_msg *dmsg, *omsg, dummy;
485
486 memset(&dummy, 0, sizeof(struct i2c_msg));
487
488 /*
489 * We expect either two messages (one with an offset and one with the
490 * actual data) or one message (just data or offset/data combined)
491 */
492 if (nmsgs > 2 || nmsgs == 0) {
493 debug("%s: Only one or two messages are supported.", __func__);
494 return -1;
495 }
496
497 omsg = nmsgs == 1 ? &dummy : msg;
498 dmsg = nmsgs == 1 ? msg : msg + 1;
499
500 if (dmsg->flags & I2C_M_RD)
501 return __i2c_read(i2c->base, dmsg->addr, omsg->buf,
502 omsg->len, dmsg->buf, dmsg->len);
503 else
504 return __i2c_write(i2c->base, dmsg->addr, omsg->buf,
505 omsg->len, dmsg->buf, dmsg->len);
506 }
507
mv_i2c_set_bus_speed(struct udevice * bus,unsigned int speed)508 static int mv_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
509 {
510 struct mv_i2c_priv *priv = dev_get_priv(bus);
511 u32 val;
512
513 if (speed > I2C_SPEED_STANDARD_RATE)
514 val = ICR_FM;
515 else
516 val = ICR_SM;
517 clrsetbits_le32(&priv->base->icr, ICR_MODE_MASK, val);
518
519 return 0;
520 }
521
mv_i2c_probe(struct udevice * bus)522 static int mv_i2c_probe(struct udevice *bus)
523 {
524 struct mv_i2c_priv *priv = dev_get_priv(bus);
525
526 priv->base = dev_read_addr_ptr(bus);
527
528 return 0;
529 }
530
531 static const struct dm_i2c_ops mv_i2c_ops = {
532 .xfer = mv_i2c_xfer,
533 .set_bus_speed = mv_i2c_set_bus_speed,
534 };
535
536 static const struct udevice_id mv_i2c_ids[] = {
537 { .compatible = "marvell,armada-3700-i2c" },
538 { }
539 };
540
541 U_BOOT_DRIVER(i2c_mv) = {
542 .name = "i2c_mv",
543 .id = UCLASS_I2C,
544 .of_match = mv_i2c_ids,
545 .probe = mv_i2c_probe,
546 .priv_auto = sizeof(struct mv_i2c_priv),
547 .ops = &mv_i2c_ops,
548 };
549 #endif /* CONFIG_DM_I2C */
550