1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Atmel SMC (Static Memory Controller) helper functions.
4 *
5 * Copyright (C) 2022 Microchip Technology Inc.
6 * Copyright (C) 2017 Free Electrons
7 *
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
9 */
10
11 #include <clk.h>
12 #include <dm/device.h>
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/mfd/syscon/atmel-smc.h>
16 #include <linux/string.h>
17
18 /**
19 * atmel_smc_cs_conf_init - initialize a SMC CS conf
20 * @conf: the SMC CS conf to initialize
21 *
22 * Set all fields to 0 so that one can start defining a new config.
23 */
atmel_smc_cs_conf_init(struct atmel_smc_cs_conf * conf)24 void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf)
25 {
26 memset(conf, 0, sizeof(*conf));
27 }
28 EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_init);
29
30 /**
31 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
32 * format expected by the SMC engine
33 * @ncycles: number of MCK clk cycles
34 * @msbpos: position of the MSB part of the timing field
35 * @msbwidth: width of the MSB part of the timing field
36 * @msbfactor: factor applied to the MSB
37 * @encodedval: param used to store the encoding result
38 *
39 * This function encodes the @ncycles value as described in the datasheet
40 * (section "SMC Setup/Pulse/Cycle/Timings Register"). This is a generic
41 * helper which called with different parameter depending on the encoding
42 * scheme.
43 *
44 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
45 * the encodedval is contains the maximum val. Otherwise, 0 is returned.
46 */
atmel_smc_cs_encode_ncycles(unsigned int ncycles,unsigned int msbpos,unsigned int msbwidth,unsigned int msbfactor,unsigned int * encodedval)47 static int atmel_smc_cs_encode_ncycles(unsigned int ncycles,
48 unsigned int msbpos,
49 unsigned int msbwidth,
50 unsigned int msbfactor,
51 unsigned int *encodedval)
52 {
53 unsigned int lsbmask = GENMASK(msbpos - 1, 0);
54 unsigned int msbmask = GENMASK(msbwidth - 1, 0);
55 unsigned int msb, lsb;
56 int ret = 0;
57
58 msb = ncycles / msbfactor;
59 lsb = ncycles % msbfactor;
60
61 if (lsb > lsbmask) {
62 lsb = 0;
63 msb++;
64 }
65
66 /*
67 * Let's just put the maximum we can if the requested setting does
68 * not fit in the register field.
69 * We still return -ERANGE in case the caller cares.
70 */
71 if (msb > msbmask) {
72 msb = msbmask;
73 lsb = lsbmask;
74 ret = -ERANGE;
75 }
76
77 *encodedval = (msb << msbpos) | lsb;
78
79 return ret;
80 }
81
82 /**
83 * atmel_smc_cs_conf_set_timing - set the SMC CS conf Txx parameter to a
84 * specific value
85 * @conf: SMC CS conf descriptor
86 * @shift: the position of the Txx field in the TIMINGS register
87 * @ncycles: value (expressed in MCK clk cycles) to assign to this Txx
88 * parameter
89 *
90 * This function encodes the @ncycles value as described in the datasheet
91 * (section "SMC Timings Register"), and then stores the result in the
92 * @conf->timings field at @shift position.
93 *
94 * Returns -EINVAL if shift is invalid, -ERANGE if ncycles does not fit in
95 * the field, and 0 otherwise.
96 */
atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf * conf,unsigned int shift,unsigned int ncycles)97 int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf,
98 unsigned int shift, unsigned int ncycles)
99 {
100 unsigned int val;
101 int ret;
102
103 if (shift != ATMEL_HSMC_TIMINGS_TCLR_SHIFT &&
104 shift != ATMEL_HSMC_TIMINGS_TADL_SHIFT &&
105 shift != ATMEL_HSMC_TIMINGS_TAR_SHIFT &&
106 shift != ATMEL_HSMC_TIMINGS_TRR_SHIFT &&
107 shift != ATMEL_HSMC_TIMINGS_TWB_SHIFT)
108 return -EINVAL;
109
110 /*
111 * The formula described in atmel datasheets (section "HSMC Timings
112 * Register"):
113 *
114 * ncycles = (Txx[3] * 64) + Txx[2:0]
115 */
116 ret = atmel_smc_cs_encode_ncycles(ncycles, 3, 1, 64, &val);
117 conf->timings &= ~GENMASK(shift + 3, shift);
118 conf->timings |= val << shift;
119
120 return ret;
121 }
122 EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_timing);
123
124 /**
125 * atmel_smc_cs_conf_set_setup - set the SMC CS conf xx_SETUP parameter to a
126 * specific value
127 * @conf: SMC CS conf descriptor
128 * @shift: the position of the xx_SETUP field in the SETUP register
129 * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_SETUP
130 * parameter
131 *
132 * This function encodes the @ncycles value as described in the datasheet
133 * (section "SMC Setup Register"), and then stores the result in the
134 * @conf->setup field at @shift position.
135 *
136 * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
137 * the field, and 0 otherwise.
138 */
atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf * conf,unsigned int shift,unsigned int ncycles)139 int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf,
140 unsigned int shift, unsigned int ncycles)
141 {
142 unsigned int val;
143 int ret;
144
145 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&
146 shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)
147 return -EINVAL;
148
149 /*
150 * The formula described in atmel datasheets (section "SMC Setup
151 * Register"):
152 *
153 * ncycles = (128 * xx_SETUP[5]) + xx_SETUP[4:0]
154 */
155 ret = atmel_smc_cs_encode_ncycles(ncycles, 5, 1, 128, &val);
156 conf->setup &= ~GENMASK(shift + 7, shift);
157 conf->setup |= val << shift;
158
159 return ret;
160 }
161 EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_setup);
162
163 /**
164 * atmel_smc_cs_conf_set_pulse - set the SMC CS conf xx_PULSE parameter to a
165 * specific value
166 * @conf: SMC CS conf descriptor
167 * @shift: the position of the xx_PULSE field in the PULSE register
168 * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_PULSE
169 * parameter
170 *
171 * This function encodes the @ncycles value as described in the datasheet
172 * (section "SMC Pulse Register"), and then stores the result in the
173 * @conf->setup field at @shift position.
174 *
175 * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
176 * the field, and 0 otherwise.
177 */
atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf * conf,unsigned int shift,unsigned int ncycles)178 int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf,
179 unsigned int shift, unsigned int ncycles)
180 {
181 unsigned int val;
182 int ret;
183
184 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&
185 shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)
186 return -EINVAL;
187
188 /*
189 * The formula described in atmel datasheets (section "SMC Pulse
190 * Register"):
191 *
192 * ncycles = (256 * xx_PULSE[6]) + xx_PULSE[5:0]
193 */
194 ret = atmel_smc_cs_encode_ncycles(ncycles, 6, 1, 256, &val);
195 conf->pulse &= ~GENMASK(shift + 7, shift);
196 conf->pulse |= val << shift;
197
198 return ret;
199 }
200 EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_pulse);
201
202 /**
203 * atmel_smc_cs_conf_set_cycle - set the SMC CS conf xx_CYCLE parameter to a
204 * specific value
205 * @conf: SMC CS conf descriptor
206 * @shift: the position of the xx_CYCLE field in the CYCLE register
207 * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_CYCLE
208 * parameter
209 *
210 * This function encodes the @ncycles value as described in the datasheet
211 * (section "SMC Cycle Register"), and then stores the result in the
212 * @conf->setup field at @shift position.
213 *
214 * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
215 * the field, and 0 otherwise.
216 */
atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf * conf,unsigned int shift,unsigned int ncycles)217 int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf,
218 unsigned int shift, unsigned int ncycles)
219 {
220 unsigned int val;
221 int ret;
222
223 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NRD_SHIFT)
224 return -EINVAL;
225
226 /*
227 * The formula described in atmel datasheets (section "SMC Cycle
228 * Register"):
229 *
230 * ncycles = (xx_CYCLE[8:7] * 256) + xx_CYCLE[6:0]
231 */
232 ret = atmel_smc_cs_encode_ncycles(ncycles, 7, 2, 256, &val);
233 conf->cycle &= ~GENMASK(shift + 15, shift);
234 conf->cycle |= val << shift;
235
236 return ret;
237 }
238 EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_cycle);
239
240 /**
241 * atmel_smc_cs_conf_apply - apply an SMC CS conf
242 * @regmap: the SMC regmap
243 * @cs: the CS id
244 * @conf: the SMC CS conf to apply
245 *
246 * Applies an SMC CS configuration.
247 * Only valid on at91sam9/avr32 SoCs.
248 */
atmel_smc_cs_conf_apply(struct regmap * regmap,int cs,const struct atmel_smc_cs_conf * conf)249 void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs,
250 const struct atmel_smc_cs_conf *conf)
251 {
252 regmap_write(regmap, ATMEL_SMC_SETUP(cs), conf->setup);
253 regmap_write(regmap, ATMEL_SMC_PULSE(cs), conf->pulse);
254 regmap_write(regmap, ATMEL_SMC_CYCLE(cs), conf->cycle);
255 regmap_write(regmap, ATMEL_SMC_MODE(cs), conf->mode);
256 }
257 EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_apply);
258
259 /**
260 * atmel_hsmc_cs_conf_apply - apply an SMC CS conf
261 * @regmap: the HSMC regmap
262 * @cs: the CS id
263 * @layout: the layout of registers
264 * @conf: the SMC CS conf to apply
265 *
266 * Applies an SMC CS configuration.
267 * Only valid on post-sama5 SoCs.
268 */
atmel_hsmc_cs_conf_apply(struct regmap * regmap,const struct atmel_hsmc_reg_layout * layout,int cs,const struct atmel_smc_cs_conf * conf)269 void atmel_hsmc_cs_conf_apply(struct regmap *regmap,
270 const struct atmel_hsmc_reg_layout *layout,
271 int cs, const struct atmel_smc_cs_conf *conf)
272 {
273 regmap_write(regmap, ATMEL_HSMC_SETUP(layout, cs), conf->setup);
274 regmap_write(regmap, ATMEL_HSMC_PULSE(layout, cs), conf->pulse);
275 regmap_write(regmap, ATMEL_HSMC_CYCLE(layout, cs), conf->cycle);
276 regmap_write(regmap, ATMEL_HSMC_TIMINGS(layout, cs), conf->timings);
277 regmap_write(regmap, ATMEL_HSMC_MODE(layout, cs), conf->mode);
278 }
279 EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_apply);
280
281 /**
282 * atmel_smc_cs_conf_get - retrieve the current SMC CS conf
283 * @regmap: the SMC regmap
284 * @cs: the CS id
285 * @conf: the SMC CS conf object to store the current conf
286 *
287 * Retrieve the SMC CS configuration.
288 * Only valid on at91sam9/avr32 SoCs.
289 */
atmel_smc_cs_conf_get(struct regmap * regmap,int cs,struct atmel_smc_cs_conf * conf)290 void atmel_smc_cs_conf_get(struct regmap *regmap, int cs,
291 struct atmel_smc_cs_conf *conf)
292 {
293 regmap_read(regmap, ATMEL_SMC_SETUP(cs), &conf->setup);
294 regmap_read(regmap, ATMEL_SMC_PULSE(cs), &conf->pulse);
295 regmap_read(regmap, ATMEL_SMC_CYCLE(cs), &conf->cycle);
296 regmap_read(regmap, ATMEL_SMC_MODE(cs), &conf->mode);
297 }
298 EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_get);
299
300 /**
301 * atmel_hsmc_cs_conf_get - retrieve the current SMC CS conf
302 * @regmap: the HSMC regmap
303 * @cs: the CS id
304 * @layout: the layout of registers
305 * @conf: the SMC CS conf object to store the current conf
306 *
307 * Retrieve the SMC CS configuration.
308 * Only valid on post-sama5 SoCs.
309 */
atmel_hsmc_cs_conf_get(struct regmap * regmap,const struct atmel_hsmc_reg_layout * layout,int cs,struct atmel_smc_cs_conf * conf)310 void atmel_hsmc_cs_conf_get(struct regmap *regmap,
311 const struct atmel_hsmc_reg_layout *layout,
312 int cs, struct atmel_smc_cs_conf *conf)
313 {
314 regmap_read(regmap, ATMEL_HSMC_SETUP(layout, cs), &conf->setup);
315 regmap_read(regmap, ATMEL_HSMC_PULSE(layout, cs), &conf->pulse);
316 regmap_read(regmap, ATMEL_HSMC_CYCLE(layout, cs), &conf->cycle);
317 regmap_read(regmap, ATMEL_HSMC_TIMINGS(layout, cs), &conf->timings);
318 regmap_read(regmap, ATMEL_HSMC_MODE(layout, cs), &conf->mode);
319 }
320 EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_get);
321
322 static const struct atmel_hsmc_reg_layout sama5d3_reg_layout = {
323 .timing_regs_offset = 0x600,
324 };
325
326 static const struct atmel_hsmc_reg_layout sama5d2_reg_layout = {
327 .timing_regs_offset = 0x700,
328 };
329
330 static const struct udevice_id atmel_smc_ids[] = {
331 { .compatible = "atmel,at91sam9260-smc", .data = (ulong)0 },
332 { .compatible = "atmel,sama5d3-smc", .data = (ulong)&sama5d3_reg_layout },
333 { .compatible = "atmel,sama5d2-smc", .data = (ulong)&sama5d2_reg_layout },
334 { /* sentinel */ },
335 };
336
337 /**
338 * atmel_hsmc_get_reg_layout - retrieve the layout of HSMC registers
339 * @np: the HSMC regmap
340 *
341 * Retrieve the layout of HSMC registers.
342 *
343 * Returns NULL in case of SMC, a struct atmel_hsmc_reg_layout pointer
344 * in HSMC case, otherwise ERR_PTR(-EINVAL).
345 */
346 const struct atmel_hsmc_reg_layout *
atmel_hsmc_get_reg_layout(ofnode np)347 atmel_hsmc_get_reg_layout(ofnode np)
348 {
349 int i;
350 const struct udevice_id *match;
351 const char *name;
352 int len;
353
354 name = ofnode_get_property(np, "compatible", &len);
355
356 for (i = 0; i < ARRAY_SIZE(atmel_smc_ids); i++) {
357 if (!strcmp(name, atmel_smc_ids[i].compatible)) {
358 match = &atmel_smc_ids[i];
359 break;
360 }
361 }
362
363 return match ? (struct atmel_hsmc_reg_layout *)match->data : ERR_PTR(-EINVAL);
364 }
365