1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Qualcomm SDHCI driver - SD/eMMC controller
4 *
5 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
6 *
7 * Based on Linux driver
8 */
9
10 #include <common.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <malloc.h>
14 #include <sdhci.h>
15 #include <wait_bit.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <linux/bitops.h>
19
20 /* Non-standard registers needed for SDHCI startup */
21 #define SDCC_MCI_POWER 0x0
22 #define SDCC_MCI_POWER_SW_RST BIT(7)
23
24 /* This is undocumented register */
25 #define SDCC_MCI_VERSION 0x50
26 #define SDCC_V5_VERSION 0x318
27
28 #define SDCC_VERSION_MAJOR_SHIFT 28
29 #define SDCC_VERSION_MAJOR_MASK (0xf << SDCC_VERSION_MAJOR_SHIFT)
30 #define SDCC_VERSION_MINOR_MASK 0xff
31
32 #define SDCC_MCI_STATUS2 0x6C
33 #define SDCC_MCI_STATUS2_MCI_ACT 0x1
34 #define SDCC_MCI_HC_MODE 0x78
35
36 /* Non standard (?) SDHCI register */
37 #define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c
38
39 struct msm_sdhc_plat {
40 struct mmc_config cfg;
41 struct mmc mmc;
42 };
43
44 struct msm_sdhc {
45 struct sdhci_host host;
46 void *base;
47 };
48
49 struct msm_sdhc_variant_info {
50 bool mci_removed;
51 };
52
53 DECLARE_GLOBAL_DATA_PTR;
54
msm_sdc_clk_init(struct udevice * dev)55 static int msm_sdc_clk_init(struct udevice *dev)
56 {
57 int node = dev_of_offset(dev);
58 uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
59 400000);
60 uint clkd[2]; /* clk_id and clk_no */
61 int clk_offset;
62 struct udevice *clk_dev;
63 struct clk clk;
64 int ret;
65
66 ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
67 if (ret)
68 return ret;
69
70 clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
71 if (clk_offset < 0)
72 return clk_offset;
73
74 ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
75 if (ret)
76 return ret;
77
78 clk.id = clkd[1];
79 ret = clk_request(clk_dev, &clk);
80 if (ret < 0)
81 return ret;
82
83 ret = clk_set_rate(&clk, clk_rate);
84 clk_free(&clk);
85 if (ret < 0)
86 return ret;
87
88 return 0;
89 }
90
msm_sdc_mci_init(struct msm_sdhc * prv)91 static int msm_sdc_mci_init(struct msm_sdhc *prv)
92 {
93 /* Reset the core and Enable SDHC mode */
94 writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST,
95 prv->base + SDCC_MCI_POWER);
96
97
98 /* Wait for reset to be written to register */
99 if (wait_for_bit_le32(prv->base + SDCC_MCI_STATUS2,
100 SDCC_MCI_STATUS2_MCI_ACT, false, 10, false)) {
101 printf("msm_sdhci: reset request failed\n");
102 return -EIO;
103 }
104
105 /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
106 if (wait_for_bit_le32(prv->base + SDCC_MCI_POWER,
107 SDCC_MCI_POWER_SW_RST, false, 2, false)) {
108 printf("msm_sdhci: stuck in reset\n");
109 return -ETIMEDOUT;
110 }
111
112 /* Enable host-controller mode */
113 writel(1, prv->base + SDCC_MCI_HC_MODE);
114
115 return 0;
116 }
117
msm_sdc_probe(struct udevice * dev)118 static int msm_sdc_probe(struct udevice *dev)
119 {
120 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
121 struct msm_sdhc_plat *plat = dev_get_plat(dev);
122 struct msm_sdhc *prv = dev_get_priv(dev);
123 const struct msm_sdhc_variant_info *var_info;
124 struct sdhci_host *host = &prv->host;
125 u32 core_version, core_minor, core_major;
126 u32 caps;
127 int ret;
128
129 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
130
131 host->max_clk = 0;
132
133 /* Init clocks */
134 ret = msm_sdc_clk_init(dev);
135 if (ret)
136 return ret;
137
138 var_info = (void *)dev_get_driver_data(dev);
139 if (!var_info->mci_removed) {
140 ret = msm_sdc_mci_init(prv);
141 if (ret)
142 return ret;
143 }
144
145 if (!var_info->mci_removed)
146 core_version = readl(prv->base + SDCC_MCI_VERSION);
147 else
148 core_version = readl(host->ioaddr + SDCC_V5_VERSION);
149
150 core_major = (core_version & SDCC_VERSION_MAJOR_MASK);
151 core_major >>= SDCC_VERSION_MAJOR_SHIFT;
152
153 core_minor = core_version & SDCC_VERSION_MINOR_MASK;
154
155 /*
156 * Support for some capabilities is not advertised by newer
157 * controller versions and must be explicitly enabled.
158 */
159 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
160 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
161 caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
162 writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0);
163 }
164
165 ret = mmc_of_parse(dev, &plat->cfg);
166 if (ret)
167 return ret;
168
169 host->mmc = &plat->mmc;
170 host->mmc->dev = dev;
171 ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
172 if (ret)
173 return ret;
174 host->mmc->priv = &prv->host;
175 upriv->mmc = host->mmc;
176
177 return sdhci_probe(dev);
178 }
179
msm_sdc_remove(struct udevice * dev)180 static int msm_sdc_remove(struct udevice *dev)
181 {
182 struct msm_sdhc *priv = dev_get_priv(dev);
183 const struct msm_sdhc_variant_info *var_info;
184
185 var_info = (void *)dev_get_driver_data(dev);
186
187 /* Disable host-controller mode */
188 if (!var_info->mci_removed)
189 writel(0, priv->base + SDCC_MCI_HC_MODE);
190
191 return 0;
192 }
193
msm_of_to_plat(struct udevice * dev)194 static int msm_of_to_plat(struct udevice *dev)
195 {
196 struct udevice *parent = dev->parent;
197 struct msm_sdhc *priv = dev_get_priv(dev);
198 struct sdhci_host *host = &priv->host;
199 int node = dev_of_offset(dev);
200
201 host->name = strdup(dev->name);
202 host->ioaddr = dev_read_addr_ptr(dev);
203 host->bus_width = fdtdec_get_int(gd->fdt_blob, node, "bus-width", 4);
204 host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
205 priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
206 dev_of_offset(parent), node, "reg", 1, NULL, false);
207 if (priv->base == (void *)FDT_ADDR_T_NONE ||
208 host->ioaddr == (void *)FDT_ADDR_T_NONE)
209 return -EINVAL;
210
211 return 0;
212 }
213
msm_sdc_bind(struct udevice * dev)214 static int msm_sdc_bind(struct udevice *dev)
215 {
216 struct msm_sdhc_plat *plat = dev_get_plat(dev);
217
218 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
219 }
220
221 static const struct msm_sdhc_variant_info msm_sdhc_mci_var = {
222 .mci_removed = false,
223 };
224
225 static const struct msm_sdhc_variant_info msm_sdhc_v5_var = {
226 .mci_removed = true,
227 };
228
229 static const struct udevice_id msm_mmc_ids[] = {
230 { .compatible = "qcom,sdhci-msm-v4", .data = (ulong)&msm_sdhc_mci_var },
231 { .compatible = "qcom,sdhci-msm-v5", .data = (ulong)&msm_sdhc_v5_var },
232 { }
233 };
234
235 U_BOOT_DRIVER(msm_sdc_drv) = {
236 .name = "msm_sdc",
237 .id = UCLASS_MMC,
238 .of_match = msm_mmc_ids,
239 .of_to_plat = msm_of_to_plat,
240 .ops = &sdhci_ops,
241 .bind = msm_sdc_bind,
242 .probe = msm_sdc_probe,
243 .remove = msm_sdc_remove,
244 .priv_auto = sizeof(struct msm_sdhc),
245 .plat_auto = sizeof(struct msm_sdhc_plat),
246 };
247