1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
4 */
5
6 #include <common.h>
7 #include <bouncebuf.h>
8 #include <clk.h>
9 #include <fdtdec.h>
10 #include <log.h>
11 #include <malloc.h>
12 #include <mmc.h>
13 #include <dm.h>
14 #include <asm/global_data.h>
15 #include <dm/device_compat.h>
16 #include <linux/bitops.h>
17 #include <linux/compat.h>
18 #include <linux/delay.h>
19 #include <linux/dma-direction.h>
20 #include <linux/io.h>
21 #include <linux/sizes.h>
22 #include <power/regulator.h>
23 #include <asm/unaligned.h>
24 #include "tmio-common.h"
25
26 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
27 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
28 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
29
30 /* SCC registers */
31 #define RENESAS_SDHI_SCC_DTCNTL 0x800
32 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
33 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
34 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
35 #define RENESAS_SDHI_SCC_TAPSET 0x804
36 #define RENESAS_SDHI_SCC_DT2FF 0x808
37 #define RENESAS_SDHI_SCC_CKSEL 0x80c
38 #define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
39 #define RENESAS_SDHI_SCC_RVSCNTL 0x810
40 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
41 #define RENESAS_SDHI_SCC_RVSREQ 0x814
42 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
43 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
44 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
45 #define RENESAS_SDHI_SCC_SMPCMP 0x818
46 #define RENESAS_SDHI_SCC_SMPCMP_CMD_ERR (BIT(24) | BIT(8))
47 #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
48 #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
49 #define RENESAS_SDHI_SCC_TMPPORT2 0x81c
50 #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
51 #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
52 #define RENESAS_SDHI_SCC_TMPPORT3 0x828
53 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0 3
54 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1 2
55 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2 1
56 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3 0
57 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK 0x3
58 #define RENESAS_SDHI_SCC_TMPPORT4 0x82c
59 #define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
60 #define RENESAS_SDHI_SCC_TMPPORT5 0x830
61 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
62 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
63 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
64 #define RENESAS_SDHI_SCC_TMPPORT6 0x834
65 #define RENESAS_SDHI_SCC_TMPPORT7 0x838
66 #define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
67 #define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
68 #define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
69
70 #define RENESAS_SDHI_MAX_TAP 3
71
72 #define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1)
73
74 static const u8 r8a7796_rev13_calib_table[2][CALIB_TABLE_MAX] = {
75 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15,
76 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
77 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11,
78 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
79 };
80
81 static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = {
82 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
83 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
84 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17,
85 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
86 };
87
88 static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
89 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
90 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
91 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10,
92 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
93 };
94
rmobile_is_gen3_mmc0(struct tmio_sd_priv * priv)95 static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
96 {
97 /* On R-Car Gen3, MMC0 is at 0xee140000 */
98 return (uintptr_t)(priv->regbase) == 0xee140000;
99 }
100
sd_scc_tmpport_read32(struct tmio_sd_priv * priv,u32 addr)101 static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
102 {
103 /* read mode */
104 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
105 (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
106 RENESAS_SDHI_SCC_TMPPORT5);
107
108 /* access start and stop */
109 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
110 RENESAS_SDHI_SCC_TMPPORT4);
111 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
112
113 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
114 }
115
sd_scc_tmpport_write32(struct tmio_sd_priv * priv,u32 addr,u32 val)116 static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
117 {
118 /* write mode */
119 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
120 (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
121 RENESAS_SDHI_SCC_TMPPORT5);
122 tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
123
124 /* access start and stop */
125 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
126 RENESAS_SDHI_SCC_TMPPORT4);
127 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
128 }
129
renesas_sdhi_check_scc_error(struct udevice * dev)130 static bool renesas_sdhi_check_scc_error(struct udevice *dev)
131 {
132 struct tmio_sd_priv *priv = dev_get_priv(dev);
133 struct mmc *mmc = mmc_get_mmc_dev(dev);
134 unsigned long new_tap = priv->tap_set;
135 unsigned long error_tap = priv->tap_set;
136 u32 reg, smpcmp;
137
138 if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
139 (mmc->selected_mode != UHS_SDR104) &&
140 (mmc->selected_mode != MMC_HS_200) &&
141 (mmc->selected_mode != MMC_HS_400) &&
142 (priv->nrtaps != 4))
143 return false;
144
145 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
146 /* Handle automatic tuning correction */
147 if (reg & RENESAS_SDHI_SCC_RVSCNTL_RVSEN) {
148 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
149 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) {
150 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
151 return true;
152 }
153
154 return false;
155 }
156
157 /* Handle manual tuning correction */
158 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
159 if (!reg) /* No error */
160 return false;
161
162 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
163
164 if (mmc->selected_mode == MMC_HS_400) {
165 /*
166 * Correction Error Status contains CMD and DAT signal status.
167 * In HS400, DAT signal based on DS signal, not CLK.
168 * Therefore, use only CMD status.
169 */
170 smpcmp = tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP) &
171 RENESAS_SDHI_SCC_SMPCMP_CMD_ERR;
172
173 switch (smpcmp) {
174 case 0:
175 return false; /* No error in CMD signal */
176 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP:
177 new_tap = (priv->tap_set +
178 priv->tap_num + 1) % priv->tap_num;
179 error_tap = (priv->tap_set +
180 priv->tap_num - 1) % priv->tap_num;
181 break;
182 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN:
183 new_tap = (priv->tap_set +
184 priv->tap_num - 1) % priv->tap_num;
185 error_tap = (priv->tap_set +
186 priv->tap_num + 1) % priv->tap_num;
187 break;
188 default:
189 return true; /* Need re-tune */
190 }
191
192 if (priv->hs400_bad_tap & BIT(new_tap)) {
193 /*
194 * New tap is bad tap (cannot change).
195 * Compare with HS200 tuning result.
196 * In HS200 tuning, when smpcmp[error_tap]
197 * is OK, retune is executed.
198 */
199 if (priv->smpcmp & BIT(error_tap))
200 return true; /* Need retune */
201
202 return false; /* cannot change */
203 }
204
205 priv->tap_set = new_tap;
206 } else {
207 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR)
208 return true; /* Need re-tune */
209 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPUP)
210 priv->tap_set = (priv->tap_set +
211 priv->tap_num + 1) % priv->tap_num;
212 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN)
213 priv->tap_set = (priv->tap_set +
214 priv->tap_num - 1) % priv->tap_num;
215 else
216 return false;
217 }
218
219 /* Set TAP position */
220 tmio_sd_writel(priv, priv->tap_set >> ((priv->nrtaps == 4) ? 1 : 0),
221 RENESAS_SDHI_SCC_TAPSET);
222
223 return false;
224 }
225
renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv * priv)226 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
227 {
228 u32 calib_code;
229
230 if (!priv->adjust_hs400_enable)
231 return;
232
233 if (!priv->needs_adjust_hs400)
234 return;
235
236 if (!priv->adjust_hs400_calib_table)
237 return;
238
239 /*
240 * Enabled Manual adjust HS400 mode
241 *
242 * 1) Disabled Write Protect
243 * W(addr=0x00, WP_DISABLE_CODE)
244 *
245 * 2) Read Calibration code
246 * read_value = R(addr=0x26)
247 * 3) Refer to calibration table
248 * Calibration code = table[read_value]
249 * 4) Enabled Manual Calibration
250 * W(addr=0x22, manual mode | Calibration code)
251 * 5) Set Offset value to TMPPORT3 Reg
252 */
253 sd_scc_tmpport_write32(priv, 0x00,
254 RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
255 calib_code = sd_scc_tmpport_read32(priv, 0x26);
256 calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
257 sd_scc_tmpport_write32(priv, 0x22,
258 RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
259 priv->adjust_hs400_calib_table[calib_code]);
260 tmio_sd_writel(priv, priv->adjust_hs400_offset,
261 RENESAS_SDHI_SCC_TMPPORT3);
262
263 /* Clear flag */
264 priv->needs_adjust_hs400 = false;
265 }
266
renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv * priv)267 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
268 {
269
270 /* Disabled Manual adjust HS400 mode
271 *
272 * 1) Disabled Write Protect
273 * W(addr=0x00, WP_DISABLE_CODE)
274 * 2) Disabled Manual Calibration
275 * W(addr=0x22, 0)
276 * 3) Clear offset value to TMPPORT3 Reg
277 */
278 sd_scc_tmpport_write32(priv, 0x00,
279 RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
280 sd_scc_tmpport_write32(priv, 0x22, 0);
281 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
282 }
283
renesas_sdhi_init_tuning(struct tmio_sd_priv * priv)284 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
285 {
286 u32 reg;
287
288 /* Initialize SCC */
289 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
290
291 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
292 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
293 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
294
295 /* Set sampling clock selection range */
296 tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
297 RENESAS_SDHI_SCC_DTCNTL_TAPEN,
298 RENESAS_SDHI_SCC_DTCNTL);
299
300 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
301 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
302 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
303
304 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
305 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
306 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
307
308 tmio_sd_writel(priv, 0x300 /* scc_tappos */,
309 RENESAS_SDHI_SCC_DT2FF);
310
311 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
312 reg |= TMIO_SD_CLKCTL_SCLKEN;
313 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
314
315 /* Read TAPNUM */
316 return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
317 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
318 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
319 }
320
renesas_sdhi_reset_tuning(struct tmio_sd_priv * priv)321 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
322 {
323 u32 reg;
324
325 /* Reset SCC */
326 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
327 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
328 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
329
330 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
331 reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
332 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
333
334 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
335 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
336 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
337 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
338
339 /* Disable HS400 mode adjustment */
340 renesas_sdhi_adjust_hs400_mode_disable(priv);
341
342 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
343 reg |= TMIO_SD_CLKCTL_SCLKEN;
344 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
345
346 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
347 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
348 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
349
350 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
351 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
352 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
353 }
354
renesas_sdhi_hs400(struct udevice * dev)355 static int renesas_sdhi_hs400(struct udevice *dev)
356 {
357 struct tmio_sd_priv *priv = dev_get_priv(dev);
358 struct mmc *mmc = mmc_get_mmc_dev(dev);
359 bool hs400 = (mmc->selected_mode == MMC_HS_400);
360 int ret, taps = hs400 ? priv->nrtaps : 8;
361 const u32 sdn_rate = 200000000;
362 u32 sdnh_rate = 800000000;
363 unsigned long new_tap;
364 u32 reg;
365
366 if (clk_valid(&priv->clkh) && !priv->needs_clkh_fallback) {
367 /* HS400 on 4tap SoC => SDnH=400 MHz, SDn=200 MHz */
368 if (taps == 4)
369 sdnh_rate /= 2;
370 ret = clk_set_rate(&priv->clkh, sdnh_rate);
371 if (ret < 0)
372 return ret;
373 }
374
375 ret = clk_set_rate(&priv->clk, sdn_rate);
376 if (ret < 0)
377 return ret;
378
379 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
380 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
381 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
382
383 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
384 if (hs400) {
385 reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
386 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
387 } else {
388 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
389 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
390 }
391
392 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
393
394 /* Disable HS400 mode adjustment */
395 if (!hs400)
396 renesas_sdhi_adjust_hs400_mode_disable(priv);
397
398 tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
399 RENESAS_SDHI_SCC_DTCNTL_TAPEN,
400 RENESAS_SDHI_SCC_DTCNTL);
401
402 /* Avoid bad TAP */
403 if (priv->hs400_bad_tap & BIT(priv->tap_set)) {
404 new_tap = (priv->tap_set +
405 priv->tap_num + 1) % priv->tap_num;
406
407 if (priv->hs400_bad_tap & BIT(new_tap))
408 new_tap = (priv->tap_set +
409 priv->tap_num - 1) % priv->tap_num;
410
411 if (priv->hs400_bad_tap & BIT(new_tap)) {
412 new_tap = priv->tap_set;
413 debug("Three consecutive bad tap is prohibited\n");
414 }
415
416 priv->tap_set = new_tap;
417 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
418 }
419
420 if (taps == 4) {
421 tmio_sd_writel(priv, priv->tap_set >> 1,
422 RENESAS_SDHI_SCC_TAPSET);
423 tmio_sd_writel(priv, hs400 ? 0x100 : 0x300,
424 RENESAS_SDHI_SCC_DT2FF);
425 } else {
426 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
427 tmio_sd_writel(priv, 0x300, RENESAS_SDHI_SCC_DT2FF);
428 }
429
430 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
431 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
432 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
433
434 /* Execute adjust hs400 offset after setting to HS400 mode */
435 if (hs400)
436 priv->needs_adjust_hs400 = true;
437
438 return 0;
439 }
440
renesas_sdhi_prepare_tuning(struct tmio_sd_priv * priv,unsigned long tap)441 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
442 unsigned long tap)
443 {
444 /* Set sampling clock position */
445 tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
446 }
447
renesas_sdhi_compare_scc_data(struct tmio_sd_priv * priv)448 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
449 {
450 /* Get comparison of sampling data */
451 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
452 }
453
renesas_sdhi_select_tuning(struct tmio_sd_priv * priv,unsigned int taps)454 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
455 unsigned int taps)
456 {
457 unsigned long tap_cnt; /* counter of tuning success */
458 unsigned long tap_start;/* start position of tuning success */
459 unsigned long tap_end; /* end position of tuning success */
460 unsigned long ntap; /* temporary counter of tuning success */
461 unsigned long match_cnt;/* counter of matching data */
462 unsigned long i;
463 bool select = false;
464 u32 reg;
465
466 priv->needs_adjust_hs400 = false;
467
468 /* Clear SCC_RVSREQ */
469 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
470
471 /* Merge the results */
472 for (i = 0; i < priv->tap_num * 2; i++) {
473 if (!(taps & BIT(i))) {
474 taps &= ~BIT(i % priv->tap_num);
475 taps &= ~BIT((i % priv->tap_num) + priv->tap_num);
476 }
477 if (!(priv->smpcmp & BIT(i))) {
478 priv->smpcmp &= ~BIT(i % priv->tap_num);
479 priv->smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num);
480 }
481 }
482
483 /*
484 * Find the longest consecutive run of successful probes. If that
485 * is more than RENESAS_SDHI_MAX_TAP probes long then use the
486 * center index as the tap.
487 */
488 tap_cnt = 0;
489 ntap = 0;
490 tap_start = 0;
491 tap_end = 0;
492 for (i = 0; i < priv->tap_num * 2; i++) {
493 if (taps & BIT(i))
494 ntap++;
495 else {
496 if (ntap > tap_cnt) {
497 tap_start = i - ntap;
498 tap_end = i - 1;
499 tap_cnt = ntap;
500 }
501 ntap = 0;
502 }
503 }
504
505 if (ntap > tap_cnt) {
506 tap_start = i - ntap;
507 tap_end = i - 1;
508 tap_cnt = ntap;
509 }
510
511 /*
512 * If all of the TAP is OK, the sampling clock position is selected by
513 * identifying the change point of data.
514 */
515 if (tap_cnt == priv->tap_num * 2) {
516 match_cnt = 0;
517 ntap = 0;
518 tap_start = 0;
519 tap_end = 0;
520 for (i = 0; i < priv->tap_num * 2; i++) {
521 if (priv->smpcmp & BIT(i))
522 ntap++;
523 else {
524 if (ntap > match_cnt) {
525 tap_start = i - ntap;
526 tap_end = i - 1;
527 match_cnt = ntap;
528 }
529 ntap = 0;
530 }
531 }
532 if (ntap > match_cnt) {
533 tap_start = i - ntap;
534 tap_end = i - 1;
535 match_cnt = ntap;
536 }
537 if (match_cnt)
538 select = true;
539 } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
540 select = true;
541
542 if (select)
543 priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num;
544 else
545 return -EIO;
546
547 /* Set SCC */
548 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
549
550 /* Enable auto re-tuning */
551 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
552 reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
553 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
554
555 return 0;
556 }
557
renesas_sdhi_execute_tuning(struct udevice * dev,uint opcode)558 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
559 {
560 struct tmio_sd_priv *priv = dev_get_priv(dev);
561 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
562 struct mmc *mmc = upriv->mmc;
563 unsigned int tap_num;
564 unsigned int taps = 0;
565 int i, ret = 0;
566 u32 caps;
567
568 /* Only supported on Renesas RCar */
569 if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
570 return -EINVAL;
571
572 /* clock tuning is not needed for upto 52MHz */
573 if (!((mmc->selected_mode == MMC_HS_200) ||
574 (mmc->selected_mode == MMC_HS_400) ||
575 (mmc->selected_mode == UHS_SDR104) ||
576 (mmc->selected_mode == UHS_SDR50)))
577 return 0;
578
579 tap_num = renesas_sdhi_init_tuning(priv);
580 if (!tap_num)
581 /* Tuning is not supported */
582 goto out;
583
584 priv->tap_num = tap_num;
585
586 if (priv->tap_num * 2 >= sizeof(taps) * 8) {
587 dev_err(dev,
588 "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
589 goto out;
590 }
591
592 priv->smpcmp = 0;
593
594 /* Issue CMD19 twice for each tap */
595 for (i = 0; i < 2 * priv->tap_num; i++) {
596 renesas_sdhi_prepare_tuning(priv, i % priv->tap_num);
597
598 /* Force PIO for the tuning */
599 caps = priv->caps;
600 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
601
602 ret = mmc_send_tuning(mmc, opcode, NULL);
603
604 priv->caps = caps;
605
606 if (ret == 0)
607 taps |= BIT(i);
608
609 ret = renesas_sdhi_compare_scc_data(priv);
610 if (ret == 0)
611 priv->smpcmp |= BIT(i);
612
613 mdelay(1);
614 }
615
616 ret = renesas_sdhi_select_tuning(priv, taps);
617
618 out:
619 if (ret < 0) {
620 dev_warn(dev, "Tuning procedure failed\n");
621 renesas_sdhi_reset_tuning(priv);
622 }
623
624 return ret;
625 }
626 #else
renesas_sdhi_hs400(struct udevice * dev)627 static int renesas_sdhi_hs400(struct udevice *dev)
628 {
629 return 0;
630 }
631 #endif
632
renesas_sdhi_set_ios(struct udevice * dev)633 static int renesas_sdhi_set_ios(struct udevice *dev)
634 {
635 struct tmio_sd_priv *priv = dev_get_priv(dev);
636 u32 tmp;
637 int ret;
638
639 /* Stop the clock before changing its rate to avoid a glitch signal */
640 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
641 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
642 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
643
644 ret = renesas_sdhi_hs400(dev);
645 if (ret)
646 return ret;
647
648 ret = tmio_sd_set_ios(dev);
649
650 mdelay(10);
651
652 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
653 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
654 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
655 struct mmc *mmc = mmc_get_mmc_dev(dev);
656 if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
657 (mmc->selected_mode != UHS_SDR104) &&
658 (mmc->selected_mode != MMC_HS_200) &&
659 (mmc->selected_mode != MMC_HS_400)) {
660 renesas_sdhi_reset_tuning(priv);
661 }
662 #endif
663
664 return ret;
665 }
666
667 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
renesas_sdhi_wait_dat0(struct udevice * dev,int state,int timeout_us)668 static int renesas_sdhi_wait_dat0(struct udevice *dev, int state,
669 int timeout_us)
670 {
671 int ret = -ETIMEDOUT;
672 bool dat0_high;
673 bool target_dat0_high = !!state;
674 struct tmio_sd_priv *priv = dev_get_priv(dev);
675
676 timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
677 while (timeout_us--) {
678 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
679 if (dat0_high == target_dat0_high) {
680 ret = 0;
681 break;
682 }
683 udelay(10);
684 }
685
686 return ret;
687 }
688 #endif
689
690 #define RENESAS_SDHI_DMA_ALIGNMENT 128
691
renesas_sdhi_addr_aligned_gen(uintptr_t ubuf,size_t len,size_t len_aligned)692 static int renesas_sdhi_addr_aligned_gen(uintptr_t ubuf,
693 size_t len, size_t len_aligned)
694 {
695 /* Check if start is aligned */
696 if (!IS_ALIGNED(ubuf, RENESAS_SDHI_DMA_ALIGNMENT)) {
697 debug("Unaligned buffer address %lx\n", ubuf);
698 return 0;
699 }
700
701 /* Check if length is aligned */
702 if (len != len_aligned) {
703 debug("Unaligned buffer length %zu\n", len);
704 return 0;
705 }
706
707 #ifdef CONFIG_PHYS_64BIT
708 /* Check if below 32bit boundary */
709 if ((ubuf >> 32) || (ubuf + len_aligned) >> 32) {
710 debug("Buffer above 32bit boundary %lx-%lx\n",
711 ubuf, ubuf + len_aligned);
712 return 0;
713 }
714 #endif
715
716 /* Aligned */
717 return 1;
718 }
719
renesas_sdhi_addr_aligned(struct bounce_buffer * state)720 static int renesas_sdhi_addr_aligned(struct bounce_buffer *state)
721 {
722 uintptr_t ubuf = (uintptr_t)state->user_buffer;
723
724 return renesas_sdhi_addr_aligned_gen(ubuf, state->len,
725 state->len_aligned);
726 }
727
renesas_sdhi_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)728 static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
729 struct mmc_data *data)
730 {
731 struct bounce_buffer bbstate;
732 unsigned int bbflags;
733 bool bbok = false;
734 size_t len;
735 void *buf;
736 int ret;
737
738 if (data) {
739 if (data->flags & MMC_DATA_READ) {
740 buf = data->dest;
741 bbflags = GEN_BB_WRITE;
742 } else {
743 buf = (void *)data->src;
744 bbflags = GEN_BB_READ;
745 }
746 len = data->blocks * data->blocksize;
747
748 ret = bounce_buffer_start_extalign(&bbstate, buf, len, bbflags,
749 RENESAS_SDHI_DMA_ALIGNMENT,
750 renesas_sdhi_addr_aligned);
751 /*
752 * If the amount of data to transfer is too large, we can get
753 * -ENOMEM when starting the bounce buffer. If that happens,
754 * fall back to PIO as it was before, otherwise use the BB.
755 */
756 if (!ret) {
757 bbok = true;
758 if (data->flags & MMC_DATA_READ)
759 data->dest = bbstate.bounce_buffer;
760 else
761 data->src = bbstate.bounce_buffer;
762 }
763 }
764
765 ret = tmio_sd_send_cmd(dev, cmd, data);
766
767 if (data && bbok) {
768 buf = bbstate.user_buffer;
769
770 bounce_buffer_stop(&bbstate);
771
772 if (data->flags & MMC_DATA_READ)
773 data->dest = buf;
774 else
775 data->src = buf;
776 }
777
778 if (ret)
779 return ret;
780
781 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
782 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
783 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
784 struct tmio_sd_priv *priv = dev_get_priv(dev);
785
786 renesas_sdhi_check_scc_error(dev);
787
788 if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
789 renesas_sdhi_adjust_hs400_mode_enable(priv);
790 #endif
791
792 return 0;
793 }
794
renesas_sdhi_get_b_max(struct udevice * dev,void * dst,lbaint_t blkcnt)795 int renesas_sdhi_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt)
796 {
797 struct tmio_sd_priv *priv = dev_get_priv(dev);
798 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
799 struct mmc *mmc = upriv->mmc;
800 size_t len = blkcnt * mmc->read_bl_len;
801 size_t len_align = roundup(len, RENESAS_SDHI_DMA_ALIGNMENT);
802
803 if (renesas_sdhi_addr_aligned_gen((uintptr_t)dst, len, len_align)) {
804 if (priv->quirks & TMIO_SD_CAP_16BIT)
805 return U16_MAX;
806 else
807 return U32_MAX;
808 } else {
809 return (CONFIG_SYS_MALLOC_LEN / 4) / mmc->read_bl_len;
810 }
811 }
812
813 static const struct dm_mmc_ops renesas_sdhi_ops = {
814 .send_cmd = renesas_sdhi_send_cmd,
815 .set_ios = renesas_sdhi_set_ios,
816 .get_cd = tmio_sd_get_cd,
817 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
818 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
819 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
820 .execute_tuning = renesas_sdhi_execute_tuning,
821 #endif
822 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
823 .wait_dat0 = renesas_sdhi_wait_dat0,
824 #endif
825 .get_b_max = renesas_sdhi_get_b_max,
826 };
827
828 #define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
829 #define RENESAS_GEN3_QUIRKS \
830 TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
831
832 static const struct udevice_id renesas_sdhi_match[] = {
833 { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
834 { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
835 { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
836 { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
837 { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
838 { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
839 { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
840 { .compatible = "renesas,sdhi-r8a77961", .data = RENESAS_GEN3_QUIRKS },
841 { .compatible = "renesas,rcar-gen3-sdhi", .data = RENESAS_GEN3_QUIRKS },
842 { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
843 { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
844 { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
845 { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
846 { .compatible = "renesas,rcar-gen4-sdhi", .data = RENESAS_GEN3_QUIRKS },
847 { /* sentinel */ }
848 };
849
renesas_sdhi_clk_get_rate(struct tmio_sd_priv * priv)850 static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
851 {
852 return clk_get_rate(&priv->clk);
853 }
854
renesas_sdhi_filter_caps(struct udevice * dev)855 static void renesas_sdhi_filter_caps(struct udevice *dev)
856 {
857 struct tmio_sd_priv *priv = dev_get_priv(dev);
858
859 if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
860 return;
861
862 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL)
863 priv->idma_bus_width = TMIO_SD_DMA_MODE_BUS_WIDTH;
864
865 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
866 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
867 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
868 struct tmio_sd_plat *plat = dev_get_plat(dev);
869
870 /* HS400 is not supported on H3 ES1.x, M3W ES1.[012], V3M, V3H ES1.x, D3 */
871 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
872 (rmobile_get_cpu_rev_integer() <= 1)) ||
873 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
874 (rmobile_get_cpu_rev_integer() == 1) &&
875 (rmobile_get_cpu_rev_fraction() <= 2)) ||
876 (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970) ||
877 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77980) &&
878 (rmobile_get_cpu_rev_integer() <= 1)) ||
879 (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
880 plat->cfg.host_caps &= ~MMC_MODE_HS400;
881
882 /* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
883 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
884 (rmobile_get_cpu_rev_integer() >= 2)) ||
885 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
886 (rmobile_get_cpu_rev_integer() == 1) &&
887 (rmobile_get_cpu_rev_fraction() == 2)) ||
888 (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
889 priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
890
891 /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
892 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
893 (rmobile_get_cpu_rev_integer() == 1) &&
894 (rmobile_get_cpu_rev_fraction() > 2)) {
895 priv->adjust_hs400_enable = true;
896 priv->adjust_hs400_offset = 3;
897 priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
898 priv->adjust_hs400_calib_table =
899 r8a7796_rev13_calib_table[!rmobile_is_gen3_mmc0(priv)];
900 }
901
902 /* M3W+ bad taps */
903 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
904 (rmobile_get_cpu_rev_integer() == 3))
905 priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
906
907 /* M3N can use HS400 with manual adjustment */
908 if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
909 priv->adjust_hs400_enable = true;
910 priv->adjust_hs400_offset = 3;
911 priv->adjust_hs400_calib_table =
912 r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)];
913 }
914
915 /* E3 can use HS400 with manual adjustment */
916 if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
917 priv->adjust_hs400_enable = true;
918 priv->adjust_hs400_offset = 3;
919 priv->adjust_hs400_calib_table =
920 r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)];
921 }
922
923 /* H3 ES1.x, ES2.0 and M3W ES1.[0123] uses 4 tuning taps */
924 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
925 (rmobile_get_cpu_rev_integer() <= 2)) ||
926 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
927 (rmobile_get_cpu_rev_integer() == 1) &&
928 (rmobile_get_cpu_rev_fraction() <= 3)))
929 priv->nrtaps = 4;
930 else
931 priv->nrtaps = 8;
932 #endif
933 /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
934 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
935 (rmobile_get_cpu_rev_integer() <= 1)) ||
936 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
937 (rmobile_get_cpu_rev_integer() == 1) &&
938 (rmobile_get_cpu_rev_fraction() == 0)))
939 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
940 else
941 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
942
943 /* V3M handles SD0H differently than other Gen3 SoCs */
944 if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970)
945 priv->needs_clkh_fallback = true;
946 else
947 priv->needs_clkh_fallback = false;
948 }
949
renesas_sdhi_probe(struct udevice * dev)950 static int renesas_sdhi_probe(struct udevice *dev)
951 {
952 struct tmio_sd_priv *priv = dev_get_priv(dev);
953 u32 quirks = dev_get_driver_data(dev);
954 struct fdt_resource reg_res;
955 DECLARE_GLOBAL_DATA_PTR;
956 int ret;
957
958 priv->clk_get_rate = renesas_sdhi_clk_get_rate;
959
960 if (quirks == RENESAS_GEN2_QUIRKS) {
961 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
962 "reg", 0, ®_res);
963 if (ret < 0) {
964 dev_err(dev, "\"reg\" resource not found, ret=%i\n",
965 ret);
966 return ret;
967 }
968
969 if (fdt_resource_size(®_res) == 0x100)
970 quirks |= TMIO_SD_CAP_16BIT;
971 }
972
973 ret = clk_get_by_index(dev, 0, &priv->clk);
974 if (ret < 0) {
975 dev_err(dev, "failed to get host clock\n");
976 return ret;
977 }
978
979 /* optional SDnH clock */
980 ret = clk_get_by_name(dev, "clkh", &priv->clkh);
981 if (ret < 0) {
982 dev_dbg(dev, "failed to get clkh\n");
983 } else {
984 ret = clk_set_rate(&priv->clkh, 800000000);
985 if (ret < 0) {
986 dev_err(dev, "failed to set rate for SDnH clock (%d)\n", ret);
987 goto err_clk;
988 }
989 }
990
991 /* set to max rate */
992 ret = clk_set_rate(&priv->clk, 200000000);
993 if (ret < 0) {
994 dev_err(dev, "failed to set rate for SDn clock (%d)\n", ret);
995 goto err_clkh;
996 }
997
998 ret = clk_enable(&priv->clk);
999 if (ret) {
1000 dev_err(dev, "failed to enable SDn clock (%d)\n", ret);
1001 goto err_clkh;
1002 }
1003
1004 priv->quirks = quirks;
1005 ret = tmio_sd_probe(dev, quirks);
1006 if (ret)
1007 goto err_tmio_probe;
1008
1009 renesas_sdhi_filter_caps(dev);
1010
1011 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
1012 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
1013 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1014 if (priv->caps & TMIO_SD_CAP_RCAR_UHS)
1015 renesas_sdhi_reset_tuning(priv);
1016 #endif
1017 return 0;
1018
1019 err_tmio_probe:
1020 clk_disable(&priv->clk);
1021 err_clkh:
1022 clk_free(&priv->clkh);
1023 err_clk:
1024 clk_free(&priv->clk);
1025 return ret;
1026 }
1027
1028 U_BOOT_DRIVER(renesas_sdhi) = {
1029 .name = "renesas-sdhi",
1030 .id = UCLASS_MMC,
1031 .of_match = renesas_sdhi_match,
1032 .bind = tmio_sd_bind,
1033 .probe = renesas_sdhi_probe,
1034 .priv_auto = sizeof(struct tmio_sd_priv),
1035 .plat_auto = sizeof(struct tmio_sd_plat),
1036 .ops = &renesas_sdhi_ops,
1037 };
1038