1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de
5 */
6
7 #include <common.h>
8 #include <nand.h>
9 #include <asm/io.h>
10 #include <linux/delay.h>
11 #include <linux/mtd/rawnand.h>
12
13 #define CFG_NAND_MODE_REG (void *)(CFG_SYS_NAND_BASE + 0x20000)
14 #define CFG_NAND_DATA_REG (void *)(CFG_SYS_NAND_BASE + 0x30000)
15
16 #define read_mode() in_8(CFG_NAND_MODE_REG)
17 #define write_mode(val) out_8(CFG_NAND_MODE_REG, val)
18 #define read_data() in_8(CFG_NAND_DATA_REG)
19 #define write_data(val) out_8(CFG_NAND_DATA_REG, val)
20
21 #define KPN_RDY2 (1 << 7)
22 #define KPN_RDY1 (1 << 6)
23 #define KPN_WPN (1 << 4)
24 #define KPN_CE2N (1 << 3)
25 #define KPN_CE1N (1 << 2)
26 #define KPN_ALE (1 << 1)
27 #define KPN_CLE (1 << 0)
28
29 #define KPN_DEFAULT_CHIP_DELAY 50
30
kpn_chip_ready(void)31 static int kpn_chip_ready(void)
32 {
33 if (read_mode() & KPN_RDY1)
34 return 1;
35
36 return 0;
37 }
38
kpn_wait_rdy(void)39 static void kpn_wait_rdy(void)
40 {
41 int cnt = 1000000;
42
43 while (--cnt && !kpn_chip_ready())
44 udelay(1);
45
46 if (!cnt)
47 printf ("timeout while waiting for RDY\n");
48 }
49
kpn_nand_hwcontrol(struct mtd_info * mtd,int cmd,unsigned int ctrl)50 static void kpn_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
51 {
52 u8 reg_val = read_mode();
53
54 if (ctrl & NAND_CTRL_CHANGE) {
55 reg_val = reg_val & ~(KPN_ALE + KPN_CLE);
56
57 if (ctrl & NAND_CLE)
58 reg_val = reg_val | KPN_CLE;
59 if (ctrl & NAND_ALE)
60 reg_val = reg_val | KPN_ALE;
61 if (ctrl & NAND_NCE)
62 reg_val = reg_val & ~KPN_CE1N;
63 else
64 reg_val = reg_val | KPN_CE1N;
65
66 write_mode(reg_val);
67 }
68 if (cmd != NAND_CMD_NONE)
69 write_data(cmd);
70
71 /* wait until flash is ready */
72 kpn_wait_rdy();
73 }
74
kpn_nand_read_byte(struct mtd_info * mtd)75 static u_char kpn_nand_read_byte(struct mtd_info *mtd)
76 {
77 return read_data();
78 }
79
kpn_nand_write_buf(struct mtd_info * mtd,const u_char * buf,int len)80 static void kpn_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
81 {
82 int i;
83
84 for (i = 0; i < len; i++) {
85 write_data(buf[i]);
86 kpn_wait_rdy();
87 }
88 }
89
kpn_nand_read_buf(struct mtd_info * mtd,u_char * buf,int len)90 static void kpn_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
91 {
92 int i;
93
94 for (i = 0; i < len; i++)
95 buf[i] = read_data();
96 }
97
kpn_nand_dev_ready(struct mtd_info * mtd)98 static int kpn_nand_dev_ready(struct mtd_info *mtd)
99 {
100 kpn_wait_rdy();
101
102 return 1;
103 }
104
board_nand_init(struct nand_chip * nand)105 int board_nand_init(struct nand_chip *nand)
106 {
107 #if defined(CONFIG_NAND_ECC_BCH)
108 nand->ecc.mode = NAND_ECC_SOFT_BCH;
109 #else
110 nand->ecc.mode = NAND_ECC_SOFT;
111 #endif
112
113 /* Reference hardware control function */
114 nand->cmd_ctrl = kpn_nand_hwcontrol;
115 nand->read_byte = kpn_nand_read_byte;
116 nand->write_buf = kpn_nand_write_buf;
117 nand->read_buf = kpn_nand_read_buf;
118 nand->dev_ready = kpn_nand_dev_ready;
119 nand->chip_delay = KPN_DEFAULT_CHIP_DELAY;
120
121 /* reset mode register */
122 write_mode(KPN_CE1N + KPN_CE2N + KPN_WPN);
123 return 0;
124 }
125