1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2021 Macronix International Co., Ltd.
4 *
5 * Author:
6 * Zhengxun Li <zhengxunli@mxic.com.tw>
7 */
8
9 #include <common.h>
10 #include <clk.h>
11 #include <dm.h>
12 #include <malloc.h>
13 #include <nand.h>
14 #include <asm/io.h>
15 #include <asm/arch/hardware.h>
16 #include <dm/device_compat.h>
17 #include <linux/bug.h>
18 #include <linux/errno.h>
19 #include <linux/iopoll.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/rawnand.h>
22 #include <linux/mtd/partitions.h>
23 #include <linux/mtd/nand_ecc.h>
24 #include <linux/delay.h>
25
26 #define HC_CFG 0x0
27 #define HC_CFG_IF_CFG(x) ((x) << 27)
28 #define HC_CFG_DUAL_SLAVE BIT(31)
29 #define HC_CFG_INDIVIDUAL BIT(30)
30 #define HC_CFG_NIO(x) (((x) / 4) << 27)
31 #define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2)))
32 #define HC_CFG_TYPE_SPI_NOR 0
33 #define HC_CFG_TYPE_SPI_NAND 1
34 #define HC_CFG_TYPE_SPI_RAM 2
35 #define HC_CFG_TYPE_RAW_NAND 3
36 #define HC_CFG_SLV_ACT(x) ((x) << 21)
37 #define HC_CFG_CLK_PH_EN BIT(20)
38 #define HC_CFG_CLK_POL_INV BIT(19)
39 #define HC_CFG_BIG_ENDIAN BIT(18)
40 #define HC_CFG_DATA_PASS BIT(17)
41 #define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16)
42 #define HC_CFG_MAN_START_EN BIT(3)
43 #define HC_CFG_MAN_START BIT(2)
44 #define HC_CFG_MAN_CS_EN BIT(1)
45 #define HC_CFG_MAN_CS_ASSERT BIT(0)
46
47 #define INT_STS 0x4
48 #define INT_STS_EN 0x8
49 #define INT_SIG_EN 0xc
50 #define INT_STS_ALL GENMASK(31, 0)
51 #define INT_RDY_PIN BIT(26)
52 #define INT_RDY_SR BIT(25)
53 #define INT_LNR_SUSP BIT(24)
54 #define INT_ECC_ERR BIT(17)
55 #define INT_CRC_ERR BIT(16)
56 #define INT_LWR_DIS BIT(12)
57 #define INT_LRD_DIS BIT(11)
58 #define INT_SDMA_INT BIT(10)
59 #define INT_DMA_FINISH BIT(9)
60 #define INT_RX_NOT_FULL BIT(3)
61 #define INT_RX_NOT_EMPTY BIT(2)
62 #define INT_TX_NOT_FULL BIT(1)
63 #define INT_TX_EMPTY BIT(0)
64
65 #define HC_EN 0x10
66 #define HC_EN_BIT BIT(0)
67
68 #define TXD(x) (0x14 + ((x) * 4))
69 #define RXD 0x24
70
71 #define SS_CTRL(s) (0x30 + ((s) * 4))
72 #define LRD_CFG 0x44
73 #define LWR_CFG 0x80
74 #define RWW_CFG 0x70
75 #define OP_READ BIT(23)
76 #define OP_DUMMY_CYC(x) ((x) << 17)
77 #define OP_ADDR_BYTES(x) ((x) << 14)
78 #define OP_CMD_BYTES(x) (((x) - 1) << 13)
79 #define OP_OCTA_CRC_EN BIT(12)
80 #define OP_DQS_EN BIT(11)
81 #define OP_ENHC_EN BIT(10)
82 #define OP_PREAMBLE_EN BIT(9)
83 #define OP_DATA_DDR BIT(8)
84 #define OP_DATA_BUSW(x) ((x) << 6)
85 #define OP_ADDR_DDR BIT(5)
86 #define OP_ADDR_BUSW(x) ((x) << 3)
87 #define OP_CMD_DDR BIT(2)
88 #define OP_CMD_BUSW(x) (x)
89 #define OP_BUSW_1 0
90 #define OP_BUSW_2 1
91 #define OP_BUSW_4 2
92 #define OP_BUSW_8 3
93
94 #define OCTA_CRC 0x38
95 #define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16))
96 #define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16)))
97 #define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16))
98
99 #define ONFI_DIN_CNT(s) (0x3c + (s))
100
101 #define LRD_CTRL 0x48
102 #define RWW_CTRL 0x74
103 #define LWR_CTRL 0x84
104 #define LMODE_EN BIT(31)
105 #define LMODE_SLV_ACT(x) ((x) << 21)
106 #define LMODE_CMD1(x) ((x) << 8)
107 #define LMODE_CMD0(x) (x)
108
109 #define LRD_ADDR 0x4c
110 #define LWR_ADDR 0x88
111 #define LRD_RANGE 0x50
112 #define LWR_RANGE 0x8c
113
114 #define AXI_SLV_ADDR 0x54
115
116 #define DMAC_RD_CFG 0x58
117 #define DMAC_WR_CFG 0x94
118 #define DMAC_CFG_PERIPH_EN BIT(31)
119 #define DMAC_CFG_ALLFLUSH_EN BIT(30)
120 #define DMAC_CFG_LASTFLUSH_EN BIT(29)
121 #define DMAC_CFG_QE(x) (((x) + 1) << 16)
122 #define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12)
123 #define DMAC_CFG_BURST_SZ(x) ((x) << 8)
124 #define DMAC_CFG_DIR_READ BIT(1)
125 #define DMAC_CFG_START BIT(0)
126
127 #define DMAC_RD_CNT 0x5c
128 #define DMAC_WR_CNT 0x98
129
130 #define SDMA_ADDR 0x60
131
132 #define DMAM_CFG 0x64
133 #define DMAM_CFG_START BIT(31)
134 #define DMAM_CFG_CONT BIT(30)
135 #define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2)
136 #define DMAM_CFG_DIR_READ BIT(1)
137 #define DMAM_CFG_EN BIT(0)
138
139 #define DMAM_CNT 0x68
140
141 #define LNR_TIMER_TH 0x6c
142
143 #define RDM_CFG0 0x78
144 #define RDM_CFG0_POLY(x) (x)
145
146 #define RDM_CFG1 0x7c
147 #define RDM_CFG1_RDM_EN BIT(31)
148 #define RDM_CFG1_SEED(x) (x)
149
150 #define LWR_SUSP_CTRL 0x90
151 #define LWR_SUSP_CTRL_EN BIT(31)
152
153 #define DMAS_CTRL 0x9c
154 #define DMAS_CTRL_EN BIT(31)
155 #define DMAS_CTRL_DIR_READ BIT(30)
156
157 #define DATA_STROB 0xa0
158 #define DATA_STROB_EDO_EN BIT(2)
159 #define DATA_STROB_INV_POL BIT(1)
160 #define DATA_STROB_DELAY_2CYC BIT(0)
161
162 #define IDLY_CODE(x) (0xa4 + ((x) * 4))
163 #define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8))
164
165 #define GPIO 0xc4
166 #define GPIO_PT(x) BIT(3 + ((x) * 16))
167 #define GPIO_RESET(x) BIT(2 + ((x) * 16))
168 #define GPIO_HOLDB(x) BIT(1 + ((x) * 16))
169 #define GPIO_WPB(x) BIT((x) * 16)
170
171 #define HC_VER 0xd0
172
173 #define HW_TEST(x) (0xe0 + ((x) * 4))
174
175 #define MXIC_NFC_MAX_CLK_HZ 50000000
176 #define IRQ_TIMEOUT 1000
177
178 struct mxic_nand_ctrl {
179 struct clk *send_clk;
180 struct clk *send_dly_clk;
181 void __iomem *regs;
182 struct nand_chip nand_chip;
183 };
184
185 /*
186 * struct mxic_nfc_command_format - Defines NAND flash command format
187 * @start_cmd: First cycle command (Start command)
188 * @end_cmd: Second cycle command (Last command)
189 * @addr_len: Number of address cycles required to send the address
190 * @read: Direction of command
191 */
192
193 struct mxic_nfc_command_format {
194 int start_cmd;
195 int end_cmd;
196 u8 addr_len;
197 bool read;
198 };
199
200 /* The NAND flash operations command format */
201 static const struct mxic_nfc_command_format mxic_nand_commands[] = {
202 {NAND_CMD_READ0, NAND_CMD_READSTART, 5, 1 },
203 {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, 1 },
204 {NAND_CMD_READID, NAND_CMD_NONE, 1, 1 },
205 {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 1 },
206 {NAND_CMD_SEQIN, NAND_CMD_NONE, 5, 0 },
207 {NAND_CMD_PAGEPROG, NAND_CMD_NONE, 0, 0 },
208 {NAND_CMD_CACHEDPROG, NAND_CMD_NONE, 0, 0 },
209 {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0 },
210 {NAND_CMD_ERASE1, NAND_CMD_NONE, 3, 0 },
211 {NAND_CMD_ERASE2, NAND_CMD_NONE, 0, 0 },
212 {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0 },
213 {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 1 },
214 {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 1 },
215 {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0 },
216 {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0 },
217 };
218
mxic_nfc_clk_enable(struct mxic_nand_ctrl * nfc)219 static int mxic_nfc_clk_enable(struct mxic_nand_ctrl *nfc)
220 {
221 int ret;
222
223 ret = clk_prepare_enable(nfc->send_clk);
224 if (ret)
225 return ret;
226
227 ret = clk_prepare_enable(nfc->send_dly_clk);
228 if (ret)
229 goto err_send_dly_clk;
230
231 return ret;
232
233 err_send_dly_clk:
234 clk_disable_unprepare(nfc->send_clk);
235
236 return ret;
237 }
238
mxic_nfc_clk_disable(struct mxic_nand_ctrl * nfc)239 static void mxic_nfc_clk_disable(struct mxic_nand_ctrl *nfc)
240 {
241 clk_disable_unprepare(nfc->send_clk);
242 clk_disable_unprepare(nfc->send_dly_clk);
243 }
244
mxic_nfc_set_input_delay(struct mxic_nand_ctrl * nfc,u8 idly_code)245 static void mxic_nfc_set_input_delay(struct mxic_nand_ctrl *nfc, u8 idly_code)
246 {
247 writel(IDLY_CODE_VAL(0, idly_code) |
248 IDLY_CODE_VAL(1, idly_code) |
249 IDLY_CODE_VAL(2, idly_code) |
250 IDLY_CODE_VAL(3, idly_code),
251 nfc->regs + IDLY_CODE(0));
252 writel(IDLY_CODE_VAL(4, idly_code) |
253 IDLY_CODE_VAL(5, idly_code) |
254 IDLY_CODE_VAL(6, idly_code) |
255 IDLY_CODE_VAL(7, idly_code),
256 nfc->regs + IDLY_CODE(1));
257 }
258
mxic_nfc_clk_setup(struct mxic_nand_ctrl * nfc,unsigned long freq)259 static int mxic_nfc_clk_setup(struct mxic_nand_ctrl *nfc, unsigned long freq)
260 {
261 int ret;
262
263 ret = clk_set_rate(nfc->send_clk, freq);
264 if (ret)
265 return ret;
266
267 ret = clk_set_rate(nfc->send_dly_clk, freq);
268 if (ret)
269 return ret;
270
271 /*
272 * A constant delay range from 0x0 ~ 0x1F for input delay,
273 * the unit is 78 ps, the max input delay is 2.418 ns.
274 */
275 mxic_nfc_set_input_delay(nfc, 0xf);
276
277 return 0;
278 }
279
mxic_nfc_set_freq(struct mxic_nand_ctrl * nfc,unsigned long freq)280 static int mxic_nfc_set_freq(struct mxic_nand_ctrl *nfc, unsigned long freq)
281 {
282 int ret;
283
284 if (freq > MXIC_NFC_MAX_CLK_HZ)
285 freq = MXIC_NFC_MAX_CLK_HZ;
286
287 mxic_nfc_clk_disable(nfc);
288 ret = mxic_nfc_clk_setup(nfc, freq);
289 if (ret)
290 return ret;
291
292 ret = mxic_nfc_clk_enable(nfc);
293 if (ret)
294 return ret;
295
296 return 0;
297 }
298
mxic_nfc_hw_init(struct mxic_nand_ctrl * nfc)299 static void mxic_nfc_hw_init(struct mxic_nand_ctrl *nfc)
300 {
301 writel(HC_CFG_NIO(8) | HC_CFG_TYPE(1, HC_CFG_TYPE_RAW_NAND) |
302 HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN |
303 HC_CFG_IDLE_SIO_LVL(1), nfc->regs + HC_CFG);
304 writel(INT_STS_ALL, nfc->regs + INT_STS_EN);
305 writel(INT_RDY_PIN, nfc->regs + INT_SIG_EN);
306 writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
307 writel(0, nfc->regs + LRD_CFG);
308 writel(0, nfc->regs + LRD_CTRL);
309 writel(0x0, nfc->regs + HC_EN);
310 }
311
mxic_nfc_cs_enable(struct mxic_nand_ctrl * nfc)312 static void mxic_nfc_cs_enable(struct mxic_nand_ctrl *nfc)
313 {
314 writel(readl(nfc->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
315 nfc->regs + HC_CFG);
316 writel(HC_CFG_MAN_CS_ASSERT | readl(nfc->regs + HC_CFG),
317 nfc->regs + HC_CFG);
318 }
319
mxic_nfc_cs_disable(struct mxic_nand_ctrl * nfc)320 static void mxic_nfc_cs_disable(struct mxic_nand_ctrl *nfc)
321 {
322 writel(~HC_CFG_MAN_CS_ASSERT & readl(nfc->regs + HC_CFG),
323 nfc->regs + HC_CFG);
324 }
325
mxic_nfc_data_xfer(struct mxic_nand_ctrl * nfc,const void * txbuf,void * rxbuf,unsigned int len)326 static int mxic_nfc_data_xfer(struct mxic_nand_ctrl *nfc, const void *txbuf,
327 void *rxbuf, unsigned int len)
328 {
329 unsigned int pos = 0;
330
331 while (pos < len) {
332 unsigned int nbytes = len - pos;
333 u32 data = 0xffffffff;
334 u32 sts;
335 int ret;
336
337 if (nbytes > 4)
338 nbytes = 4;
339
340 if (txbuf)
341 memcpy(&data, txbuf + pos, nbytes);
342
343 ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
344 sts & INT_TX_EMPTY, 1000000);
345 if (ret)
346 return ret;
347
348 writel(data, nfc->regs + TXD(nbytes % 4));
349
350 ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
351 sts & INT_TX_EMPTY, 1000000);
352 if (ret)
353 return ret;
354
355 ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
356 sts & INT_RX_NOT_EMPTY, 1000000);
357 if (ret)
358 return ret;
359
360 data = readl(nfc->regs + RXD);
361 if (rxbuf) {
362 data >>= (8 * (4 - nbytes));
363 memcpy(rxbuf + pos, &data, nbytes);
364 }
365
366 WARN_ON(readl(nfc->regs + INT_STS) & INT_RX_NOT_EMPTY);
367
368 pos += nbytes;
369 }
370
371 return 0;
372 }
373
mxic_nfc_read_byte(struct mtd_info * mtd)374 static uint8_t mxic_nfc_read_byte(struct mtd_info *mtd)
375 {
376 struct nand_chip *chip = mtd_to_nand(mtd);
377 struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
378 u8 data;
379
380 writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
381 writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
382 OP_READ, nfc->regs + SS_CTRL(0));
383
384 mxic_nfc_data_xfer(nfc, NULL, &data, 1);
385
386 return data;
387 }
388
mxic_nfc_read_buf(struct mtd_info * mtd,uint8_t * rxbuf,int rlen)389 static void mxic_nfc_read_buf(struct mtd_info *mtd, uint8_t *rxbuf, int rlen)
390 {
391 struct nand_chip *chip = mtd_to_nand(mtd);
392 struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
393
394 writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
395 writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
396 OP_READ, nfc->regs + SS_CTRL(0));
397
398 mxic_nfc_data_xfer(nfc, NULL, rxbuf, rlen);
399 }
400
mxic_nfc_write_buf(struct mtd_info * mtd,const uint8_t * txbuf,int wlen)401 static void mxic_nfc_write_buf(struct mtd_info *mtd, const uint8_t *txbuf,
402 int wlen)
403 {
404 struct nand_chip *chip = mtd_to_nand(mtd);
405 struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
406
407 writel(wlen, nfc->regs + ONFI_DIN_CNT(0));
408 writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F),
409 nfc->regs + SS_CTRL(0));
410
411 mxic_nfc_data_xfer(nfc, txbuf, NULL, wlen);
412 }
413
mxic_nfc_cmd_function(struct mtd_info * mtd,unsigned int command,int column,int page_addr)414 static void mxic_nfc_cmd_function(struct mtd_info *mtd, unsigned int command,
415 int column, int page_addr)
416 {
417 struct nand_chip *chip = mtd_to_nand(mtd);
418 struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
419 const struct mxic_nfc_command_format *cmd = NULL;
420 u32 sts;
421 u8 index, addr[5];
422
423 /* Emulate NAND_CMD_READOOB */
424 if (command == NAND_CMD_READOOB) {
425 column += mtd->writesize;
426 command = NAND_CMD_READ0;
427 }
428
429 /* Get the command format */
430 for (index = 0; index < ARRAY_SIZE(mxic_nand_commands); index++)
431 if (command == mxic_nand_commands[index].start_cmd)
432 break;
433
434 cmd = &mxic_nand_commands[index];
435
436 if (!(command == NAND_CMD_PAGEPROG ||
437 command == NAND_CMD_CACHEDPROG ||
438 command == NAND_CMD_ERASE2))
439 mxic_nfc_cs_disable(nfc);
440
441 mxic_nfc_cs_enable(nfc);
442
443 if (column != -1) {
444 addr[0] = column;
445 addr[1] = column >> 8;
446
447 if (page_addr != -1) {
448 addr[2] = page_addr;
449 addr[3] = page_addr >> 8;
450 addr[4] = page_addr >> 16;
451 }
452 } else if (page_addr != -1) {
453 addr[0] = page_addr;
454 addr[1] = page_addr >> 8;
455 addr[2] = page_addr >> 16;
456 }
457
458 writel(0, nfc->regs + HC_EN);
459 writel(HC_EN_BIT, nfc->regs + HC_EN);
460 writel(OP_CMD_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | OP_CMD_BYTES(0),
461 nfc->regs + SS_CTRL(0));
462
463 mxic_nfc_data_xfer(nfc, &cmd->start_cmd, NULL, 1);
464
465 if (cmd->addr_len) {
466 writel(OP_ADDR_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
467 OP_ADDR_BYTES(cmd->addr_len), nfc->regs + SS_CTRL(0));
468
469 mxic_nfc_data_xfer(nfc, &addr, NULL, cmd->addr_len);
470 }
471
472 if (cmd->end_cmd != NAND_CMD_NONE) {
473 writel(0, nfc->regs + HC_EN);
474 writel(HC_EN_BIT, nfc->regs + HC_EN);
475 writel(OP_CMD_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
476 OP_CMD_BYTES(0), nfc->regs + SS_CTRL(0));
477
478 mxic_nfc_data_xfer(nfc, &cmd->end_cmd, NULL, 1);
479 }
480
481 readl_poll_timeout(nfc->regs + INT_STS, sts, sts & INT_RDY_PIN,
482 1000000);
483
484 if (command == NAND_CMD_PAGEPROG ||
485 command == NAND_CMD_CACHEDPROG ||
486 command == NAND_CMD_ERASE2 ||
487 command == NAND_CMD_RESET) {
488 mxic_nfc_cs_disable(nfc);
489 }
490 }
491
mxic_nfc_setup_data_interface(struct mtd_info * mtd,int chipnr,const struct nand_data_interface * conf)492 static int mxic_nfc_setup_data_interface(struct mtd_info *mtd, int chipnr,
493 const struct nand_data_interface *conf)
494 {
495 struct nand_chip *chip = mtd_to_nand(mtd);
496 struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip);
497 const struct nand_sdr_timings *sdr;
498 unsigned long freq;
499 int ret;
500
501 sdr = nand_get_sdr_timings(conf);
502 if (IS_ERR(sdr))
503 return PTR_ERR(sdr);
504
505 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
506 return 0;
507
508 freq = 1000000000 / (sdr->tRC_min / 1000);
509
510 ret = mxic_nfc_set_freq(nfc, freq);
511 if (ret)
512 WARN_ON("Set freq failed\n");
513
514 if (sdr->tRC_min < 30000)
515 writel(DATA_STROB_EDO_EN, nfc->regs + DATA_STROB);
516
517 return 0;
518 }
519
520 /* Dummy implementation: we don't support multiple chips */
mxic_nfc_select_chip(struct mtd_info * mtd,int chipnr)521 static void mxic_nfc_select_chip(struct mtd_info *mtd, int chipnr)
522 {
523 switch (chipnr) {
524 case -1:
525 case 0:
526 break;
527
528 default:
529 BUG();
530 }
531 }
532
mxic_nfc_probe(struct udevice * dev)533 static int mxic_nfc_probe(struct udevice *dev)
534 {
535 struct mxic_nand_ctrl *nfc = dev_get_priv(dev);
536 struct nand_chip *nand_chip = &nfc->nand_chip;
537 struct mtd_info *mtd;
538 ofnode child;
539 int err;
540
541 nfc->regs = dev_read_addr_ptr(dev);
542
543 nfc->send_clk = devm_clk_get(dev, "send");
544 if (IS_ERR(nfc->send_clk))
545 return PTR_ERR(nfc->send_clk);
546
547 nfc->send_dly_clk = devm_clk_get(dev, "send_dly");
548 if (IS_ERR(nfc->send_dly_clk))
549 return PTR_ERR(nfc->send_dly_clk);
550
551 mtd = nand_to_mtd(nand_chip);
552
553 ofnode_for_each_subnode(child, dev_ofnode(dev))
554 nand_set_flash_node(nand_chip, child);
555
556 nand_set_controller_data(nand_chip, nfc);
557
558 nand_chip->select_chip = mxic_nfc_select_chip;
559 nand_chip->setup_data_interface = mxic_nfc_setup_data_interface;
560 nand_chip->cmdfunc = mxic_nfc_cmd_function;
561 nand_chip->read_byte = mxic_nfc_read_byte;
562 nand_chip->read_buf = mxic_nfc_read_buf;
563 nand_chip->write_buf = mxic_nfc_write_buf;
564
565 mxic_nfc_hw_init(nfc);
566
567 err = nand_scan(mtd, 1);
568 if (err)
569 return err;
570
571 err = nand_register(0, mtd);
572 if (err) {
573 dev_err(dev, "Failed to register MTD: %d\n", err);
574 return err;
575 }
576
577 return 0;
578 }
579
580 static const struct udevice_id mxic_nfc_of_ids[] = {
581 { .compatible = "mxic,multi-itfc-v009-nand-controller" },
582 { /* Sentinel */ }
583 };
584
585 U_BOOT_DRIVER(mxic_nfc) = {
586 .name = "mxic_nfc",
587 .id = UCLASS_MTD,
588 .of_match = mxic_nfc_of_ids,
589 .probe = mxic_nfc_probe,
590 .priv_auto = sizeof(struct mxic_nand_ctrl),
591 };
592
board_nand_init(void)593 void board_nand_init(void)
594 {
595 struct udevice *dev;
596 int ret;
597
598 ret = uclass_get_device_by_driver(UCLASS_MTD,
599 DM_DRIVER_GET(mxic_nfc), &dev);
600 if (ret && ret != -ENODEV)
601 pr_err("Failed to initialize %s. (error %d)\n", dev->name,
602 ret);
603 }
604