1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
4 *
5 * Authors:
6 * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <fdt_support.h>
12 #include <linux/errno.h>
13 #include "nvmxip.h"
14
15 #include <asm/global_data.h>
16 DECLARE_GLOBAL_DATA_PTR;
17
18 #define NVMXIP_QSPI_DRV_NAME "nvmxip_qspi"
19
20 /**
21 * nvmxip_qspi_of_to_plat() -read from DT
22 * @dev: the NVMXIP device
23 *
24 * Read from the DT the NVMXIP information.
25 *
26 * Return:
27 *
28 * 0 on success. Otherwise, failure
29 */
nvmxip_qspi_of_to_plat(struct udevice * dev)30 static int nvmxip_qspi_of_to_plat(struct udevice *dev)
31 {
32 struct nvmxip_plat *plat = dev_get_plat(dev);
33 int ret;
34
35 plat->phys_base = (phys_addr_t)dev_read_addr(dev);
36 if (plat->phys_base == FDT_ADDR_T_NONE) {
37 log_err("[%s]: can not get base address from device tree\n", dev->name);
38 return -EINVAL;
39 }
40
41 ret = dev_read_u32(dev, "lba_shift", &plat->lba_shift);
42 if (ret) {
43 log_err("[%s]: can not get lba_shift from device tree\n", dev->name);
44 return -EINVAL;
45 }
46
47 ret = dev_read_u32(dev, "lba", (u32 *)&plat->lba);
48 if (ret) {
49 log_err("[%s]: can not get lba from device tree\n", dev->name);
50 return -EINVAL;
51 }
52
53 log_debug("[%s]: XIP device base addr: 0x%llx , lba_shift: %d , lbas: %lu\n",
54 dev->name, plat->phys_base, plat->lba_shift, plat->lba);
55
56 return 0;
57 }
58
59 static const struct udevice_id nvmxip_qspi_ids[] = {
60 { .compatible = "nvmxip,qspi" },
61 { /* sentinel */ }
62 };
63
64 U_BOOT_DRIVER(nvmxip_qspi) = {
65 .name = NVMXIP_QSPI_DRV_NAME,
66 .id = UCLASS_NVMXIP,
67 .of_match = nvmxip_qspi_ids,
68 .of_to_plat = nvmxip_qspi_of_to_plat,
69 .plat_auto = sizeof(struct nvmxip_plat),
70 };
71