1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Atmel DataFlash probing
4 *
5 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
6 * Haikun Wang (haikun.wang@freescale.com)
7 */
8
9 #include <common.h>
10 #include <display_options.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <fdtdec.h>
14 #include <log.h>
15 #include <spi.h>
16 #include <spi_flash.h>
17 #include <div64.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/math64.h>
21
22 #include "sf_internal.h"
23
24 #define CMD_READ_ID 0x9f
25 /* reads can bypass the buffers */
26 #define OP_READ_CONTINUOUS 0xE8
27 #define OP_READ_PAGE 0xD2
28
29 /* group B requests can run even while status reports "busy" */
30 #define OP_READ_STATUS 0xD7 /* group B */
31
32 /* move data between host and buffer */
33 #define OP_READ_BUFFER1 0xD4 /* group B */
34 #define OP_READ_BUFFER2 0xD6 /* group B */
35 #define OP_WRITE_BUFFER1 0x84 /* group B */
36 #define OP_WRITE_BUFFER2 0x87 /* group B */
37
38 /* erasing flash */
39 #define OP_ERASE_PAGE 0x81
40 #define OP_ERASE_BLOCK 0x50
41
42 /* move data between buffer and flash */
43 #define OP_TRANSFER_BUF1 0x53
44 #define OP_TRANSFER_BUF2 0x55
45 #define OP_MREAD_BUFFER1 0xD4
46 #define OP_MREAD_BUFFER2 0xD6
47 #define OP_MWERASE_BUFFER1 0x83
48 #define OP_MWERASE_BUFFER2 0x86
49 #define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */
50 #define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */
51
52 /* write to buffer, then write-erase to flash */
53 #define OP_PROGRAM_VIA_BUF1 0x82
54 #define OP_PROGRAM_VIA_BUF2 0x85
55
56 /* compare buffer to flash */
57 #define OP_COMPARE_BUF1 0x60
58 #define OP_COMPARE_BUF2 0x61
59
60 /* read flash to buffer, then write-erase to flash */
61 #define OP_REWRITE_VIA_BUF1 0x58
62 #define OP_REWRITE_VIA_BUF2 0x59
63
64 /*
65 * newer chips report JEDEC manufacturer and device IDs; chip
66 * serial number and OTP bits; and per-sector writeprotect.
67 */
68 #define OP_READ_ID 0x9F
69 #define OP_READ_SECURITY 0x77
70 #define OP_WRITE_SECURITY_REVC 0x9A
71 #define OP_WRITE_SECURITY 0x9B /* revision D */
72
73 #define DATAFLASH_SHIFT_EXTID 24
74 #define DATAFLASH_SHIFT_ID 40
75
76 struct dataflash {
77 uint8_t command[16];
78 unsigned short page_offset; /* offset in flash address */
79 };
80
81 /* Return the status of the DataFlash device */
dataflash_status(struct spi_slave * spi)82 static inline int dataflash_status(struct spi_slave *spi)
83 {
84 int ret;
85 u8 opcode = OP_READ_STATUS;
86 u8 status;
87
88 /*
89 * NOTE: at45db321c over 25 MHz wants to write
90 * a dummy byte after the opcode...
91 */
92 ret = spi_write_then_read(spi, &opcode, 1, NULL, &status, 1);
93 return ret ? -EIO : status;
94 }
95
96 /*
97 * Poll the DataFlash device until it is READY.
98 * This usually takes 5-20 msec or so; more for sector erase.
99 * ready: return > 0
100 */
dataflash_waitready(struct spi_slave * spi)101 static int dataflash_waitready(struct spi_slave *spi)
102 {
103 int status;
104 int timeout = 2 * CONFIG_SYS_HZ;
105 int timebase;
106
107 timebase = get_timer(0);
108 do {
109 status = dataflash_status(spi);
110 if (status < 0)
111 status = 0;
112
113 if (status & (1 << 7)) /* RDY/nBSY */
114 return status;
115
116 mdelay(3);
117 } while (get_timer(timebase) < timeout);
118
119 return -ETIME;
120 }
121
122 /* Erase pages of flash */
spi_dataflash_erase(struct udevice * dev,u32 offset,size_t len)123 static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
124 {
125 struct dataflash *dataflash;
126 struct spi_flash *spi_flash;
127 struct spi_slave *spi;
128 unsigned blocksize;
129 uint8_t *command;
130 uint32_t rem;
131 int status;
132
133 dataflash = dev_get_priv(dev);
134 spi_flash = dev_get_uclass_priv(dev);
135 spi = spi_flash->spi;
136
137 blocksize = spi_flash->page_size << 3;
138
139 memset(dataflash->command, 0 , sizeof(dataflash->command));
140 command = dataflash->command;
141
142 debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
143
144 div_u64_rem(len, spi_flash->page_size, &rem);
145 if (rem) {
146 printf("%s: len(0x%x) isn't the multiple of page size(0x%x)\n",
147 dev->name, len, spi_flash->page_size);
148 return -EINVAL;
149 }
150 div_u64_rem(offset, spi_flash->page_size, &rem);
151 if (rem) {
152 printf("%s: offset(0x%x) isn't the multiple of page size(0x%x)\n",
153 dev->name, offset, spi_flash->page_size);
154 return -EINVAL;
155 }
156
157 status = spi_claim_bus(spi);
158 if (status) {
159 debug("dataflash: unable to claim SPI bus\n");
160 return status;
161 }
162
163 while (len > 0) {
164 unsigned int pageaddr;
165 int do_block;
166 /*
167 * Calculate flash page address; use block erase (for speed) if
168 * we're at a block boundary and need to erase the whole block.
169 */
170 pageaddr = div_u64(offset, spi_flash->page_size);
171 do_block = (pageaddr & 0x7) == 0 && len >= blocksize;
172 pageaddr = pageaddr << dataflash->page_offset;
173
174 command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
175 command[1] = (uint8_t)(pageaddr >> 16);
176 command[2] = (uint8_t)(pageaddr >> 8);
177 command[3] = 0;
178
179 debug("%s ERASE %s: (%x) %x %x %x [%d]\n",
180 dev->name, do_block ? "block" : "page",
181 command[0], command[1], command[2], command[3],
182 pageaddr);
183
184 status = spi_write_then_read(spi, command, 4, NULL, NULL, 0);
185 if (status < 0) {
186 debug("%s: erase send command error!\n", dev->name);
187 return -EIO;
188 }
189
190 status = dataflash_waitready(spi);
191 if (status < 0) {
192 debug("%s: erase waitready error!\n", dev->name);
193 return status;
194 }
195
196 if (do_block) {
197 offset += blocksize;
198 len -= blocksize;
199 } else {
200 offset += spi_flash->page_size;
201 len -= spi_flash->page_size;
202 }
203 }
204
205 spi_release_bus(spi);
206
207 return 0;
208 }
209
210 /*
211 * Read from the DataFlash device.
212 * offset : Start offset in flash device
213 * len : Amount to read
214 * buf : Buffer containing the data
215 */
spi_dataflash_read(struct udevice * dev,u32 offset,size_t len,void * buf)216 static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len,
217 void *buf)
218 {
219 struct dataflash *dataflash;
220 struct spi_flash *spi_flash;
221 struct spi_slave *spi;
222 unsigned int addr;
223 uint8_t *command;
224 int status;
225
226 dataflash = dev_get_priv(dev);
227 spi_flash = dev_get_uclass_priv(dev);
228 spi = spi_flash->spi;
229
230 memset(dataflash->command, 0 , sizeof(dataflash->command));
231 command = dataflash->command;
232
233 debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
234 debug("READ: (%x) %x %x %x\n",
235 command[0], command[1], command[2], command[3]);
236
237 /* Calculate flash page/byte address */
238 addr = (((unsigned)offset / spi_flash->page_size)
239 << dataflash->page_offset)
240 + ((unsigned)offset % spi_flash->page_size);
241
242 status = spi_claim_bus(spi);
243 if (status) {
244 debug("dataflash: unable to claim SPI bus\n");
245 return status;
246 }
247
248 /*
249 * Continuous read, max clock = f(car) which may be less than
250 * the peak rate available. Some chips support commands with
251 * fewer "don't care" bytes. Both buffers stay unchanged.
252 */
253 command[0] = OP_READ_CONTINUOUS;
254 command[1] = (uint8_t)(addr >> 16);
255 command[2] = (uint8_t)(addr >> 8);
256 command[3] = (uint8_t)(addr >> 0);
257
258 /* plus 4 "don't care" bytes, command len: 4 + 4 "don't care" bytes */
259 status = spi_write_then_read(spi, command, 8, NULL, buf, len);
260
261 spi_release_bus(spi);
262
263 return status;
264 }
265
266 /*
267 * Write to the DataFlash device.
268 * offset : Start offset in flash device
269 * len : Amount to write
270 * buf : Buffer containing the data
271 */
spi_dataflash_write(struct udevice * dev,u32 offset,size_t len,const void * buf)272 int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
273 const void *buf)
274 {
275 struct dataflash *dataflash;
276 struct spi_flash *spi_flash;
277 struct spi_slave *spi;
278 uint8_t *command;
279 unsigned int pageaddr, addr, to, writelen;
280 size_t remaining = len;
281 u_char *writebuf = (u_char *)buf;
282 int status = -EINVAL;
283
284 dataflash = dev_get_priv(dev);
285 spi_flash = dev_get_uclass_priv(dev);
286 spi = spi_flash->spi;
287
288 memset(dataflash->command, 0 , sizeof(dataflash->command));
289 command = dataflash->command;
290
291 debug("%s: write 0x%x..0x%x\n", dev->name, offset, (offset + len));
292
293 pageaddr = ((unsigned)offset / spi_flash->page_size);
294 to = ((unsigned)offset % spi_flash->page_size);
295 if (to + len > spi_flash->page_size)
296 writelen = spi_flash->page_size - to;
297 else
298 writelen = len;
299
300 status = spi_claim_bus(spi);
301 if (status) {
302 debug("dataflash: unable to claim SPI bus\n");
303 return status;
304 }
305
306 while (remaining > 0) {
307 debug("write @ %d:%d len=%d\n", pageaddr, to, writelen);
308
309 /*
310 * REVISIT:
311 * (a) each page in a sector must be rewritten at least
312 * once every 10K sibling erase/program operations.
313 * (b) for pages that are already erased, we could
314 * use WRITE+MWRITE not PROGRAM for ~30% speedup.
315 * (c) WRITE to buffer could be done while waiting for
316 * a previous MWRITE/MWERASE to complete ...
317 * (d) error handling here seems to be mostly missing.
318 *
319 * Two persistent bits per page, plus a per-sector counter,
320 * could support (a) and (b) ... we might consider using
321 * the second half of sector zero, which is just one block,
322 * to track that state. (On AT91, that sector should also
323 * support boot-from-DataFlash.)
324 */
325
326 addr = pageaddr << dataflash->page_offset;
327
328 /* (1) Maybe transfer partial page to Buffer1 */
329 if (writelen != spi_flash->page_size) {
330 command[0] = OP_TRANSFER_BUF1;
331 command[1] = (addr & 0x00FF0000) >> 16;
332 command[2] = (addr & 0x0000FF00) >> 8;
333 command[3] = 0;
334
335 debug("TRANSFER: (%x) %x %x %x\n",
336 command[0], command[1], command[2], command[3]);
337
338 status = spi_write_then_read(spi, command, 4,
339 NULL, NULL, 0);
340 if (status < 0) {
341 debug("%s: write(<pagesize) command error!\n",
342 dev->name);
343 return -EIO;
344 }
345
346 status = dataflash_waitready(spi);
347 if (status < 0) {
348 debug("%s: write(<pagesize) waitready error!\n",
349 dev->name);
350 return status;
351 }
352 }
353
354 /* (2) Program full page via Buffer1 */
355 addr += to;
356 command[0] = OP_PROGRAM_VIA_BUF1;
357 command[1] = (addr & 0x00FF0000) >> 16;
358 command[2] = (addr & 0x0000FF00) >> 8;
359 command[3] = (addr & 0x000000FF);
360
361 debug("PROGRAM: (%x) %x %x %x\n",
362 command[0], command[1], command[2], command[3]);
363
364 status = spi_write_then_read(spi, command, 4,
365 writebuf, NULL, writelen);
366 if (status < 0) {
367 debug("%s: write send command error!\n", dev->name);
368 return -EIO;
369 }
370
371 status = dataflash_waitready(spi);
372 if (status < 0) {
373 debug("%s: write waitready error!\n", dev->name);
374 return status;
375 }
376
377 #ifdef CONFIG_SPI_DATAFLASH_WRITE_VERIFY
378 /* (3) Compare to Buffer1 */
379 addr = pageaddr << dataflash->page_offset;
380 command[0] = OP_COMPARE_BUF1;
381 command[1] = (addr & 0x00FF0000) >> 16;
382 command[2] = (addr & 0x0000FF00) >> 8;
383 command[3] = 0;
384
385 debug("COMPARE: (%x) %x %x %x\n",
386 command[0], command[1], command[2], command[3]);
387
388 status = spi_write_then_read(spi, command, 4,
389 writebuf, NULL, writelen);
390 if (status < 0) {
391 debug("%s: write(compare) send command error!\n",
392 dev->name);
393 return -EIO;
394 }
395
396 status = dataflash_waitready(spi);
397
398 /* Check result of the compare operation */
399 if (status & (1 << 6)) {
400 printf("dataflash: write compare page %u, err %d\n",
401 pageaddr, status);
402 remaining = 0;
403 status = -EIO;
404 break;
405 } else {
406 status = 0;
407 }
408
409 #endif /* CONFIG_SPI_DATAFLASH_WRITE_VERIFY */
410 remaining = remaining - writelen;
411 pageaddr++;
412 to = 0;
413 writebuf += writelen;
414
415 if (remaining > spi_flash->page_size)
416 writelen = spi_flash->page_size;
417 else
418 writelen = remaining;
419 }
420
421 spi_release_bus(spi);
422
423 return 0;
424 }
425
add_dataflash(struct udevice * dev,char * name,int nr_pages,int pagesize,int pageoffset,char revision)426 static int add_dataflash(struct udevice *dev, char *name, int nr_pages,
427 int pagesize, int pageoffset, char revision)
428 {
429 struct spi_flash *spi_flash;
430 struct dataflash *dataflash;
431
432 dataflash = dev_get_priv(dev);
433 spi_flash = dev_get_uclass_priv(dev);
434
435 dataflash->page_offset = pageoffset;
436
437 spi_flash->name = name;
438 spi_flash->page_size = pagesize;
439 spi_flash->size = nr_pages * pagesize;
440 spi_flash->erase_size = pagesize;
441
442 #ifndef CONFIG_SPL_BUILD
443 printf("SPI DataFlash: Detected %s with page size ", spi_flash->name);
444 print_size(spi_flash->page_size, ", erase size ");
445 print_size(spi_flash->erase_size, ", total ");
446 print_size(spi_flash->size, "");
447 printf(", revision %c", revision);
448 puts("\n");
449 #endif
450
451 return 0;
452 }
453
454 struct data_flash_info {
455 char *name;
456
457 /*
458 * JEDEC id has a high byte of zero plus three data bytes:
459 * the manufacturer id, then a two byte device id.
460 */
461 uint64_t jedec_id;
462
463 /* The size listed here is what works with OP_ERASE_PAGE. */
464 unsigned nr_pages;
465 uint16_t pagesize;
466 uint16_t pageoffset;
467
468 uint16_t flags;
469 #define SUP_EXTID 0x0004 /* supports extended ID data */
470 #define SUP_POW2PS 0x0002 /* supports 2^N byte pages */
471 #define IS_POW2PS 0x0001 /* uses 2^N byte pages */
472 };
473
474 static struct data_flash_info dataflash_data[] = {
475 /*
476 * NOTE: chips with SUP_POW2PS (rev D and up) need two entries,
477 * one with IS_POW2PS and the other without. The entry with the
478 * non-2^N byte page size can't name exact chip revisions without
479 * losing backwards compatibility for cmdlinepart.
480 *
481 * Those two entries have different name spelling format in order to
482 * show their difference obviously.
483 * The upper case refer to the chip isn't in normal 2^N bytes page-size
484 * mode.
485 * The lower case refer to the chip is in normal 2^N bytes page-size
486 * mode.
487 *
488 * These newer chips also support 128-byte security registers (with
489 * 64 bytes one-time-programmable) and software write-protection.
490 */
491 { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS},
492 { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS},
493
494 { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS},
495 { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS},
496
497 { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS},
498 { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS},
499
500 { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS},
501 { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS},
502
503 { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS},
504 { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS},
505
506 { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */
507
508 { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS},
509 { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS},
510
511 { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS},
512 { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
513
514 { "AT45DB641E", 0x1f28000100ULL, 32768, 264, 9, SUP_EXTID | SUP_POW2PS},
515 { "at45db641e", 0x1f28000100ULL, 32768, 256, 8, SUP_EXTID | SUP_POW2PS | IS_POW2PS},
516 };
517
jedec_lookup(struct spi_slave * spi,u64 jedec,bool use_extid)518 static struct data_flash_info *jedec_lookup(struct spi_slave *spi,
519 u64 jedec, bool use_extid)
520
521 {
522 struct data_flash_info *info;
523 int status;
524
525 for (info = dataflash_data;
526 info < dataflash_data + ARRAY_SIZE(dataflash_data);
527 info++) {
528 if (use_extid && !(info->flags & SUP_EXTID))
529 continue;
530
531 if (info->jedec_id == jedec) {
532 if (info->flags & SUP_POW2PS) {
533 status = dataflash_status(spi);
534 if (status < 0) {
535 debug("dataflash: status error %d\n",
536 status);
537 return ERR_PTR(status);
538 }
539 if (status & 0x1) {
540 if (info->flags & IS_POW2PS)
541 return info;
542 } else {
543 if (!(info->flags & IS_POW2PS))
544 return info;
545 }
546 } else {
547 return info;
548 }
549 }
550 }
551
552 return ERR_PTR(-ENODEV);
553 }
554
jedec_probe(struct spi_slave * spi)555 static struct data_flash_info *jedec_probe(struct spi_slave *spi)
556 {
557 int tmp;
558 uint64_t jedec;
559 uint8_t id[sizeof(jedec)] = {0};
560 const unsigned int id_size = 5;
561 struct data_flash_info *info;
562 u8 opcode = CMD_READ_ID;
563
564 /*
565 * JEDEC also defines an optional "extended device information"
566 * string for after vendor-specific data, after the three bytes
567 * we use here. Supporting some chips might require using it.
568 *
569 * If the vendor ID isn't Atmel's (0x1f), assume this call failed.
570 * That's not an error; only rev C and newer chips handle it, and
571 * only Atmel sells these chips.
572 */
573 tmp = spi_write_then_read(spi, &opcode, 1, NULL, id, id_size);
574 if (tmp < 0) {
575 printf("dataflash: error %d reading JEDEC ID\n", tmp);
576 return ERR_PTR(tmp);
577 }
578
579 if (id[0] != 0x1f)
580 return NULL;
581
582 jedec = be64_to_cpup((__be64 *)id);
583
584 /*
585 * First, try to match device using extended device
586 * information
587 */
588 info = jedec_lookup(spi, jedec >> DATAFLASH_SHIFT_EXTID, true);
589 if (!IS_ERR(info))
590 return info;
591 /*
592 * If that fails, make another pass using regular ID
593 * information
594 */
595 info = jedec_lookup(spi, jedec >> DATAFLASH_SHIFT_ID, false);
596 if (!IS_ERR(info))
597 return info;
598 /*
599 * Treat other chips as errors ... we won't know the right page
600 * size (it might be binary) even when we can tell which density
601 * class is involved (legacy chip id scheme).
602 */
603 printf("dataflash: JEDEC id 0x%016llx not handled\n", jedec);
604 return ERR_PTR(-ENODEV);
605 }
606
607 /*
608 * Detect and initialize DataFlash device, using JEDEC IDs on newer chips
609 * or else the ID code embedded in the status bits:
610 *
611 * Device Density ID code #Pages PageSize Offset
612 * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
613 * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9
614 * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
615 * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
616 * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
617 * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
618 * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11
619 * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
620 */
spi_dataflash_probe(struct udevice * dev)621 static int spi_dataflash_probe(struct udevice *dev)
622 {
623 struct spi_slave *spi = dev_get_parent_priv(dev);
624 struct spi_flash *spi_flash;
625 struct data_flash_info *info;
626 int status;
627
628 spi_flash = dev_get_uclass_priv(dev);
629 spi_flash->spi = spi;
630 spi_flash->dev = dev;
631
632 status = spi_claim_bus(spi);
633 if (status)
634 return status;
635
636 /*
637 * Try to detect dataflash by JEDEC ID.
638 * If it succeeds we know we have either a C or D part.
639 * D will support power of 2 pagesize option.
640 * Both support the security register, though with different
641 * write procedures.
642 */
643 info = jedec_probe(spi);
644 if (IS_ERR(info))
645 goto err_jedec_probe;
646 if (info != NULL) {
647 status = add_dataflash(dev, info->name, info->nr_pages,
648 info->pagesize, info->pageoffset,
649 (info->flags & SUP_POW2PS) ? 'd' : 'c');
650 if (status < 0)
651 goto err_status;
652 else
653 return status;
654 }
655
656 /*
657 * Older chips support only legacy commands, identifing
658 * capacity using bits in the status byte.
659 */
660 status = dataflash_status(spi);
661 if (status <= 0 || status == 0xff) {
662 printf("dataflash: read status error %d\n", status);
663 if (status == 0 || status == 0xff)
664 status = -ENODEV;
665 goto err_jedec_probe;
666 }
667
668 /*
669 * if there's a device there, assume it's dataflash.
670 * board setup should have set spi->max_speed_max to
671 * match f(car) for continuous reads, mode 0 or 3.
672 */
673 switch (status & 0x3c) {
674 case 0x0c: /* 0 0 1 1 x x */
675 status = add_dataflash(dev, "AT45DB011B", 512, 264, 9, 0);
676 break;
677 case 0x14: /* 0 1 0 1 x x */
678 status = add_dataflash(dev, "AT45DB021B", 1024, 264, 9, 0);
679 break;
680 case 0x1c: /* 0 1 1 1 x x */
681 status = add_dataflash(dev, "AT45DB041x", 2048, 264, 9, 0);
682 break;
683 case 0x24: /* 1 0 0 1 x x */
684 status = add_dataflash(dev, "AT45DB081B", 4096, 264, 9, 0);
685 break;
686 case 0x2c: /* 1 0 1 1 x x */
687 status = add_dataflash(dev, "AT45DB161x", 4096, 528, 10, 0);
688 break;
689 case 0x34: /* 1 1 0 1 x x */
690 status = add_dataflash(dev, "AT45DB321x", 8192, 528, 10, 0);
691 break;
692 case 0x38: /* 1 1 1 x x x */
693 case 0x3c:
694 status = add_dataflash(dev, "AT45DB642x", 8192, 1056, 11, 0);
695 break;
696 /* obsolete AT45DB1282 not (yet?) supported */
697 default:
698 printf("dataflash: unsupported device (%x)\n", status & 0x3c);
699 status = -ENODEV;
700 goto err_status;
701 }
702
703 return status;
704
705 err_status:
706 spi_free_slave(spi);
707 err_jedec_probe:
708 spi_release_bus(spi);
709 return status;
710 }
711
712 static const struct dm_spi_flash_ops spi_dataflash_ops = {
713 .read = spi_dataflash_read,
714 .write = spi_dataflash_write,
715 .erase = spi_dataflash_erase,
716 };
717
718 static const struct udevice_id spi_dataflash_ids[] = {
719 { .compatible = "atmel,at45", },
720 { .compatible = "atmel,dataflash", },
721 { }
722 };
723
724 U_BOOT_DRIVER(spi_dataflash) = {
725 .name = "spi_dataflash",
726 .id = UCLASS_SPI_FLASH,
727 .of_match = spi_dataflash_ids,
728 .probe = spi_dataflash_probe,
729 .priv_auto = sizeof(struct dataflash),
730 .ops = &spi_dataflash_ops,
731 };
732