1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * 4 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 5 * Copyright (C) 2016 Jagan Teki <jagan@openedev.com> 6 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 7 */ 8 9 #include <common.h> 10 #include <spi.h> 11 #include <spi_flash.h> 12 13 #include "sf_internal.h" 14 15 /* Exclude chip names for SPL to save space */ 16 #if !CONFIG_IS_ENABLED(SPI_FLASH_TINY) 17 #define INFO_NAME(_name) .name = _name, 18 #else 19 #define INFO_NAME(_name) 20 #endif 21 22 /* Used when the "_ext_id" is two bytes at most */ 23 #define INFO(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 24 INFO_NAME(_name) \ 25 .id = { \ 26 ((_jedec_id) >> 16) & 0xff, \ 27 ((_jedec_id) >> 8) & 0xff, \ 28 (_jedec_id) & 0xff, \ 29 ((_ext_id) >> 8) & 0xff, \ 30 (_ext_id) & 0xff, \ 31 }, \ 32 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ 33 .sector_size = (_sector_size), \ 34 .n_sectors = (_n_sectors), \ 35 .page_size = 256, \ 36 .flags = (_flags), 37 38 #define INFO6(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 39 INFO_NAME(_name) \ 40 .id = { \ 41 ((_jedec_id) >> 16) & 0xff, \ 42 ((_jedec_id) >> 8) & 0xff, \ 43 (_jedec_id) & 0xff, \ 44 ((_ext_id) >> 16) & 0xff, \ 45 ((_ext_id) >> 8) & 0xff, \ 46 (_ext_id) & 0xff, \ 47 }, \ 48 .id_len = 6, \ 49 .sector_size = (_sector_size), \ 50 .n_sectors = (_n_sectors), \ 51 .page_size = 256, \ 52 .flags = (_flags), 53 54 /* NOTE: double check command sets and memory organization when you add 55 * more nor chips. This current list focusses on newer chips, which 56 * have been converging on command sets which including JEDEC ID. 57 * 58 * All newly added entries should describe *hardware* and should use SECT_4K 59 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage 60 * scenarios excluding small sectors there is config option that can be 61 * disabled: CONFIG_SPI_FLASH_USE_4K_SECTORS. 62 * For historical (and compatibility) reasons (before we got above config) some 63 * old entries may be missing 4K flag. 64 */ 65 const struct flash_info spi_nor_ids[] = { 66 #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ 67 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 68 { INFO("at26df321", 0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, 69 { INFO("at25df321a", 0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, 70 71 { INFO("at45db011d", 0x1f2200, 0, 64 * 1024, 4, SECT_4K) }, 72 { INFO("at45db021d", 0x1f2300, 0, 64 * 1024, 8, SECT_4K) }, 73 { INFO("at45db041d", 0x1f2400, 0, 64 * 1024, 8, SECT_4K) }, 74 { INFO("at45db081d", 0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, 75 { INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) }, 76 { INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) }, 77 { INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) }, 78 { INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) }, 79 { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, 80 #endif 81 #ifdef CONFIG_SPI_FLASH_EON /* EON */ 82 /* EON -- en25xxx */ 83 { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, 84 { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, 85 { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) }, 86 { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) }, 87 { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, 88 #endif 89 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ 90 /* GigaDevice */ 91 { 92 INFO("gd25q16", 0xc84015, 0, 64 * 1024, 32, 93 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 94 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 95 }, 96 { 97 INFO("gd25q32", 0xc84016, 0, 64 * 1024, 64, 98 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 99 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 100 }, 101 { 102 INFO("gd25lq32", 0xc86016, 0, 64 * 1024, 64, 103 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 104 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 105 }, 106 { 107 INFO("gd25q64", 0xc84017, 0, 64 * 1024, 128, 108 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 109 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 110 }, 111 { 112 INFO("gd25lq64c", 0xc86017, 0, 64 * 1024, 128, 113 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 114 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 115 }, 116 { 117 INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256, 118 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 119 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 120 }, 121 /* adding these 3V QSPI flash parts */ 122 {INFO("gd25b256", 0xc84019, 0, 64 * 1024, 512, SECT_4K | 123 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES) }, 124 {INFO("gd25b512", 0xc8471A, 0, 64 * 1024, 1024, SECT_4K | 125 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 126 {INFO("gd55b01g", 0xc8471B, 0, 64 * 1024, 2048, SECT_4K | 127 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 128 {INFO("gd55b02g", 0xc8471C, 0, 64 * 1024, 4096, SECT_4K | 129 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 130 {INFO("gd25f64", 0xc84317, 0, 64 * 1024, 128, SECT_4K | 131 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, 132 {INFO("gd25f128", 0xc84318, 0, 64 * 1024, 256, SECT_4K | 133 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, 134 {INFO("gd25f256", 0xc84319, 0, 64 * 1024, 512, SECT_4K | 135 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 136 {INFO("gd55f512", 0xc8431A, 0, 64 * 1024, 1024, SECT_4K | 137 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 138 {INFO("gd25t512", 0xc8461A, 0, 64 * 1024, 1024, SECT_4K | 139 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 140 {INFO("gd55t01g", 0xc8461B, 0, 64 * 1024, 2048, SECT_4K | 141 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 142 {INFO("gd55t02g", 0xc8461C, 0, 64 * 1024, 4096, SECT_4K | 143 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 144 /* adding these 3V OSPI flash parts */ 145 {INFO("gd25x512", 0xc8481A, 0, 64 * 1024, 1024, SECT_4K | 146 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, 147 {INFO("gd55x01g", 0xc8481B, 0, 64 * 1024, 2048, SECT_4K | 148 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, 149 {INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K | 150 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, 151 { 152 INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, 153 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 154 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 155 }, 156 { 157 INFO("gd25lq256d", 0xc86019, 0, 64 * 1024, 512, 158 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 159 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 160 }, 161 /* adding these 1.8V QSPI flash parts */ 162 {INFO("gd25lb256", 0xc86719, 0, 64 * 1024, 512, SECT_4K | 163 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 164 {INFO("gd25lb512", 0xc8671A, 0, 64 * 1024, 1024, SECT_4K | 165 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 166 {INFO("gd55lb01g", 0xc8671B, 0, 64 * 1024, 2048, SECT_4K | 167 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 168 {INFO("gd55lb02g", 0xc8671C, 0, 64 * 1024, 4096, SECT_4K | 169 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 170 {INFO("gd25lf80", 0xc86314, 0, 64 * 1024, 16, SECT_4K | 171 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, 172 {INFO("gd25lf16", 0xc86315, 0, 64 * 1024, 32, SECT_4K | 173 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, 174 {INFO("gd25lf32", 0xc86316, 0, 64 * 1024, 64, SECT_4K | 175 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, 176 {INFO("gd25lf64", 0xc86317, 0, 64 * 1024, 128, SECT_4K | 177 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, 178 {INFO("gd25lf128", 0xc86318, 0, 64 * 1024, 256, SECT_4K | 179 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, 180 {INFO("gd25lf255", 0xc86319, 0, 64 * 1024, 512, SECT_4K | 181 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 182 {INFO("gd25lf511", 0xc8631A, 0, 64 * 1024, 1024, SECT_4K | 183 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 184 {INFO("gd25lt256", 0xc86619, 0, 64 * 1024, 512, SECT_4K | 185 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 186 {INFO("gd25lt512", 0xc8661A, 0, 64 * 1024, 1024, SECT_4K | 187 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 188 {INFO("gd55lt01g", 0xc8661B, 0, 64 * 1024, 2048, SECT_4K | 189 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 190 {INFO("gd55lt02g", 0xc8661C, 0, 64 * 1024, 4096, SECT_4K | 191 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, 192 { 193 INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, 194 SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) 195 }, 196 /* adding these 1.8V OSPI flash parts */ 197 {INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024, SECT_4K | 198 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, 199 {INFO("gd55lx01g", 0xc8681B, 0, 64 * 1024, 2048, SECT_4K | 200 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, 201 {INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096, SECT_4K | 202 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, 203 #endif 204 #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ 205 /* ISSI */ 206 { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8, 207 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 208 { INFO("is25lp008", 0x9d6014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, 209 { INFO("is25lp016", 0x9d6015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, 210 { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) }, 211 { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) }, 212 { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256, 213 SECT_4K | SPI_NOR_DUAL_READ) }, 214 { INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512, 215 SECT_4K | SPI_NOR_DUAL_READ) }, 216 { INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024, 217 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 218 { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048, 219 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 220 { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, 221 { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, 222 { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64, 223 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 224 { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128, 225 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 226 { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256, 227 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 228 { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512, 229 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 230 SPI_NOR_4B_OPCODES) }, 231 { INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024, 232 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 233 { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048, 234 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 235 { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256, 236 SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, 237 #endif 238 #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ 239 /* Macronix */ 240 { INFO("mx25l2005a", 0xc22012, 0, 64 * 1024, 4, SECT_4K) }, 241 { INFO("mx25l4005a", 0xc22013, 0, 64 * 1024, 8, SECT_4K) }, 242 { INFO("mx25l8005", 0xc22014, 0, 64 * 1024, 16, 0) }, 243 { INFO("mx25l1606e", 0xc22015, 0, 64 * 1024, 32, SECT_4K) }, 244 { INFO("mx25l3205d", 0xc22016, 0, 64 * 1024, 64, SECT_4K) }, 245 { INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) }, 246 { INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) }, 247 { INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) }, 248 { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) }, 249 { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) }, 250 { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) }, 251 { INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) }, 252 { INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | 253 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 254 { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, 255 { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 256 { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) }, 257 { INFO("mx25v8035f", 0xc22314, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 258 { INFO("mx25r1635f", 0xc22815, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 259 { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) }, 260 { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 261 { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 262 { INFO("mx25u51245f", 0xc2953a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 263 { INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 264 { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 265 { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 266 { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 267 { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, 268 { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, 269 { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 270 { INFO("mx66lm1g45g", 0xc2853b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 271 { INFO("mx25lm51245g", 0xc2853a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 272 { INFO("mx25lw51245g", 0xc2863a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 273 { INFO("mx25lm25645g", 0xc28539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 274 { INFO("mx66uw2g345g", 0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 275 { INFO("mx66um1g45g", 0xc2803b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 276 { INFO("mx66uw1g45g", 0xc2813b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 277 { INFO("mx25uw51245g", 0xc2813a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 278 { INFO("mx25uw51345g", 0xc2843a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 279 { INFO("mx25um25645g", 0xc28039, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 280 { INFO("mx25uw25645g", 0xc28139, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 281 { INFO("mx25um25345g", 0xc28339, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 282 { INFO("mx25uw25345g", 0xc28439, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 283 { INFO("mx25uw12845g", 0xc28138, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 284 { INFO("mx25uw12345g", 0xc28438, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 285 { INFO("mx25uw6445g", 0xc28137, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 286 { INFO("mx25uw6345g", 0xc28437, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, 287 #endif 288 289 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 290 /* Micron */ 291 { INFO("n25q016a", 0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, 292 { INFO("n25q032", 0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 293 { INFO("n25q032a", 0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 294 { INFO("n25q064", 0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 295 { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 296 { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 297 { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 298 { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, 299 { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) }, 300 { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, 301 { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) }, 302 { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, 303 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | 304 USE_FSR) }, 305 { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 306 { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 307 { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 308 { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 309 { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 310 { INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 311 { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 312 { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, 313 #ifdef CONFIG_SPI_FLASH_MT35XU 314 { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, 315 { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, 316 #endif /* CONFIG_SPI_FLASH_MT35XU */ 317 { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, 318 { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, 319 #endif 320 #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ 321 /* Spansion/Cypress -- single (large) sector size only, at least 322 * for the chips listed here (without boot sectors). 323 */ 324 { INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 325 { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 326 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 327 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 328 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 329 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 330 { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 331 { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 332 { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 333 { INFO("s70fs01gs_256k", 0x010221, 0x4d00, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 334 { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) }, 335 { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) }, 336 { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 337 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 338 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 339 { INFO("s25sl008a", 0x010213, 0, 64 * 1024, 16, 0) }, 340 { INFO("s25sl016a", 0x010214, 0, 64 * 1024, 32, 0) }, 341 { INFO("s25sl032a", 0x010215, 0, 64 * 1024, 64, 0) }, 342 { INFO("s25sl064a", 0x010216, 0, 64 * 1024, 128, 0) }, 343 { INFO("s25fl116k", 0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 344 { INFO("s25fl164k", 0x014017, 0, 64 * 1024, 128, SECT_4K) }, 345 { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, 346 { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 347 { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 348 { INFO("s25fl256l", 0x016019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 349 { INFO6("s25hl512t", 0x342a1a, 0x0f0390, 256 * 1024, 256, 350 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | 351 USE_CLSR) }, 352 { INFO6("s25hl01gt", 0x342a1b, 0x0f0390, 256 * 1024, 512, 353 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | 354 USE_CLSR) }, 355 { INFO6("s25hl02gt", 0x342a1c, 0x0f0090, 256 * 1024, 1024, 356 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 357 { INFO6("s25hs512t", 0x342b1a, 0x0f0390, 256 * 1024, 256, 358 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | 359 USE_CLSR) }, 360 { INFO6("s25hs01gt", 0x342b1b, 0x0f0390, 256 * 1024, 512, 361 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | 362 USE_CLSR) }, 363 { INFO6("s25hs02gt", 0x342b1c, 0x0f0090, 256 * 1024, 1024, 364 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 365 { INFO6("s25fs256t", 0x342b19, 0x0f0890, 128 * 1024, 256, 366 SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 367 #ifdef CONFIG_SPI_FLASH_S28HX_T 368 { INFO("s28hl512t", 0x345a1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) }, 369 { INFO("s28hl01gt", 0x345a1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) }, 370 { INFO("s28hs512t", 0x345b1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) }, 371 { INFO("s28hs01gt", 0x345b1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) }, 372 #endif 373 #endif 374 #ifdef CONFIG_SPI_FLASH_SST /* SST */ 375 /* SST -- large erase sizes are "overlays", "sectors" are 4K */ 376 { INFO("sst25vf040b", 0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 377 { INFO("sst25vf080b", 0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 378 { INFO("sst25vf016b", 0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, 379 { INFO("sst25vf032b", 0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, 380 { INFO("sst25vf064c", 0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, 381 { INFO("sst25wf512", 0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, 382 { INFO("sst25wf010", 0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, 383 { INFO("sst25wf020", 0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, 384 { INFO("sst25wf020a", 0x621612, 0, 64 * 1024, 4, SECT_4K) }, 385 { INFO("sst25wf040b", 0x621613, 0, 64 * 1024, 8, SECT_4K) }, 386 { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 387 { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 388 { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 389 { INFO("sst26wf016b", 0xbf2641, 0, 64 * 1024, 32, SECT_4K) }, 390 { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, 391 { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, 392 { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, 393 #endif 394 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 395 /* STMicroelectronics -- newer production may have feature updates */ 396 { INFO("m25p10", 0x202011, 0, 32 * 1024, 4, 0) }, 397 { INFO("m25p20", 0x202012, 0, 64 * 1024, 4, 0) }, 398 { INFO("m25p40", 0x202013, 0, 64 * 1024, 8, 0) }, 399 { INFO("m25p80", 0x202014, 0, 64 * 1024, 16, 0) }, 400 { INFO("m25p16", 0x202015, 0, 64 * 1024, 32, 0) }, 401 { INFO("m25p32", 0x202016, 0, 64 * 1024, 64, 0) }, 402 { INFO("m25p64", 0x202017, 0, 64 * 1024, 128, 0) }, 403 { INFO("m25p128", 0x202018, 0, 256 * 1024, 64, 0) }, 404 { INFO("m25pe16", 0x208015, 0, 64 * 1024, 32, SECT_4K) }, 405 { INFO("m25px16", 0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 406 { INFO("m25px64", 0x207117, 0, 64 * 1024, 128, 0) }, 407 #endif 408 #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ 409 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 410 { INFO("w25p80", 0xef2014, 0x0, 64 * 1024, 16, 0) }, 411 { INFO("w25p16", 0xef2015, 0x0, 64 * 1024, 32, 0) }, 412 { INFO("w25p32", 0xef2016, 0x0, 64 * 1024, 64, 0) }, 413 { INFO("w25x05", 0xef3010, 0, 64 * 1024, 1, SECT_4K) }, 414 { INFO("w25x40", 0xef3013, 0, 64 * 1024, 8, SECT_4K) }, 415 { INFO("w25x16", 0xef3015, 0, 64 * 1024, 32, SECT_4K) }, 416 { 417 INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, 418 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 419 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 420 }, 421 { INFO("w25x32", 0xef3016, 0, 64 * 1024, 64, SECT_4K) }, 422 { INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) }, 423 { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) }, 424 { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) }, 425 { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 426 { 427 INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, 428 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 429 }, 430 { 431 INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64, 432 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 433 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 434 }, 435 { 436 INFO("w25q16jv", 0xef7015, 0, 64 * 1024, 32, 437 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) 438 }, 439 { 440 INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64, 441 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 442 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 443 }, 444 { 445 INFO("w25q32jwm", 0xef8016, 0, 64 * 1024, 64, 446 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 447 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 448 }, 449 { INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) }, 450 { 451 INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128, 452 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 453 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 454 }, 455 { 456 INFO("w25q64jv", 0xef7017, 0, 64 * 1024, 128, 457 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 458 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 459 }, 460 { 461 INFO("w25q128fw", 0xef6018, 0, 64 * 1024, 256, 462 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 463 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 464 }, 465 { 466 INFO("w25q128jv", 0xef7018, 0, 64 * 1024, 256, 467 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 468 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 469 }, 470 { 471 INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256, 472 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 473 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 474 }, 475 { 476 INFO("w25q256fw", 0xef6019, 0, 64 * 1024, 512, 477 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 478 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 479 }, 480 { 481 INFO("w25q256jw", 0xef7019, 0, 64 * 1024, 512, 482 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 483 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 484 }, 485 { 486 INFO("w25q512jv", 0xef7119, 0, 64 * 1024, 512, 487 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 488 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 489 }, 490 { 491 INFO("w25q512nwq", 0xef6020, 0, 64 * 1024, 1024, 492 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 493 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 494 }, 495 { 496 INFO("w25q512nwm", 0xef8020, 0, 64 * 1024, 1024, 497 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 498 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 499 }, 500 { 501 INFO("w25q512jvq", 0xef4020, 0, 64 * 1024, 1024, 502 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 503 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 504 }, 505 { 506 INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048, 507 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 508 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 509 }, 510 { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, 511 { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 512 { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 513 { INFO("w25q32bv", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 514 { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 515 { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, 516 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 517 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 518 }, 519 { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 520 { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 521 { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 522 { INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 523 #endif 524 #ifdef CONFIG_SPI_FLASH_XMC 525 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ 526 { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 527 { INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 528 { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 529 #endif 530 #ifdef CONFIG_SPI_FLASH_XTX 531 /* XTX Technology (Shenzhen) Limited */ 532 { INFO("xt25f128b", 0x0b4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 533 #endif 534 { }, 535 }; 536