1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2010
4  * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
5  */
6 
7 #ifndef _DW_ETH_H
8 #define _DW_ETH_H
9 
10 #include <asm/cache.h>
11 #include <net.h>
12 
13 #if CONFIG_IS_ENABLED(DM_GPIO)
14 #include <asm-generic/gpio.h>
15 #endif
16 
17 #define CFG_TX_DESCR_NUM	16
18 #define CFG_RX_DESCR_NUM	16
19 #define CFG_ETH_BUFSIZE	2048
20 #define TX_TOTAL_BUFSIZE	(CFG_ETH_BUFSIZE * CFG_TX_DESCR_NUM)
21 #define RX_TOTAL_BUFSIZE	(CFG_ETH_BUFSIZE * CFG_RX_DESCR_NUM)
22 
23 #define CFG_MACRESET_TIMEOUT	(3 * CONFIG_SYS_HZ)
24 #define CFG_MDIO_TIMEOUT	(3 * CONFIG_SYS_HZ)
25 
26 struct eth_mac_regs {
27 	u32 conf;		/* 0x00 */
28 	u32 framefilt;		/* 0x04 */
29 	u32 hashtablehigh;	/* 0x08 */
30 	u32 hashtablelow;	/* 0x0c */
31 	u32 miiaddr;		/* 0x10 */
32 	u32 miidata;		/* 0x14 */
33 	u32 flowcontrol;	/* 0x18 */
34 	u32 vlantag;		/* 0x1c */
35 	u32 version;		/* 0x20 */
36 	u8 reserved_1[20];
37 	u32 intreg;		/* 0x38 */
38 	u32 intmask;		/* 0x3c */
39 	u32 macaddr0hi;		/* 0x40 */
40 	u32 macaddr0lo;		/* 0x44 */
41 };
42 
43 /* MAC configuration register definitions */
44 #define FRAMEBURSTENABLE	(1 << 21)
45 #define MII_PORTSELECT		(1 << 15)
46 #define FES_100			(1 << 14)
47 #define DISABLERXOWN		(1 << 13)
48 #define FULLDPLXMODE		(1 << 11)
49 #define RXENABLE		(1 << 2)
50 #define TXENABLE		(1 << 3)
51 
52 /* MII address register definitions */
53 #define MII_BUSY		(1 << 0)
54 #define MII_WRITE		(1 << 1)
55 #define MII_CLKRANGE_60_100M	(0)
56 #define MII_CLKRANGE_100_150M	(0x4)
57 #define MII_CLKRANGE_20_35M	(0x8)
58 #define MII_CLKRANGE_35_60M	(0xC)
59 #define MII_CLKRANGE_150_250M	(0x10)
60 #define MII_CLKRANGE_250_300M	(0x14)
61 
62 #define MIIADDRSHIFT		(11)
63 #define MIIREGSHIFT		(6)
64 #define MII_REGMSK		(0x1F << 6)
65 #define MII_ADDRMSK		(0x1F << 11)
66 
67 
68 struct eth_dma_regs {
69 	u32 busmode;		/* 0x00 */
70 	u32 txpolldemand;	/* 0x04 */
71 	u32 rxpolldemand;	/* 0x08 */
72 	u32 rxdesclistaddr;	/* 0x0c */
73 	u32 txdesclistaddr;	/* 0x10 */
74 	u32 status;		/* 0x14 */
75 	u32 opmode;		/* 0x18 */
76 	u32 intenable;		/* 0x1c */
77 	u32 reserved1[2];
78 	u32 axibus;		/* 0x28 */
79 	u32 reserved2[7];
80 	u32 currhosttxdesc;	/* 0x48 */
81 	u32 currhostrxdesc;	/* 0x4c */
82 	u32 currhosttxbuffaddr;	/* 0x50 */
83 	u32 currhostrxbuffaddr;	/* 0x54 */
84 };
85 
86 #define DW_DMA_BASE_OFFSET	(0x1000)
87 
88 /* DMA Burst length */
89 #define GMAC_DEFAULT_DMA_PBL	8
90 
91 /* Bus mode register definitions */
92 #define FIXEDBURST		(1 << 16)
93 #define PRIORXTX_41		(3 << 14)
94 #define PRIORXTX_31		(2 << 14)
95 #define PRIORXTX_21		(1 << 14)
96 #define PRIORXTX_11		(0 << 14)
97 #define DMA_PBL			(GMAC_DEFAULT_DMA_PBL << 8)
98 #define RXHIGHPRIO		(1 << 1)
99 #define DMAMAC_SRST		(1 << 0)
100 
101 /* Poll demand definitions */
102 #define POLL_DATA		(0xFFFFFFFF)
103 
104 /* Operation mode definitions */
105 #define STOREFORWARD		(1 << 21)
106 #define FLUSHTXFIFO		(1 << 20)
107 #define TXSTART			(1 << 13)
108 #define TXSECONDFRAME		(1 << 2)
109 #define RXSTART			(1 << 1)
110 
111 /* Descriptior related definitions */
112 #define MAC_MAX_FRAME_SZ	(1600)
113 
114 struct dmamacdescr {
115 	u32 txrx_status;
116 	u32 dmamac_cntl;
117 	u32 dmamac_addr;
118 	u32 dmamac_next;
119 } __aligned(ARCH_DMA_MINALIGN);
120 
121 /*
122  * txrx_status definitions
123  */
124 
125 /* tx status bits definitions */
126 #if defined(CONFIG_DW_ALTDESCRIPTOR)
127 
128 #define DESC_TXSTS_OWNBYDMA		(1 << 31)
129 #define DESC_TXSTS_TXINT		(1 << 30)
130 #define DESC_TXSTS_TXLAST		(1 << 29)
131 #define DESC_TXSTS_TXFIRST		(1 << 28)
132 #define DESC_TXSTS_TXCRCDIS		(1 << 27)
133 
134 #define DESC_TXSTS_TXPADDIS		(1 << 26)
135 #define DESC_TXSTS_TXCHECKINSCTRL	(3 << 22)
136 #define DESC_TXSTS_TXRINGEND		(1 << 21)
137 #define DESC_TXSTS_TXCHAIN		(1 << 20)
138 #define DESC_TXSTS_MSK			(0x1FFFF << 0)
139 
140 #else
141 
142 #define DESC_TXSTS_OWNBYDMA		(1 << 31)
143 #define DESC_TXSTS_MSK			(0x1FFFF << 0)
144 
145 #endif
146 
147 /* rx status bits definitions */
148 #define DESC_RXSTS_OWNBYDMA		(1 << 31)
149 #define DESC_RXSTS_DAFILTERFAIL		(1 << 30)
150 #define DESC_RXSTS_FRMLENMSK		(0x3FFF << 16)
151 #define DESC_RXSTS_FRMLENSHFT		(16)
152 
153 #define DESC_RXSTS_ERROR		(1 << 15)
154 #define DESC_RXSTS_RXTRUNCATED		(1 << 14)
155 #define DESC_RXSTS_SAFILTERFAIL		(1 << 13)
156 #define DESC_RXSTS_RXIPC_GIANTFRAME	(1 << 12)
157 #define DESC_RXSTS_RXDAMAGED		(1 << 11)
158 #define DESC_RXSTS_RXVLANTAG		(1 << 10)
159 #define DESC_RXSTS_RXFIRST		(1 << 9)
160 #define DESC_RXSTS_RXLAST		(1 << 8)
161 #define DESC_RXSTS_RXIPC_GIANT		(1 << 7)
162 #define DESC_RXSTS_RXCOLLISION		(1 << 6)
163 #define DESC_RXSTS_RXFRAMEETHER		(1 << 5)
164 #define DESC_RXSTS_RXWATCHDOG		(1 << 4)
165 #define DESC_RXSTS_RXMIIERROR		(1 << 3)
166 #define DESC_RXSTS_RXDRIBBLING		(1 << 2)
167 #define DESC_RXSTS_RXCRC		(1 << 1)
168 
169 /*
170  * dmamac_cntl definitions
171  */
172 
173 /* tx control bits definitions */
174 #if defined(CONFIG_DW_ALTDESCRIPTOR)
175 
176 #define DESC_TXCTRL_SIZE1MASK		(0x1FFF << 0)
177 #define DESC_TXCTRL_SIZE1SHFT		(0)
178 #define DESC_TXCTRL_SIZE2MASK		(0x1FFF << 16)
179 #define DESC_TXCTRL_SIZE2SHFT		(16)
180 
181 #else
182 
183 #define DESC_TXCTRL_TXINT		(1 << 31)
184 #define DESC_TXCTRL_TXLAST		(1 << 30)
185 #define DESC_TXCTRL_TXFIRST		(1 << 29)
186 #define DESC_TXCTRL_TXCHECKINSCTRL	(3 << 27)
187 #define DESC_TXCTRL_TXCRCDIS		(1 << 26)
188 #define DESC_TXCTRL_TXRINGEND		(1 << 25)
189 #define DESC_TXCTRL_TXCHAIN		(1 << 24)
190 
191 #define DESC_TXCTRL_SIZE1MASK		(0x7FF << 0)
192 #define DESC_TXCTRL_SIZE1SHFT		(0)
193 #define DESC_TXCTRL_SIZE2MASK		(0x7FF << 11)
194 #define DESC_TXCTRL_SIZE2SHFT		(11)
195 
196 #endif
197 
198 /* rx control bits definitions */
199 #if defined(CONFIG_DW_ALTDESCRIPTOR)
200 
201 #define DESC_RXCTRL_RXINTDIS		(1 << 31)
202 #define DESC_RXCTRL_RXRINGEND		(1 << 15)
203 #define DESC_RXCTRL_RXCHAIN		(1 << 14)
204 
205 #define DESC_RXCTRL_SIZE1MASK		(0x1FFF << 0)
206 #define DESC_RXCTRL_SIZE1SHFT		(0)
207 #define DESC_RXCTRL_SIZE2MASK		(0x1FFF << 16)
208 #define DESC_RXCTRL_SIZE2SHFT		(16)
209 
210 #else
211 
212 #define DESC_RXCTRL_RXINTDIS		(1 << 31)
213 #define DESC_RXCTRL_RXRINGEND		(1 << 25)
214 #define DESC_RXCTRL_RXCHAIN		(1 << 24)
215 
216 #define DESC_RXCTRL_SIZE1MASK		(0x7FF << 0)
217 #define DESC_RXCTRL_SIZE1SHFT		(0)
218 #define DESC_RXCTRL_SIZE2MASK		(0x7FF << 11)
219 #define DESC_RXCTRL_SIZE2SHFT		(11)
220 
221 #endif
222 
223 struct dw_eth_dev {
224 	struct dmamacdescr tx_mac_descrtable[CFG_TX_DESCR_NUM];
225 	struct dmamacdescr rx_mac_descrtable[CFG_RX_DESCR_NUM];
226 	char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
227 	char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
228 
229 	u32 interface;
230 	u32 max_speed;
231 	u32 tx_currdescnum;
232 	u32 rx_currdescnum;
233 
234 	struct eth_mac_regs *mac_regs_p;
235 	struct eth_dma_regs *dma_regs_p;
236 #if CONFIG_IS_ENABLED(DM_GPIO)
237 	struct gpio_desc reset_gpio;
238 #endif
239 #ifdef CONFIG_CLK
240 	struct clk *clocks;	/* clock list */
241 	int clock_count;	/* number of clock in clock list */
242 #endif
243 
244 	struct phy_device *phydev;
245 	struct mii_dev *bus;
246 };
247 
248 int designware_eth_of_to_plat(struct udevice *dev);
249 int designware_eth_probe(struct udevice *dev);
250 extern const struct eth_ops designware_eth_ops;
251 
252 struct dw_eth_pdata {
253 	struct eth_pdata eth_pdata;
254 	u32 reset_delays[3];
255 };
256 
257 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr);
258 int designware_eth_enable(struct dw_eth_dev *priv);
259 int designware_eth_send(struct udevice *dev, void *packet, int length);
260 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp);
261 int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
262 				   int length);
263 void designware_eth_stop(struct udevice *dev);
264 int designware_eth_write_hwaddr(struct udevice *dev);
265 
266 #endif
267