1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2016, NVIDIA CORPORATION.
4 *
5 * Portions based on U-Boot's rtl8169.c.
6 */
7
8 /*
9 * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
10 * Service) IP block. The IP supports multiple options for bus type, clocking/
11 * reset structure, and feature list.
12 *
13 * The driver is written such that generic core logic is kept separate from
14 * configuration-specific logic. Code that interacts with configuration-
15 * specific resources is split out into separate functions to avoid polluting
16 * common code. If/when this driver is enhanced to support multiple
17 * configurations, the core code should be adapted to call all configuration-
18 * specific functions through function pointers, with the definition of those
19 * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
20 * field.
21 *
22 * The following configurations are currently supported:
23 * tegra186:
24 * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
25 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
26 * supports a single RGMII PHY. This configuration also has SW control over
27 * all clock and reset signals to the HW block.
28 */
29
30 #define LOG_CATEGORY UCLASS_ETH
31
32 #include <common.h>
33 #include <clk.h>
34 #include <cpu_func.h>
35 #include <dm.h>
36 #include <errno.h>
37 #include <eth_phy.h>
38 #include <log.h>
39 #include <malloc.h>
40 #include <memalign.h>
41 #include <miiphy.h>
42 #include <net.h>
43 #include <netdev.h>
44 #include <phy.h>
45 #include <reset.h>
46 #include <wait_bit.h>
47 #include <asm/cache.h>
48 #include <asm/gpio.h>
49 #include <asm/io.h>
50 #ifdef CONFIG_ARCH_IMX8M
51 #include <asm/arch/clock.h>
52 #include <asm/mach-imx/sys_proto.h>
53 #endif
54 #include <linux/delay.h>
55
56 #include "dwc_eth_qos.h"
57
58 /*
59 * TX and RX descriptors are 16 bytes. This causes problems with the cache
60 * maintenance on CPUs where the cache-line size exceeds the size of these
61 * descriptors. What will happen is that when the driver receives a packet
62 * it will be immediately requeued for the hardware to reuse. The CPU will
63 * therefore need to flush the cache-line containing the descriptor, which
64 * will cause all other descriptors in the same cache-line to be flushed
65 * along with it. If one of those descriptors had been written to by the
66 * device those changes (and the associated packet) will be lost.
67 *
68 * To work around this, we make use of non-cached memory if available. If
69 * descriptors are mapped uncached there's no need to manually flush them
70 * or invalidate them.
71 *
72 * Note that this only applies to descriptors. The packet data buffers do
73 * not have the same constraints since they are 1536 bytes large, so they
74 * are unlikely to share cache-lines.
75 */
eqos_alloc_descs(struct eqos_priv * eqos,unsigned int num)76 static void *eqos_alloc_descs(struct eqos_priv *eqos, unsigned int num)
77 {
78 return memalign(ARCH_DMA_MINALIGN, num * eqos->desc_size);
79 }
80
eqos_free_descs(void * descs)81 static void eqos_free_descs(void *descs)
82 {
83 free(descs);
84 }
85
eqos_get_desc(struct eqos_priv * eqos,unsigned int num,bool rx)86 static struct eqos_desc *eqos_get_desc(struct eqos_priv *eqos,
87 unsigned int num, bool rx)
88 {
89 return (rx ? eqos->rx_descs : eqos->tx_descs) +
90 (num * eqos->desc_size);
91 }
92
eqos_inval_desc_generic(void * desc)93 void eqos_inval_desc_generic(void *desc)
94 {
95 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
96 unsigned long end = ALIGN(start + sizeof(struct eqos_desc),
97 ARCH_DMA_MINALIGN);
98
99 invalidate_dcache_range(start, end);
100 }
101
eqos_flush_desc_generic(void * desc)102 void eqos_flush_desc_generic(void *desc)
103 {
104 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
105 unsigned long end = ALIGN(start + sizeof(struct eqos_desc),
106 ARCH_DMA_MINALIGN);
107
108 flush_dcache_range(start, end);
109 }
110
eqos_inval_buffer_tegra186(void * buf,size_t size)111 static void eqos_inval_buffer_tegra186(void *buf, size_t size)
112 {
113 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
114 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
115
116 invalidate_dcache_range(start, end);
117 }
118
eqos_inval_buffer_generic(void * buf,size_t size)119 void eqos_inval_buffer_generic(void *buf, size_t size)
120 {
121 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
122 unsigned long end = roundup((unsigned long)buf + size,
123 ARCH_DMA_MINALIGN);
124
125 invalidate_dcache_range(start, end);
126 }
127
eqos_flush_buffer_tegra186(void * buf,size_t size)128 static void eqos_flush_buffer_tegra186(void *buf, size_t size)
129 {
130 flush_cache((unsigned long)buf, size);
131 }
132
eqos_flush_buffer_generic(void * buf,size_t size)133 void eqos_flush_buffer_generic(void *buf, size_t size)
134 {
135 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
136 unsigned long end = roundup((unsigned long)buf + size,
137 ARCH_DMA_MINALIGN);
138
139 flush_dcache_range(start, end);
140 }
141
eqos_mdio_wait_idle(struct eqos_priv * eqos)142 static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
143 {
144 return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
145 EQOS_MAC_MDIO_ADDRESS_GB, false,
146 1000000, true);
147 }
148
eqos_mdio_read(struct mii_dev * bus,int mdio_addr,int mdio_devad,int mdio_reg)149 static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
150 int mdio_reg)
151 {
152 struct eqos_priv *eqos = bus->priv;
153 u32 val;
154 int ret;
155
156 debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr,
157 mdio_reg);
158
159 ret = eqos_mdio_wait_idle(eqos);
160 if (ret) {
161 pr_err("MDIO not idle at entry");
162 return ret;
163 }
164
165 val = readl(&eqos->mac_regs->mdio_address);
166 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
167 EQOS_MAC_MDIO_ADDRESS_C45E;
168 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
169 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
170 (eqos->config->config_mac_mdio <<
171 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
172 (EQOS_MAC_MDIO_ADDRESS_GOC_READ <<
173 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
174 EQOS_MAC_MDIO_ADDRESS_GB;
175 writel(val, &eqos->mac_regs->mdio_address);
176
177 udelay(eqos->config->mdio_wait);
178
179 ret = eqos_mdio_wait_idle(eqos);
180 if (ret) {
181 pr_err("MDIO read didn't complete");
182 return ret;
183 }
184
185 val = readl(&eqos->mac_regs->mdio_data);
186 val &= EQOS_MAC_MDIO_DATA_GD_MASK;
187
188 debug("%s: val=%x\n", __func__, val);
189
190 return val;
191 }
192
eqos_mdio_write(struct mii_dev * bus,int mdio_addr,int mdio_devad,int mdio_reg,u16 mdio_val)193 static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
194 int mdio_reg, u16 mdio_val)
195 {
196 struct eqos_priv *eqos = bus->priv;
197 u32 val;
198 int ret;
199
200 debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev,
201 mdio_addr, mdio_reg, mdio_val);
202
203 ret = eqos_mdio_wait_idle(eqos);
204 if (ret) {
205 pr_err("MDIO not idle at entry");
206 return ret;
207 }
208
209 writel(mdio_val, &eqos->mac_regs->mdio_data);
210
211 val = readl(&eqos->mac_regs->mdio_address);
212 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
213 EQOS_MAC_MDIO_ADDRESS_C45E;
214 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
215 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
216 (eqos->config->config_mac_mdio <<
217 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
218 (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE <<
219 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
220 EQOS_MAC_MDIO_ADDRESS_GB;
221 writel(val, &eqos->mac_regs->mdio_address);
222
223 udelay(eqos->config->mdio_wait);
224
225 ret = eqos_mdio_wait_idle(eqos);
226 if (ret) {
227 pr_err("MDIO read didn't complete");
228 return ret;
229 }
230
231 return 0;
232 }
233
eqos_start_clks_tegra186(struct udevice * dev)234 static int eqos_start_clks_tegra186(struct udevice *dev)
235 {
236 #ifdef CONFIG_CLK
237 struct eqos_priv *eqos = dev_get_priv(dev);
238 int ret;
239
240 debug("%s(dev=%p):\n", __func__, dev);
241
242 ret = clk_enable(&eqos->clk_slave_bus);
243 if (ret < 0) {
244 pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
245 goto err;
246 }
247
248 ret = clk_enable(&eqos->clk_master_bus);
249 if (ret < 0) {
250 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
251 goto err_disable_clk_slave_bus;
252 }
253
254 ret = clk_enable(&eqos->clk_rx);
255 if (ret < 0) {
256 pr_err("clk_enable(clk_rx) failed: %d", ret);
257 goto err_disable_clk_master_bus;
258 }
259
260 ret = clk_enable(&eqos->clk_ptp_ref);
261 if (ret < 0) {
262 pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
263 goto err_disable_clk_rx;
264 }
265
266 ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
267 if (ret < 0) {
268 pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret);
269 goto err_disable_clk_ptp_ref;
270 }
271
272 ret = clk_enable(&eqos->clk_tx);
273 if (ret < 0) {
274 pr_err("clk_enable(clk_tx) failed: %d", ret);
275 goto err_disable_clk_ptp_ref;
276 }
277 #endif
278
279 debug("%s: OK\n", __func__);
280 return 0;
281
282 #ifdef CONFIG_CLK
283 err_disable_clk_ptp_ref:
284 clk_disable(&eqos->clk_ptp_ref);
285 err_disable_clk_rx:
286 clk_disable(&eqos->clk_rx);
287 err_disable_clk_master_bus:
288 clk_disable(&eqos->clk_master_bus);
289 err_disable_clk_slave_bus:
290 clk_disable(&eqos->clk_slave_bus);
291 err:
292 debug("%s: FAILED: %d\n", __func__, ret);
293 return ret;
294 #endif
295 }
296
eqos_start_clks_stm32(struct udevice * dev)297 static int eqos_start_clks_stm32(struct udevice *dev)
298 {
299 #ifdef CONFIG_CLK
300 struct eqos_priv *eqos = dev_get_priv(dev);
301 int ret;
302
303 debug("%s(dev=%p):\n", __func__, dev);
304
305 ret = clk_enable(&eqos->clk_master_bus);
306 if (ret < 0) {
307 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
308 goto err;
309 }
310
311 ret = clk_enable(&eqos->clk_rx);
312 if (ret < 0) {
313 pr_err("clk_enable(clk_rx) failed: %d", ret);
314 goto err_disable_clk_master_bus;
315 }
316
317 ret = clk_enable(&eqos->clk_tx);
318 if (ret < 0) {
319 pr_err("clk_enable(clk_tx) failed: %d", ret);
320 goto err_disable_clk_rx;
321 }
322
323 if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) {
324 ret = clk_enable(&eqos->clk_ck);
325 if (ret < 0) {
326 pr_err("clk_enable(clk_ck) failed: %d", ret);
327 goto err_disable_clk_tx;
328 }
329 eqos->clk_ck_enabled = true;
330 }
331 #endif
332
333 debug("%s: OK\n", __func__);
334 return 0;
335
336 #ifdef CONFIG_CLK
337 err_disable_clk_tx:
338 clk_disable(&eqos->clk_tx);
339 err_disable_clk_rx:
340 clk_disable(&eqos->clk_rx);
341 err_disable_clk_master_bus:
342 clk_disable(&eqos->clk_master_bus);
343 err:
344 debug("%s: FAILED: %d\n", __func__, ret);
345 return ret;
346 #endif
347 }
348
eqos_stop_clks_tegra186(struct udevice * dev)349 static int eqos_stop_clks_tegra186(struct udevice *dev)
350 {
351 #ifdef CONFIG_CLK
352 struct eqos_priv *eqos = dev_get_priv(dev);
353
354 debug("%s(dev=%p):\n", __func__, dev);
355
356 clk_disable(&eqos->clk_tx);
357 clk_disable(&eqos->clk_ptp_ref);
358 clk_disable(&eqos->clk_rx);
359 clk_disable(&eqos->clk_master_bus);
360 clk_disable(&eqos->clk_slave_bus);
361 #endif
362
363 debug("%s: OK\n", __func__);
364 return 0;
365 }
366
eqos_stop_clks_stm32(struct udevice * dev)367 static int eqos_stop_clks_stm32(struct udevice *dev)
368 {
369 #ifdef CONFIG_CLK
370 struct eqos_priv *eqos = dev_get_priv(dev);
371
372 debug("%s(dev=%p):\n", __func__, dev);
373
374 clk_disable(&eqos->clk_tx);
375 clk_disable(&eqos->clk_rx);
376 clk_disable(&eqos->clk_master_bus);
377 #endif
378
379 debug("%s: OK\n", __func__);
380 return 0;
381 }
382
eqos_start_resets_tegra186(struct udevice * dev)383 static int eqos_start_resets_tegra186(struct udevice *dev)
384 {
385 struct eqos_priv *eqos = dev_get_priv(dev);
386 int ret;
387
388 debug("%s(dev=%p):\n", __func__, dev);
389
390 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
391 if (ret < 0) {
392 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
393 return ret;
394 }
395
396 udelay(2);
397
398 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
399 if (ret < 0) {
400 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
401 return ret;
402 }
403
404 ret = reset_assert(&eqos->reset_ctl);
405 if (ret < 0) {
406 pr_err("reset_assert() failed: %d", ret);
407 return ret;
408 }
409
410 udelay(2);
411
412 ret = reset_deassert(&eqos->reset_ctl);
413 if (ret < 0) {
414 pr_err("reset_deassert() failed: %d", ret);
415 return ret;
416 }
417
418 debug("%s: OK\n", __func__);
419 return 0;
420 }
421
eqos_stop_resets_tegra186(struct udevice * dev)422 static int eqos_stop_resets_tegra186(struct udevice *dev)
423 {
424 struct eqos_priv *eqos = dev_get_priv(dev);
425
426 reset_assert(&eqos->reset_ctl);
427 dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
428
429 return 0;
430 }
431
eqos_calibrate_pads_tegra186(struct udevice * dev)432 static int eqos_calibrate_pads_tegra186(struct udevice *dev)
433 {
434 struct eqos_priv *eqos = dev_get_priv(dev);
435 int ret;
436
437 debug("%s(dev=%p):\n", __func__, dev);
438
439 setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
440 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
441
442 udelay(1);
443
444 setbits_le32(&eqos->tegra186_regs->auto_cal_config,
445 EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
446
447 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
448 EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
449 if (ret) {
450 pr_err("calibrate didn't start");
451 goto failed;
452 }
453
454 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
455 EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
456 if (ret) {
457 pr_err("calibrate didn't finish");
458 goto failed;
459 }
460
461 ret = 0;
462
463 failed:
464 clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
465 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
466
467 debug("%s: returns %d\n", __func__, ret);
468
469 return ret;
470 }
471
eqos_disable_calibration_tegra186(struct udevice * dev)472 static int eqos_disable_calibration_tegra186(struct udevice *dev)
473 {
474 struct eqos_priv *eqos = dev_get_priv(dev);
475
476 debug("%s(dev=%p):\n", __func__, dev);
477
478 clrbits_le32(&eqos->tegra186_regs->auto_cal_config,
479 EQOS_AUTO_CAL_CONFIG_ENABLE);
480
481 return 0;
482 }
483
eqos_get_tick_clk_rate_tegra186(struct udevice * dev)484 static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
485 {
486 #ifdef CONFIG_CLK
487 struct eqos_priv *eqos = dev_get_priv(dev);
488
489 return clk_get_rate(&eqos->clk_slave_bus);
490 #else
491 return 0;
492 #endif
493 }
494
eqos_get_tick_clk_rate_stm32(struct udevice * dev)495 static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
496 {
497 #ifdef CONFIG_CLK
498 struct eqos_priv *eqos = dev_get_priv(dev);
499
500 return clk_get_rate(&eqos->clk_master_bus);
501 #else
502 return 0;
503 #endif
504 }
505
eqos_set_full_duplex(struct udevice * dev)506 static int eqos_set_full_duplex(struct udevice *dev)
507 {
508 struct eqos_priv *eqos = dev_get_priv(dev);
509
510 debug("%s(dev=%p):\n", __func__, dev);
511
512 setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
513
514 return 0;
515 }
516
eqos_set_half_duplex(struct udevice * dev)517 static int eqos_set_half_duplex(struct udevice *dev)
518 {
519 struct eqos_priv *eqos = dev_get_priv(dev);
520
521 debug("%s(dev=%p):\n", __func__, dev);
522
523 clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
524
525 /* WAR: Flush TX queue when switching to half-duplex */
526 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
527 EQOS_MTL_TXQ0_OPERATION_MODE_FTQ);
528
529 return 0;
530 }
531
eqos_set_gmii_speed(struct udevice * dev)532 static int eqos_set_gmii_speed(struct udevice *dev)
533 {
534 struct eqos_priv *eqos = dev_get_priv(dev);
535
536 debug("%s(dev=%p):\n", __func__, dev);
537
538 clrbits_le32(&eqos->mac_regs->configuration,
539 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
540
541 return 0;
542 }
543
eqos_set_mii_speed_100(struct udevice * dev)544 static int eqos_set_mii_speed_100(struct udevice *dev)
545 {
546 struct eqos_priv *eqos = dev_get_priv(dev);
547
548 debug("%s(dev=%p):\n", __func__, dev);
549
550 setbits_le32(&eqos->mac_regs->configuration,
551 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
552
553 return 0;
554 }
555
eqos_set_mii_speed_10(struct udevice * dev)556 static int eqos_set_mii_speed_10(struct udevice *dev)
557 {
558 struct eqos_priv *eqos = dev_get_priv(dev);
559
560 debug("%s(dev=%p):\n", __func__, dev);
561
562 clrsetbits_le32(&eqos->mac_regs->configuration,
563 EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS);
564
565 return 0;
566 }
567
eqos_set_tx_clk_speed_tegra186(struct udevice * dev)568 static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
569 {
570 #ifdef CONFIG_CLK
571 struct eqos_priv *eqos = dev_get_priv(dev);
572 ulong rate;
573 int ret;
574
575 debug("%s(dev=%p):\n", __func__, dev);
576
577 switch (eqos->phy->speed) {
578 case SPEED_1000:
579 rate = 125 * 1000 * 1000;
580 break;
581 case SPEED_100:
582 rate = 25 * 1000 * 1000;
583 break;
584 case SPEED_10:
585 rate = 2.5 * 1000 * 1000;
586 break;
587 default:
588 pr_err("invalid speed %d", eqos->phy->speed);
589 return -EINVAL;
590 }
591
592 ret = clk_set_rate(&eqos->clk_tx, rate);
593 if (ret < 0) {
594 pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
595 return ret;
596 }
597 #endif
598
599 return 0;
600 }
601
eqos_adjust_link(struct udevice * dev)602 static int eqos_adjust_link(struct udevice *dev)
603 {
604 struct eqos_priv *eqos = dev_get_priv(dev);
605 int ret;
606 bool en_calibration;
607
608 debug("%s(dev=%p):\n", __func__, dev);
609
610 if (eqos->phy->duplex)
611 ret = eqos_set_full_duplex(dev);
612 else
613 ret = eqos_set_half_duplex(dev);
614 if (ret < 0) {
615 pr_err("eqos_set_*_duplex() failed: %d", ret);
616 return ret;
617 }
618
619 switch (eqos->phy->speed) {
620 case SPEED_1000:
621 en_calibration = true;
622 ret = eqos_set_gmii_speed(dev);
623 break;
624 case SPEED_100:
625 en_calibration = true;
626 ret = eqos_set_mii_speed_100(dev);
627 break;
628 case SPEED_10:
629 en_calibration = false;
630 ret = eqos_set_mii_speed_10(dev);
631 break;
632 default:
633 pr_err("invalid speed %d", eqos->phy->speed);
634 return -EINVAL;
635 }
636 if (ret < 0) {
637 pr_err("eqos_set_*mii_speed*() failed: %d", ret);
638 return ret;
639 }
640
641 if (en_calibration) {
642 ret = eqos->config->ops->eqos_calibrate_pads(dev);
643 if (ret < 0) {
644 pr_err("eqos_calibrate_pads() failed: %d",
645 ret);
646 return ret;
647 }
648 } else {
649 ret = eqos->config->ops->eqos_disable_calibration(dev);
650 if (ret < 0) {
651 pr_err("eqos_disable_calibration() failed: %d",
652 ret);
653 return ret;
654 }
655 }
656 ret = eqos->config->ops->eqos_set_tx_clk_speed(dev);
657 if (ret < 0) {
658 pr_err("eqos_set_tx_clk_speed() failed: %d", ret);
659 return ret;
660 }
661
662 return 0;
663 }
664
eqos_write_hwaddr(struct udevice * dev)665 static int eqos_write_hwaddr(struct udevice *dev)
666 {
667 struct eth_pdata *plat = dev_get_plat(dev);
668 struct eqos_priv *eqos = dev_get_priv(dev);
669 uint32_t val;
670
671 /*
672 * This function may be called before start() or after stop(). At that
673 * time, on at least some configurations of the EQoS HW, all clocks to
674 * the EQoS HW block will be stopped, and a reset signal applied. If
675 * any register access is attempted in this state, bus timeouts or CPU
676 * hangs may occur. This check prevents that.
677 *
678 * A simple solution to this problem would be to not implement
679 * write_hwaddr(), since start() always writes the MAC address into HW
680 * anyway. However, it is desirable to implement write_hwaddr() to
681 * support the case of SW that runs subsequent to U-Boot which expects
682 * the MAC address to already be programmed into the EQoS registers,
683 * which must happen irrespective of whether the U-Boot user (or
684 * scripts) actually made use of the EQoS device, and hence
685 * irrespective of whether start() was ever called.
686 *
687 * Note that this requirement by subsequent SW is not valid for
688 * Tegra186, and is likely not valid for any non-PCI instantiation of
689 * the EQoS HW block. This function is implemented solely as
690 * future-proofing with the expectation the driver will eventually be
691 * ported to some system where the expectation above is true.
692 */
693 if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok)
694 return 0;
695
696 /* Update the MAC address */
697 val = (plat->enetaddr[5] << 8) |
698 (plat->enetaddr[4]);
699 writel(val, &eqos->mac_regs->address0_high);
700 val = (plat->enetaddr[3] << 24) |
701 (plat->enetaddr[2] << 16) |
702 (plat->enetaddr[1] << 8) |
703 (plat->enetaddr[0]);
704 writel(val, &eqos->mac_regs->address0_low);
705
706 return 0;
707 }
708
eqos_read_rom_hwaddr(struct udevice * dev)709 static int eqos_read_rom_hwaddr(struct udevice *dev)
710 {
711 struct eth_pdata *pdata = dev_get_plat(dev);
712 struct eqos_priv *eqos = dev_get_priv(dev);
713 int ret;
714
715 ret = eqos->config->ops->eqos_get_enetaddr(dev);
716 if (ret < 0)
717 return ret;
718
719 return !is_valid_ethaddr(pdata->enetaddr);
720 }
721
eqos_get_phy_addr(struct eqos_priv * priv,struct udevice * dev)722 static int eqos_get_phy_addr(struct eqos_priv *priv, struct udevice *dev)
723 {
724 struct ofnode_phandle_args phandle_args;
725 int reg;
726
727 if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
728 &phandle_args)) {
729 debug("Failed to find phy-handle");
730 return -ENODEV;
731 }
732
733 priv->phy_of_node = phandle_args.node;
734
735 reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
736
737 return reg;
738 }
739
eqos_start(struct udevice * dev)740 static int eqos_start(struct udevice *dev)
741 {
742 struct eqos_priv *eqos = dev_get_priv(dev);
743 int ret, i;
744 ulong rate;
745 u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
746 ulong last_rx_desc;
747 ulong desc_pad;
748
749 debug("%s(dev=%p):\n", __func__, dev);
750
751 eqos->tx_desc_idx = 0;
752 eqos->rx_desc_idx = 0;
753
754 ret = eqos->config->ops->eqos_start_resets(dev);
755 if (ret < 0) {
756 pr_err("eqos_start_resets() failed: %d", ret);
757 goto err;
758 }
759
760 udelay(10);
761
762 eqos->reg_access_ok = true;
763
764 /*
765 * Assert the SWR first, the actually reset the MAC and to latch in
766 * e.g. i.MX8M Plus GPR[1] content, which selects interface mode.
767 */
768 setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR);
769
770 ret = wait_for_bit_le32(&eqos->dma_regs->mode,
771 EQOS_DMA_MODE_SWR, false,
772 eqos->config->swr_wait, false);
773 if (ret) {
774 pr_err("EQOS_DMA_MODE_SWR stuck");
775 goto err_stop_resets;
776 }
777
778 ret = eqos->config->ops->eqos_calibrate_pads(dev);
779 if (ret < 0) {
780 pr_err("eqos_calibrate_pads() failed: %d", ret);
781 goto err_stop_resets;
782 }
783
784 if (eqos->config->ops->eqos_get_tick_clk_rate) {
785 rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
786
787 val = (rate / 1000000) - 1;
788 writel(val, &eqos->mac_regs->us_tic_counter);
789 }
790
791 /*
792 * if PHY was already connected and configured,
793 * don't need to reconnect/reconfigure again
794 */
795 if (!eqos->phy) {
796 int addr = -1;
797 ofnode fixed_node;
798
799 if (IS_ENABLED(CONFIG_PHY_FIXED)) {
800 fixed_node = ofnode_find_subnode(dev_ofnode(dev),
801 "fixed-link");
802 if (ofnode_valid(fixed_node))
803 eqos->phy = fixed_phy_create(dev_ofnode(dev));
804 }
805
806 if (!eqos->phy) {
807 addr = eqos_get_phy_addr(eqos, dev);
808 eqos->phy = phy_connect(eqos->mii, addr, dev,
809 eqos->config->interface(dev));
810 }
811
812 if (!eqos->phy) {
813 pr_err("phy_connect() failed");
814 goto err_stop_resets;
815 }
816
817 if (eqos->max_speed) {
818 ret = phy_set_supported(eqos->phy, eqos->max_speed);
819 if (ret) {
820 pr_err("phy_set_supported() failed: %d", ret);
821 goto err_shutdown_phy;
822 }
823 }
824
825 eqos->phy->node = eqos->phy_of_node;
826 ret = phy_config(eqos->phy);
827 if (ret < 0) {
828 pr_err("phy_config() failed: %d", ret);
829 goto err_shutdown_phy;
830 }
831 }
832
833 ret = phy_startup(eqos->phy);
834 if (ret < 0) {
835 pr_err("phy_startup() failed: %d", ret);
836 goto err_shutdown_phy;
837 }
838
839 if (!eqos->phy->link) {
840 pr_err("No link");
841 goto err_shutdown_phy;
842 }
843
844 ret = eqos_adjust_link(dev);
845 if (ret < 0) {
846 pr_err("eqos_adjust_link() failed: %d", ret);
847 goto err_shutdown_phy;
848 }
849
850 /* Configure MTL */
851
852 /* Enable Store and Forward mode for TX */
853 /* Program Tx operating mode */
854 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
855 EQOS_MTL_TXQ0_OPERATION_MODE_TSF |
856 (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
857 EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
858
859 /* Transmit Queue weight */
860 writel(0x10, &eqos->mtl_regs->txq0_quantum_weight);
861
862 /* Enable Store and Forward mode for RX, since no jumbo frame */
863 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
864 EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
865
866 /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
867 val = readl(&eqos->mac_regs->hw_feature1);
868 tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
869 EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
870 rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
871 EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
872
873 /* r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting */
874 tx_fifo_sz = 128 << tx_fifo_sz;
875 rx_fifo_sz = 128 << rx_fifo_sz;
876
877 /* Allow platform to override TX/RX fifo size */
878 if (eqos->tx_fifo_sz)
879 tx_fifo_sz = eqos->tx_fifo_sz;
880 if (eqos->rx_fifo_sz)
881 rx_fifo_sz = eqos->rx_fifo_sz;
882
883 /* r/tqs is encoded as (n / 256) - 1 */
884 tqs = tx_fifo_sz / 256 - 1;
885 rqs = rx_fifo_sz / 256 - 1;
886
887 clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
888 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
889 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
890 tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
891 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
892 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
893 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
894 rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
895
896 /* Flow control used only if each channel gets 4KB or more FIFO */
897 if (rqs >= ((4096 / 256) - 1)) {
898 u32 rfd, rfa;
899
900 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
901 EQOS_MTL_RXQ0_OPERATION_MODE_EHFC);
902
903 /*
904 * Set Threshold for Activating Flow Contol space for min 2
905 * frames ie, (1500 * 1) = 1500 bytes.
906 *
907 * Set Threshold for Deactivating Flow Contol for space of
908 * min 1 frame (frame size 1500bytes) in receive fifo
909 */
910 if (rqs == ((4096 / 256) - 1)) {
911 /*
912 * This violates the above formula because of FIFO size
913 * limit therefore overflow may occur inspite of this.
914 */
915 rfd = 0x3; /* Full-3K */
916 rfa = 0x1; /* Full-1.5K */
917 } else if (rqs == ((8192 / 256) - 1)) {
918 rfd = 0x6; /* Full-4K */
919 rfa = 0xa; /* Full-6K */
920 } else if (rqs == ((16384 / 256) - 1)) {
921 rfd = 0x6; /* Full-4K */
922 rfa = 0x12; /* Full-10K */
923 } else {
924 rfd = 0x6; /* Full-4K */
925 rfa = 0x1E; /* Full-16K */
926 }
927
928 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
929 (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK <<
930 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
931 (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK <<
932 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT),
933 (rfd <<
934 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
935 (rfa <<
936 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT));
937 }
938
939 /* Configure MAC */
940
941 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
942 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
943 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
944 eqos->config->config_mac <<
945 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
946
947 /* Multicast and Broadcast Queue Enable */
948 setbits_le32(&eqos->mac_regs->unused_0a4,
949 0x00100000);
950 /* enable promise mode */
951 setbits_le32(&eqos->mac_regs->unused_004[1],
952 0x1);
953
954 /* Set TX flow control parameters */
955 /* Set Pause Time */
956 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
957 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
958 /* Assign priority for TX flow control */
959 clrbits_le32(&eqos->mac_regs->txq_prty_map0,
960 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK <<
961 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT);
962 /* Assign priority for RX flow control */
963 clrbits_le32(&eqos->mac_regs->rxq_ctrl2,
964 EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK <<
965 EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
966 /* Enable flow control */
967 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
968 EQOS_MAC_Q0_TX_FLOW_CTRL_TFE);
969 setbits_le32(&eqos->mac_regs->rx_flow_ctrl,
970 EQOS_MAC_RX_FLOW_CTRL_RFE);
971
972 clrsetbits_le32(&eqos->mac_regs->configuration,
973 EQOS_MAC_CONFIGURATION_GPSLCE |
974 EQOS_MAC_CONFIGURATION_WD |
975 EQOS_MAC_CONFIGURATION_JD |
976 EQOS_MAC_CONFIGURATION_JE,
977 EQOS_MAC_CONFIGURATION_CST |
978 EQOS_MAC_CONFIGURATION_ACS);
979
980 eqos_write_hwaddr(dev);
981
982 /* Configure DMA */
983
984 /* Enable OSP mode */
985 setbits_le32(&eqos->dma_regs->ch0_tx_control,
986 EQOS_DMA_CH0_TX_CONTROL_OSP);
987
988 /* RX buffer size. Must be a multiple of bus width */
989 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
990 EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
991 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
992 EQOS_MAX_PACKET_SIZE <<
993 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
994
995 desc_pad = (eqos->desc_size - sizeof(struct eqos_desc)) /
996 eqos->config->axi_bus_width;
997
998 setbits_le32(&eqos->dma_regs->ch0_control,
999 EQOS_DMA_CH0_CONTROL_PBLX8 |
1000 (desc_pad << EQOS_DMA_CH0_CONTROL_DSL_SHIFT));
1001
1002 /*
1003 * Burst length must be < 1/2 FIFO size.
1004 * FIFO size in tqs is encoded as (n / 256) - 1.
1005 * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
1006 * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
1007 */
1008 pbl = tqs + 1;
1009 if (pbl > 32)
1010 pbl = 32;
1011 clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,
1012 EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
1013 EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
1014 pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
1015
1016 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1017 EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
1018 EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
1019 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
1020
1021 /* DMA performance configuration */
1022 val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
1023 EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 |
1024 EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4;
1025 writel(val, &eqos->dma_regs->sysbus_mode);
1026
1027 /* Set up descriptors */
1028
1029 memset(eqos->tx_descs, 0, eqos->desc_size * EQOS_DESCRIPTORS_TX);
1030 memset(eqos->rx_descs, 0, eqos->desc_size * EQOS_DESCRIPTORS_RX);
1031
1032 for (i = 0; i < EQOS_DESCRIPTORS_TX; i++) {
1033 struct eqos_desc *tx_desc = eqos_get_desc(eqos, i, false);
1034 eqos->config->ops->eqos_flush_desc(tx_desc);
1035 }
1036
1037 for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
1038 struct eqos_desc *rx_desc = eqos_get_desc(eqos, i, true);
1039 rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
1040 (i * EQOS_MAX_PACKET_SIZE));
1041 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
1042 mb();
1043 eqos->config->ops->eqos_flush_desc(rx_desc);
1044 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf +
1045 (i * EQOS_MAX_PACKET_SIZE),
1046 EQOS_MAX_PACKET_SIZE);
1047 }
1048
1049 writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
1050 writel((ulong)eqos_get_desc(eqos, 0, false),
1051 &eqos->dma_regs->ch0_txdesc_list_address);
1052 writel(EQOS_DESCRIPTORS_TX - 1,
1053 &eqos->dma_regs->ch0_txdesc_ring_length);
1054
1055 writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
1056 writel((ulong)eqos_get_desc(eqos, 0, true),
1057 &eqos->dma_regs->ch0_rxdesc_list_address);
1058 writel(EQOS_DESCRIPTORS_RX - 1,
1059 &eqos->dma_regs->ch0_rxdesc_ring_length);
1060
1061 /* Enable everything */
1062 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1063 EQOS_DMA_CH0_TX_CONTROL_ST);
1064 setbits_le32(&eqos->dma_regs->ch0_rx_control,
1065 EQOS_DMA_CH0_RX_CONTROL_SR);
1066 setbits_le32(&eqos->mac_regs->configuration,
1067 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1068
1069 /* TX tail pointer not written until we need to TX a packet */
1070 /*
1071 * Point RX tail pointer at last descriptor. Ideally, we'd point at the
1072 * first descriptor, implying all descriptors were available. However,
1073 * that's not distinguishable from none of the descriptors being
1074 * available.
1075 */
1076 last_rx_desc = (ulong)eqos_get_desc(eqos, EQOS_DESCRIPTORS_RX - 1, true);
1077 writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1078
1079 eqos->started = true;
1080
1081 debug("%s: OK\n", __func__);
1082 return 0;
1083
1084 err_shutdown_phy:
1085 phy_shutdown(eqos->phy);
1086 err_stop_resets:
1087 eqos->config->ops->eqos_stop_resets(dev);
1088 err:
1089 pr_err("FAILED: %d", ret);
1090 return ret;
1091 }
1092
eqos_stop(struct udevice * dev)1093 static void eqos_stop(struct udevice *dev)
1094 {
1095 struct eqos_priv *eqos = dev_get_priv(dev);
1096 int i;
1097
1098 debug("%s(dev=%p):\n", __func__, dev);
1099
1100 if (!eqos->started)
1101 return;
1102 eqos->started = false;
1103 eqos->reg_access_ok = false;
1104
1105 /* Disable TX DMA */
1106 clrbits_le32(&eqos->dma_regs->ch0_tx_control,
1107 EQOS_DMA_CH0_TX_CONTROL_ST);
1108
1109 /* Wait for TX all packets to drain out of MTL */
1110 for (i = 0; i < 1000000; i++) {
1111 u32 val = readl(&eqos->mtl_regs->txq0_debug);
1112 u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) &
1113 EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK;
1114 u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS;
1115 if ((trcsts != 1) && (!txqsts))
1116 break;
1117 }
1118
1119 /* Turn off MAC TX and RX */
1120 clrbits_le32(&eqos->mac_regs->configuration,
1121 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1122
1123 /* Wait for all RX packets to drain out of MTL */
1124 for (i = 0; i < 1000000; i++) {
1125 u32 val = readl(&eqos->mtl_regs->rxq0_debug);
1126 u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) &
1127 EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK;
1128 u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) &
1129 EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK;
1130 if ((!prxq) && (!rxqsts))
1131 break;
1132 }
1133
1134 /* Turn off RX DMA */
1135 clrbits_le32(&eqos->dma_regs->ch0_rx_control,
1136 EQOS_DMA_CH0_RX_CONTROL_SR);
1137
1138 if (eqos->phy) {
1139 phy_shutdown(eqos->phy);
1140 }
1141 eqos->config->ops->eqos_stop_resets(dev);
1142
1143 debug("%s: OK\n", __func__);
1144 }
1145
eqos_send(struct udevice * dev,void * packet,int length)1146 static int eqos_send(struct udevice *dev, void *packet, int length)
1147 {
1148 struct eqos_priv *eqos = dev_get_priv(dev);
1149 struct eqos_desc *tx_desc;
1150 int i;
1151
1152 debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet,
1153 length);
1154
1155 memcpy(eqos->tx_dma_buf, packet, length);
1156 eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length);
1157
1158 tx_desc = eqos_get_desc(eqos, eqos->tx_desc_idx, false);
1159 eqos->tx_desc_idx++;
1160 eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
1161
1162 tx_desc->des0 = (ulong)eqos->tx_dma_buf;
1163 tx_desc->des1 = 0;
1164 tx_desc->des2 = length;
1165 /*
1166 * Make sure that if HW sees the _OWN write below, it will see all the
1167 * writes to the rest of the descriptor too.
1168 */
1169 mb();
1170 tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
1171 eqos->config->ops->eqos_flush_desc(tx_desc);
1172
1173 writel((ulong)eqos_get_desc(eqos, eqos->tx_desc_idx, false),
1174 &eqos->dma_regs->ch0_txdesc_tail_pointer);
1175
1176 for (i = 0; i < 1000000; i++) {
1177 eqos->config->ops->eqos_inval_desc(tx_desc);
1178 if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN))
1179 return 0;
1180 udelay(1);
1181 }
1182
1183 debug("%s: TX timeout\n", __func__);
1184
1185 return -ETIMEDOUT;
1186 }
1187
eqos_recv(struct udevice * dev,int flags,uchar ** packetp)1188 static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
1189 {
1190 struct eqos_priv *eqos = dev_get_priv(dev);
1191 struct eqos_desc *rx_desc;
1192 int length;
1193
1194 debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
1195
1196 rx_desc = eqos_get_desc(eqos, eqos->rx_desc_idx, true);
1197 eqos->config->ops->eqos_inval_desc(rx_desc);
1198 if (rx_desc->des3 & EQOS_DESC3_OWN) {
1199 debug("%s: RX packet not available\n", __func__);
1200 return -EAGAIN;
1201 }
1202
1203 *packetp = eqos->rx_dma_buf +
1204 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1205 length = rx_desc->des3 & 0x7fff;
1206 debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length);
1207
1208 eqos->config->ops->eqos_inval_buffer(*packetp, length);
1209
1210 return length;
1211 }
1212
eqos_free_pkt(struct udevice * dev,uchar * packet,int length)1213 static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
1214 {
1215 struct eqos_priv *eqos = dev_get_priv(dev);
1216 u32 idx, idx_mask = eqos->desc_per_cacheline - 1;
1217 uchar *packet_expected;
1218 struct eqos_desc *rx_desc;
1219
1220 debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
1221
1222 packet_expected = eqos->rx_dma_buf +
1223 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1224 if (packet != packet_expected) {
1225 debug("%s: Unexpected packet (expected %p)\n", __func__,
1226 packet_expected);
1227 return -EINVAL;
1228 }
1229
1230 eqos->config->ops->eqos_inval_buffer(packet, length);
1231
1232 if ((eqos->rx_desc_idx & idx_mask) == idx_mask) {
1233 for (idx = eqos->rx_desc_idx - idx_mask;
1234 idx <= eqos->rx_desc_idx;
1235 idx++) {
1236 rx_desc = eqos_get_desc(eqos, idx, true);
1237 rx_desc->des0 = 0;
1238 mb();
1239 eqos->config->ops->eqos_flush_desc(rx_desc);
1240 eqos->config->ops->eqos_inval_buffer(packet, length);
1241 rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
1242 (idx * EQOS_MAX_PACKET_SIZE));
1243 rx_desc->des1 = 0;
1244 rx_desc->des2 = 0;
1245 /*
1246 * Make sure that if HW sees the _OWN write below,
1247 * it will see all the writes to the rest of the
1248 * descriptor too.
1249 */
1250 mb();
1251 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
1252 eqos->config->ops->eqos_flush_desc(rx_desc);
1253 }
1254 writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1255 }
1256
1257 eqos->rx_desc_idx++;
1258 eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX;
1259
1260 return 0;
1261 }
1262
eqos_probe_resources_core(struct udevice * dev)1263 static int eqos_probe_resources_core(struct udevice *dev)
1264 {
1265 struct eqos_priv *eqos = dev_get_priv(dev);
1266 unsigned int desc_step;
1267 int ret;
1268
1269 debug("%s(dev=%p):\n", __func__, dev);
1270
1271 /* Maximum distance between neighboring descriptors, in Bytes. */
1272 desc_step = sizeof(struct eqos_desc) +
1273 EQOS_DMA_CH0_CONTROL_DSL_MASK * eqos->config->axi_bus_width;
1274 if (desc_step < ARCH_DMA_MINALIGN) {
1275 /*
1276 * The EQoS hardware implementation cannot place one descriptor
1277 * per cacheline, it is necessary to place multiple descriptors
1278 * per cacheline in memory and do cache management carefully.
1279 */
1280 eqos->desc_size = BIT(fls(desc_step) - 1);
1281 } else {
1282 eqos->desc_size = ALIGN(sizeof(struct eqos_desc),
1283 (unsigned int)ARCH_DMA_MINALIGN);
1284 }
1285 eqos->desc_per_cacheline = ARCH_DMA_MINALIGN / eqos->desc_size;
1286
1287 eqos->tx_descs = eqos_alloc_descs(eqos, EQOS_DESCRIPTORS_TX);
1288 if (!eqos->tx_descs) {
1289 debug("%s: eqos_alloc_descs(tx) failed\n", __func__);
1290 ret = -ENOMEM;
1291 goto err;
1292 }
1293
1294 eqos->rx_descs = eqos_alloc_descs(eqos, EQOS_DESCRIPTORS_RX);
1295 if (!eqos->rx_descs) {
1296 debug("%s: eqos_alloc_descs(rx) failed\n", __func__);
1297 ret = -ENOMEM;
1298 goto err_free_tx_descs;
1299 }
1300
1301 eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE);
1302 if (!eqos->tx_dma_buf) {
1303 debug("%s: memalign(tx_dma_buf) failed\n", __func__);
1304 ret = -ENOMEM;
1305 goto err_free_descs;
1306 }
1307 debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf);
1308
1309 eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE);
1310 if (!eqos->rx_dma_buf) {
1311 debug("%s: memalign(rx_dma_buf) failed\n", __func__);
1312 ret = -ENOMEM;
1313 goto err_free_tx_dma_buf;
1314 }
1315 debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
1316
1317 eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
1318 if (!eqos->rx_pkt) {
1319 debug("%s: malloc(rx_pkt) failed\n", __func__);
1320 ret = -ENOMEM;
1321 goto err_free_rx_dma_buf;
1322 }
1323 debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
1324
1325 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf,
1326 EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX);
1327
1328 debug("%s: OK\n", __func__);
1329 return 0;
1330
1331 err_free_rx_dma_buf:
1332 free(eqos->rx_dma_buf);
1333 err_free_tx_dma_buf:
1334 free(eqos->tx_dma_buf);
1335 err_free_descs:
1336 eqos_free_descs(eqos->rx_descs);
1337 err_free_tx_descs:
1338 eqos_free_descs(eqos->tx_descs);
1339 err:
1340
1341 debug("%s: returns %d\n", __func__, ret);
1342 return ret;
1343 }
1344
eqos_remove_resources_core(struct udevice * dev)1345 static int eqos_remove_resources_core(struct udevice *dev)
1346 {
1347 struct eqos_priv *eqos = dev_get_priv(dev);
1348
1349 debug("%s(dev=%p):\n", __func__, dev);
1350
1351 free(eqos->rx_pkt);
1352 free(eqos->rx_dma_buf);
1353 free(eqos->tx_dma_buf);
1354 eqos_free_descs(eqos->rx_descs);
1355 eqos_free_descs(eqos->tx_descs);
1356
1357 debug("%s: OK\n", __func__);
1358 return 0;
1359 }
1360
eqos_probe_resources_tegra186(struct udevice * dev)1361 static int eqos_probe_resources_tegra186(struct udevice *dev)
1362 {
1363 struct eqos_priv *eqos = dev_get_priv(dev);
1364 int ret;
1365
1366 debug("%s(dev=%p):\n", __func__, dev);
1367
1368 ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
1369 if (ret) {
1370 pr_err("reset_get_by_name(rst) failed: %d", ret);
1371 return ret;
1372 }
1373
1374 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1375 &eqos->phy_reset_gpio,
1376 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
1377 if (ret) {
1378 pr_err("gpio_request_by_name(phy reset) failed: %d", ret);
1379 goto err_free_reset_eqos;
1380 }
1381
1382 ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus);
1383 if (ret) {
1384 pr_err("clk_get_by_name(slave_bus) failed: %d", ret);
1385 goto err_free_gpio_phy_reset;
1386 }
1387
1388 ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
1389 if (ret) {
1390 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
1391 goto err_free_clk_slave_bus;
1392 }
1393
1394 ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
1395 if (ret) {
1396 pr_err("clk_get_by_name(rx) failed: %d", ret);
1397 goto err_free_clk_master_bus;
1398 }
1399
1400 ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
1401 if (ret) {
1402 pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
1403 goto err_free_clk_rx;
1404 }
1405
1406 ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
1407 if (ret) {
1408 pr_err("clk_get_by_name(tx) failed: %d", ret);
1409 goto err_free_clk_ptp_ref;
1410 }
1411
1412 debug("%s: OK\n", __func__);
1413 return 0;
1414
1415 err_free_clk_ptp_ref:
1416 clk_free(&eqos->clk_ptp_ref);
1417 err_free_clk_rx:
1418 clk_free(&eqos->clk_rx);
1419 err_free_clk_master_bus:
1420 clk_free(&eqos->clk_master_bus);
1421 err_free_clk_slave_bus:
1422 clk_free(&eqos->clk_slave_bus);
1423 err_free_gpio_phy_reset:
1424 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1425 err_free_reset_eqos:
1426 reset_free(&eqos->reset_ctl);
1427
1428 debug("%s: returns %d\n", __func__, ret);
1429 return ret;
1430 }
1431
eqos_probe_resources_stm32(struct udevice * dev)1432 static int eqos_probe_resources_stm32(struct udevice *dev)
1433 {
1434 struct eqos_priv *eqos = dev_get_priv(dev);
1435 int ret;
1436 phy_interface_t interface;
1437
1438 debug("%s(dev=%p):\n", __func__, dev);
1439
1440 interface = eqos->config->interface(dev);
1441
1442 if (interface == PHY_INTERFACE_MODE_NA) {
1443 pr_err("Invalid PHY interface\n");
1444 return -EINVAL;
1445 }
1446
1447 ret = board_interface_eth_init(dev, interface);
1448 if (ret)
1449 return -EINVAL;
1450
1451 ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
1452 if (ret) {
1453 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
1454 goto err_probe;
1455 }
1456
1457 ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
1458 if (ret) {
1459 pr_err("clk_get_by_name(rx) failed: %d", ret);
1460 goto err_free_clk_master_bus;
1461 }
1462
1463 ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
1464 if (ret) {
1465 pr_err("clk_get_by_name(tx) failed: %d", ret);
1466 goto err_free_clk_rx;
1467 }
1468
1469 /* Get ETH_CLK clocks (optional) */
1470 ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
1471 if (ret)
1472 pr_warn("No phy clock provided %d", ret);
1473
1474 debug("%s: OK\n", __func__);
1475 return 0;
1476
1477 err_free_clk_rx:
1478 clk_free(&eqos->clk_rx);
1479 err_free_clk_master_bus:
1480 clk_free(&eqos->clk_master_bus);
1481 err_probe:
1482
1483 debug("%s: returns %d\n", __func__, ret);
1484 return ret;
1485 }
1486
eqos_get_interface_tegra186(const struct udevice * dev)1487 static phy_interface_t eqos_get_interface_tegra186(const struct udevice *dev)
1488 {
1489 return PHY_INTERFACE_MODE_MII;
1490 }
1491
eqos_remove_resources_tegra186(struct udevice * dev)1492 static int eqos_remove_resources_tegra186(struct udevice *dev)
1493 {
1494 struct eqos_priv *eqos = dev_get_priv(dev);
1495
1496 debug("%s(dev=%p):\n", __func__, dev);
1497
1498 #ifdef CONFIG_CLK
1499 clk_free(&eqos->clk_tx);
1500 clk_free(&eqos->clk_ptp_ref);
1501 clk_free(&eqos->clk_rx);
1502 clk_free(&eqos->clk_slave_bus);
1503 clk_free(&eqos->clk_master_bus);
1504 #endif
1505 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1506 reset_free(&eqos->reset_ctl);
1507
1508 debug("%s: OK\n", __func__);
1509 return 0;
1510 }
1511
eqos_remove_resources_stm32(struct udevice * dev)1512 static int eqos_remove_resources_stm32(struct udevice *dev)
1513 {
1514 struct eqos_priv * __maybe_unused eqos = dev_get_priv(dev);
1515
1516 debug("%s(dev=%p):\n", __func__, dev);
1517
1518 #ifdef CONFIG_CLK
1519 clk_free(&eqos->clk_tx);
1520 clk_free(&eqos->clk_rx);
1521 clk_free(&eqos->clk_master_bus);
1522 if (clk_valid(&eqos->clk_ck))
1523 clk_free(&eqos->clk_ck);
1524 #endif
1525
1526 debug("%s: OK\n", __func__);
1527 return 0;
1528 }
1529
eqos_probe(struct udevice * dev)1530 static int eqos_probe(struct udevice *dev)
1531 {
1532 struct eqos_priv *eqos = dev_get_priv(dev);
1533 int ret;
1534
1535 debug("%s(dev=%p):\n", __func__, dev);
1536
1537 eqos->dev = dev;
1538 eqos->config = (void *)dev_get_driver_data(dev);
1539
1540 eqos->regs = dev_read_addr(dev);
1541 if (eqos->regs == FDT_ADDR_T_NONE) {
1542 pr_err("dev_read_addr() failed");
1543 return -ENODEV;
1544 }
1545 eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
1546 eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE);
1547 eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);
1548 eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
1549
1550 eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
1551
1552 ret = eqos_probe_resources_core(dev);
1553 if (ret < 0) {
1554 pr_err("eqos_probe_resources_core() failed: %d", ret);
1555 return ret;
1556 }
1557
1558 ret = eqos->config->ops->eqos_probe_resources(dev);
1559 if (ret < 0) {
1560 pr_err("eqos_probe_resources() failed: %d", ret);
1561 goto err_remove_resources_core;
1562 }
1563
1564 ret = eqos->config->ops->eqos_start_clks(dev);
1565 if (ret < 0) {
1566 pr_err("eqos_start_clks() failed: %d", ret);
1567 goto err_remove_resources_tegra;
1568 }
1569
1570 #ifdef CONFIG_DM_ETH_PHY
1571 eqos->mii = eth_phy_get_mdio_bus(dev);
1572 #endif
1573 if (!eqos->mii) {
1574 eqos->mii = mdio_alloc();
1575 if (!eqos->mii) {
1576 pr_err("mdio_alloc() failed");
1577 ret = -ENOMEM;
1578 goto err_stop_clks;
1579 }
1580 eqos->mii->read = eqos_mdio_read;
1581 eqos->mii->write = eqos_mdio_write;
1582 eqos->mii->priv = eqos;
1583 strcpy(eqos->mii->name, dev->name);
1584
1585 ret = mdio_register(eqos->mii);
1586 if (ret < 0) {
1587 pr_err("mdio_register() failed: %d", ret);
1588 goto err_free_mdio;
1589 }
1590 }
1591
1592 #ifdef CONFIG_DM_ETH_PHY
1593 eth_phy_set_mdio_bus(dev, eqos->mii);
1594 #endif
1595
1596 debug("%s: OK\n", __func__);
1597 return 0;
1598
1599 err_free_mdio:
1600 mdio_free(eqos->mii);
1601 err_stop_clks:
1602 eqos->config->ops->eqos_stop_clks(dev);
1603 err_remove_resources_tegra:
1604 eqos->config->ops->eqos_remove_resources(dev);
1605 err_remove_resources_core:
1606 eqos_remove_resources_core(dev);
1607
1608 debug("%s: returns %d\n", __func__, ret);
1609 return ret;
1610 }
1611
eqos_remove(struct udevice * dev)1612 static int eqos_remove(struct udevice *dev)
1613 {
1614 struct eqos_priv *eqos = dev_get_priv(dev);
1615
1616 debug("%s(dev=%p):\n", __func__, dev);
1617
1618 mdio_unregister(eqos->mii);
1619 mdio_free(eqos->mii);
1620 eqos->config->ops->eqos_stop_clks(dev);
1621 eqos->config->ops->eqos_remove_resources(dev);
1622
1623 eqos_remove_resources_core(dev);
1624
1625 debug("%s: OK\n", __func__);
1626 return 0;
1627 }
1628
eqos_null_ops(struct udevice * dev)1629 int eqos_null_ops(struct udevice *dev)
1630 {
1631 return 0;
1632 }
1633
1634 static const struct eth_ops eqos_ops = {
1635 .start = eqos_start,
1636 .stop = eqos_stop,
1637 .send = eqos_send,
1638 .recv = eqos_recv,
1639 .free_pkt = eqos_free_pkt,
1640 .write_hwaddr = eqos_write_hwaddr,
1641 .read_rom_hwaddr = eqos_read_rom_hwaddr,
1642 };
1643
1644 static struct eqos_ops eqos_tegra186_ops = {
1645 .eqos_inval_desc = eqos_inval_desc_generic,
1646 .eqos_flush_desc = eqos_flush_desc_generic,
1647 .eqos_inval_buffer = eqos_inval_buffer_tegra186,
1648 .eqos_flush_buffer = eqos_flush_buffer_tegra186,
1649 .eqos_probe_resources = eqos_probe_resources_tegra186,
1650 .eqos_remove_resources = eqos_remove_resources_tegra186,
1651 .eqos_stop_resets = eqos_stop_resets_tegra186,
1652 .eqos_start_resets = eqos_start_resets_tegra186,
1653 .eqos_stop_clks = eqos_stop_clks_tegra186,
1654 .eqos_start_clks = eqos_start_clks_tegra186,
1655 .eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
1656 .eqos_disable_calibration = eqos_disable_calibration_tegra186,
1657 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
1658 .eqos_get_enetaddr = eqos_null_ops,
1659 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
1660 };
1661
1662 static const struct eqos_config __maybe_unused eqos_tegra186_config = {
1663 .reg_access_always_ok = false,
1664 .mdio_wait = 10,
1665 .swr_wait = 10,
1666 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
1667 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
1668 .axi_bus_width = EQOS_AXI_WIDTH_128,
1669 .interface = eqos_get_interface_tegra186,
1670 .ops = &eqos_tegra186_ops
1671 };
1672
1673 static struct eqos_ops eqos_stm32_ops = {
1674 .eqos_inval_desc = eqos_inval_desc_generic,
1675 .eqos_flush_desc = eqos_flush_desc_generic,
1676 .eqos_inval_buffer = eqos_inval_buffer_generic,
1677 .eqos_flush_buffer = eqos_flush_buffer_generic,
1678 .eqos_probe_resources = eqos_probe_resources_stm32,
1679 .eqos_remove_resources = eqos_remove_resources_stm32,
1680 .eqos_stop_resets = eqos_null_ops,
1681 .eqos_start_resets = eqos_null_ops,
1682 .eqos_stop_clks = eqos_stop_clks_stm32,
1683 .eqos_start_clks = eqos_start_clks_stm32,
1684 .eqos_calibrate_pads = eqos_null_ops,
1685 .eqos_disable_calibration = eqos_null_ops,
1686 .eqos_set_tx_clk_speed = eqos_null_ops,
1687 .eqos_get_enetaddr = eqos_null_ops,
1688 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
1689 };
1690
1691 static const struct eqos_config __maybe_unused eqos_stm32_config = {
1692 .reg_access_always_ok = false,
1693 .mdio_wait = 10000,
1694 .swr_wait = 50,
1695 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
1696 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
1697 .axi_bus_width = EQOS_AXI_WIDTH_64,
1698 .interface = dev_read_phy_mode,
1699 .ops = &eqos_stm32_ops
1700 };
1701
1702 static const struct udevice_id eqos_ids[] = {
1703 #if IS_ENABLED(CONFIG_DWC_ETH_QOS_TEGRA186)
1704 {
1705 .compatible = "nvidia,tegra186-eqos",
1706 .data = (ulong)&eqos_tegra186_config
1707 },
1708 #endif
1709 #if IS_ENABLED(CONFIG_DWC_ETH_QOS_STM32)
1710 {
1711 .compatible = "st,stm32mp1-dwmac",
1712 .data = (ulong)&eqos_stm32_config
1713 },
1714 #endif
1715 #if IS_ENABLED(CONFIG_DWC_ETH_QOS_IMX)
1716 {
1717 .compatible = "nxp,imx8mp-dwmac-eqos",
1718 .data = (ulong)&eqos_imx_config
1719 },
1720 #endif
1721
1722 #if IS_ENABLED(CONFIG_DWC_ETH_QOS_QCOM)
1723 {
1724 .compatible = "qcom,qcs404-ethqos",
1725 .data = (ulong)&eqos_qcom_config
1726 },
1727 #endif
1728
1729 { }
1730 };
1731
1732 U_BOOT_DRIVER(eth_eqos) = {
1733 .name = "eth_eqos",
1734 .id = UCLASS_ETH,
1735 .of_match = of_match_ptr(eqos_ids),
1736 .probe = eqos_probe,
1737 .remove = eqos_remove,
1738 .ops = &eqos_ops,
1739 .priv_auto = sizeof(struct eqos_priv),
1740 .plat_auto = sizeof(struct eth_pdata),
1741 };
1742