1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000-2004
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 *
9 * Conversion to DM
10 * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
11 */
12
13 #include <common.h>
14 #include <env.h>
15 #include <hang.h>
16 #include <malloc.h>
17 #include <command.h>
18 #include <config.h>
19 #include <net.h>
20 #include <miiphy.h>
21 #include <asm/global_data.h>
22 #include <linux/delay.h>
23 #include <linux/mii.h>
24 #include <asm/immap.h>
25 #include <asm/fsl_mcdmafec.h>
26
27 #include "MCD_dma.h"
28
29 #undef ET_DEBUG
30 #undef MII_DEBUG
31
32 /* Ethernet Transmit and Receive Buffers */
33 #define DBUF_LENGTH 1520
34 #define PKT_MAXBUF_SIZE 1518
35 #define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
36
37 /* RxBD bits definitions */
38 #define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
39 BD_ENET_RX_OV | BD_ENET_RX_TR)
40
41 DECLARE_GLOBAL_DATA_PTR;
42
init_eth_info(struct fec_info_dma * info)43 static void init_eth_info(struct fec_info_dma *info)
44 {
45 /* setup Receive and Transmit buffer descriptor */
46 #ifdef CFG_SYS_FEC_BUF_USE_SRAM
47 static u32 tmp;
48
49 if (info->index == 0)
50 tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
51 else
52 info->rxbd = (cbd_t *)DBUF_LENGTH;
53
54 info->rxbd = (cbd_t *)((u32)info->rxbd + tmp);
55 tmp = (u32)info->rxbd;
56 info->txbd =
57 (cbd_t *)((u32)info->txbd + tmp +
58 (PKTBUFSRX * sizeof(cbd_t)));
59 tmp = (u32)info->txbd;
60 info->txbuf =
61 (char *)((u32)info->txbuf + tmp +
62 (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
63 tmp = (u32)info->txbuf;
64 #else
65 info->rxbd =
66 (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
67 (PKTBUFSRX * sizeof(cbd_t)));
68 info->txbd =
69 (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
70 (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
71 info->txbuf =
72 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
73 #endif
74
75 #ifdef ET_DEBUG
76 printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd);
77 #endif
78 info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
79 }
80
fec_halt(struct udevice * dev)81 static void fec_halt(struct udevice *dev)
82 {
83 struct fec_info_dma *info = dev_get_priv(dev);
84 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
85 int counter = 0xffff;
86
87 /* issue graceful stop command to the FEC transmitter if necessary */
88 fecp->tcr |= FEC_TCR_GTS;
89
90 /* wait for graceful stop to register */
91 while ((counter--) && (!(fecp->eir & FEC_EIR_GRA)))
92 ;
93
94 /* Disable DMA tasks */
95 MCD_killDma(info->tx_task);
96 MCD_killDma(info->rx_task);
97
98 /* Disable the Ethernet Controller */
99 fecp->ecr &= ~FEC_ECR_ETHER_EN;
100
101 /* Clear FIFO status registers */
102 fecp->rfsr &= FIFO_ERRSTAT;
103 fecp->tfsr &= FIFO_ERRSTAT;
104
105 fecp->frst = 0x01000000;
106
107 /* Issue a reset command to the FEC chip */
108 fecp->ecr |= FEC_ECR_RESET;
109
110 /* wait at least 20 clock cycles */
111 mdelay(10);
112
113 #ifdef ET_DEBUG
114 printf("Ethernet task stopped\n");
115 #endif
116 }
117
118 #ifdef ET_DEBUG
dbg_fec_regs(struct eth_device * dev)119 static void dbg_fec_regs(struct eth_device *dev)
120 {
121 struct fec_info_dma *info = dev->priv;
122 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
123
124 printf("=====\n");
125 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
126 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
127 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
128 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
129 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
130 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
131 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
132 printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
133 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
134 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
135 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
136 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
137 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
138 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
139 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
140 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
141 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
142 printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
143 printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
144 printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
145 printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
146 printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
147 printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
148 printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
149 printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
150 printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
151 printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
152 printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
153 printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
154 printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
155 printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
156 printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
157 printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
158 printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
159 printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
160 }
161 #endif
162
set_fec_duplex_speed(volatile fecdma_t * fecp,int dup_spd)163 static void set_fec_duplex_speed(volatile fecdma_t *fecp, int dup_spd)
164 {
165 struct bd_info *bd = gd->bd;
166
167 if ((dup_spd >> 16) == FULL) {
168 /* Set maximum frame length */
169 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
170 FEC_RCR_PROM | 0x100;
171 fecp->tcr = FEC_TCR_FDEN;
172 } else {
173 /* Half duplex mode */
174 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
175 FEC_RCR_MII_MODE | FEC_RCR_DRT;
176 fecp->tcr &= ~FEC_TCR_FDEN;
177 }
178
179 if ((dup_spd & 0xFFFF) == _100BASET) {
180 #ifdef MII_DEBUG
181 printf("100Mbps\n");
182 #endif
183 bd->bi_ethspeed = 100;
184 } else {
185 #ifdef MII_DEBUG
186 printf("10Mbps\n");
187 #endif
188 bd->bi_ethspeed = 10;
189 }
190 }
191
fec_set_hwaddr(volatile fecdma_t * fecp,u8 * mac)192 static void fec_set_hwaddr(volatile fecdma_t *fecp, u8 *mac)
193 {
194 u8 curr_byte; /* byte for which to compute the CRC */
195 int byte; /* loop - counter */
196 int bit; /* loop - counter */
197 u32 crc = 0xffffffff; /* initial value */
198
199 for (byte = 0; byte < 6; byte++) {
200 curr_byte = mac[byte];
201 for (bit = 0; bit < 8; bit++) {
202 if ((curr_byte & 0x01) ^ (crc & 0x01)) {
203 crc >>= 1;
204 crc = crc ^ 0xedb88320;
205 } else {
206 crc >>= 1;
207 }
208 curr_byte >>= 1;
209 }
210 }
211
212 crc = crc >> 26;
213
214 /* Set individual hash table register */
215 if (crc >= 32) {
216 fecp->ialr = (1 << (crc - 32));
217 fecp->iaur = 0;
218 } else {
219 fecp->ialr = 0;
220 fecp->iaur = (1 << crc);
221 }
222
223 /* Set physical address */
224 fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
225 fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
226
227 /* Clear multicast address hash table */
228 fecp->gaur = 0;
229 fecp->galr = 0;
230 }
231
fec_init(struct udevice * dev)232 static int fec_init(struct udevice *dev)
233 {
234 struct fec_info_dma *info = dev_get_priv(dev);
235 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
236 int rval, i;
237 uchar enetaddr[6];
238
239 #ifdef ET_DEBUG
240 printf("fec_init: iobase 0x%08x ...\n", info->iobase);
241 #endif
242
243 fecpin_setclear(info, 1);
244 fec_halt(dev);
245
246 mii_init();
247 set_fec_duplex_speed(fecp, info->dup_spd);
248
249 /* We use strictly polling mode only */
250 fecp->eimr = 0;
251
252 /* Clear any pending interrupt */
253 fecp->eir = 0xffffffff;
254
255 /* Set station address */
256 if (info->index == 0)
257 rval = eth_env_get_enetaddr("ethaddr", enetaddr);
258 else
259 rval = eth_env_get_enetaddr("eth1addr", enetaddr);
260
261 if (!rval) {
262 puts("Please set a valid MAC address\n");
263 return -EINVAL;
264 }
265
266 fec_set_hwaddr(fecp, enetaddr);
267
268 /* Set Opcode/Pause Duration Register */
269 fecp->opd = 0x00010020;
270
271 /* Setup Buffers and Buffer Descriptors */
272 info->rx_idx = 0;
273 info->tx_idx = 0;
274
275 /* Setup Receiver Buffer Descriptors (13.14.24.18)
276 * Settings: Empty, Wrap */
277 for (i = 0; i < PKTBUFSRX; i++) {
278 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
279 info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
280 info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
281 }
282 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
283
284 /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
285 * Settings: Last, Tx CRC */
286 for (i = 0; i < CFG_SYS_TX_ETH_BUFFER; i++) {
287 info->txbd[i].cbd_sc = 0;
288 info->txbd[i].cbd_datlen = 0;
289 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
290 }
291 info->txbd[CFG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
292
293 info->used_tbd_idx = 0;
294 info->clean_tbd_num = CFG_SYS_TX_ETH_BUFFER;
295
296 /* Set Rx FIFO alarm and granularity value */
297 fecp->rfcr = 0x0c000000;
298 fecp->rfar = 0x0000030c;
299
300 /* Set Tx FIFO granularity value */
301 fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
302 fecp->tfar = 0x00000080;
303
304 fecp->tfwr = 0x2;
305 fecp->ctcwr = 0x03000000;
306
307 /* Enable DMA receive task */
308 MCD_startDma(info->rx_task,
309 (s8 *)info->rxbd,
310 0,
311 (s8 *)&fecp->rfdr,
312 4,
313 0,
314 4,
315 info->rx_init,
316 info->rx_pri,
317 (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),
318 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
319 );
320
321 /* Enable DMA tx task with no ready buffer descriptors */
322 MCD_startDma(info->tx_task,
323 (s8 *)info->txbd,
324 0,
325 (s8 *)&fecp->tfdr,
326 4,
327 0,
328 4,
329 info->tx_init,
330 info->tx_pri,
331 (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),
332 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
333 );
334
335 /* Now enable the transmit and receive processing */
336 fecp->ecr |= FEC_ECR_ETHER_EN;
337
338 return 0;
339 }
340
mcdmafec_init(struct udevice * dev)341 static int mcdmafec_init(struct udevice *dev)
342 {
343 return fec_init(dev);
344 }
345
mcdmafec_send(struct udevice * dev,void * packet,int length)346 static int mcdmafec_send(struct udevice *dev, void *packet, int length)
347 {
348 struct fec_info_dma *info = dev_get_priv(dev);
349 cbd_t *p_tbd, *p_used_tbd;
350 u16 phy_status;
351
352 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
353
354 /* process all the consumed TBDs */
355 while (info->clean_tbd_num < CFG_SYS_TX_ETH_BUFFER) {
356 p_used_tbd = &info->txbd[info->used_tbd_idx];
357 if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) {
358 #ifdef ET_DEBUG
359 printf("Cannot clean TBD %d, in use\n",
360 info->clean_tbd_num);
361 #endif
362 return 0;
363 }
364
365 /* clean this buffer descriptor */
366 if (info->used_tbd_idx == (CFG_SYS_TX_ETH_BUFFER - 1))
367 p_used_tbd->cbd_sc = BD_ENET_TX_WRAP;
368 else
369 p_used_tbd->cbd_sc = 0;
370
371 /* update some indeces for a correct handling of TBD ring */
372 info->clean_tbd_num++;
373 info->used_tbd_idx = (info->used_tbd_idx + 1)
374 % CFG_SYS_TX_ETH_BUFFER;
375 }
376
377 /* Check for valid length of data. */
378 if (length > 1500 || length <= 0)
379 return -1;
380
381 /* Check the number of vacant TxBDs. */
382 if (info->clean_tbd_num < 1) {
383 printf("No available TxBDs ...\n");
384 return -1;
385 }
386
387 /* Get the first TxBD to send the mac header */
388 p_tbd = &info->txbd[info->tx_idx];
389 p_tbd->cbd_datlen = length;
390 p_tbd->cbd_bufaddr = (u32)packet;
391 p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
392 info->tx_idx = (info->tx_idx + 1) % CFG_SYS_TX_ETH_BUFFER;
393
394 /* Enable DMA transmit task */
395 MCD_continDma(info->tx_task);
396
397 info->clean_tbd_num -= 1;
398
399 /* wait until frame is sent . */
400 while (p_tbd->cbd_sc & BD_ENET_TX_READY)
401 udelay(10);
402
403 return (int)(info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS);
404 }
405
mcdmafec_recv(struct udevice * dev,int flags,uchar ** packetp)406 static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp)
407 {
408 struct fec_info_dma *info = dev_get_priv(dev);
409 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
410
411 cbd_t *prbd = &info->rxbd[info->rx_idx];
412 u32 ievent;
413 int frame_length, len = 0;
414
415 /* Check if any critical events have happened */
416 ievent = fecp->eir;
417 if (ievent != 0) {
418 fecp->eir = ievent;
419
420 if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
421 printf("fec_recv: error\n");
422 fec_halt(dev);
423 fec_init(dev);
424 return 0;
425 }
426
427 if (ievent & FEC_EIR_HBERR) {
428 /* Heartbeat error */
429 fecp->tcr |= FEC_TCR_GTS;
430 }
431
432 if (ievent & FEC_EIR_GRA) {
433 /* Graceful stop complete */
434 if (fecp->tcr & FEC_TCR_GTS) {
435 printf("fec_recv: tcr_gts\n");
436 fec_halt(dev);
437 fecp->tcr &= ~FEC_TCR_GTS;
438 fec_init(dev);
439 }
440 }
441 }
442
443 if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
444 if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
445 !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
446 ((prbd->cbd_datlen - 4) > 14)) {
447 /* Get buffer address and size */
448 frame_length = prbd->cbd_datlen - 4;
449
450 /* Fill the buffer and pass it to upper layers */
451 net_process_received_packet((uchar *)prbd->cbd_bufaddr,
452 frame_length);
453 len = frame_length;
454 }
455
456 /* Reset buffer descriptor as empty */
457 if (info->rx_idx == (PKTBUFSRX - 1))
458 prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
459 else
460 prbd->cbd_sc = BD_ENET_RX_EMPTY;
461
462 prbd->cbd_datlen = PKTSIZE_ALIGN;
463
464 /* Now, we have an empty RxBD, restart the DMA receive task */
465 MCD_continDma(info->rx_task);
466
467 /* Increment BD count */
468 info->rx_idx = (info->rx_idx + 1) % PKTBUFSRX;
469 }
470
471 return len;
472 }
473
mcdmafec_halt(struct udevice * dev)474 static void mcdmafec_halt(struct udevice *dev)
475 {
476 fec_halt(dev);
477 }
478
479 static const struct eth_ops mcdmafec_ops = {
480 .start = mcdmafec_init,
481 .send = mcdmafec_send,
482 .recv = mcdmafec_recv,
483 .stop = mcdmafec_halt,
484 };
485
486 /*
487 * Boot sequence, called just after mcffec_of_to_plat,
488 * as DM way, it replaces old mcffec_initialize.
489 */
mcdmafec_probe(struct udevice * dev)490 static int mcdmafec_probe(struct udevice *dev)
491 {
492 struct fec_info_dma *info = dev_get_priv(dev);
493 struct eth_pdata *pdata = dev_get_plat(dev);
494 int node = dev_of_offset(dev);
495 int retval;
496 const u32 *val;
497
498 info->index = dev_seq(dev);
499 info->iobase = pdata->iobase;
500 info->miibase = pdata->iobase;
501 info->phy_addr = -1;
502
503 val = fdt_getprop(gd->fdt_blob, node, "rx-task", NULL);
504 if (val)
505 info->rx_task = fdt32_to_cpu(*val);
506
507 val = fdt_getprop(gd->fdt_blob, node, "tx-task", NULL);
508 if (val)
509 info->tx_task = fdt32_to_cpu(*val);
510
511 val = fdt_getprop(gd->fdt_blob, node, "rx-prioprity", NULL);
512 if (val)
513 info->rx_pri = fdt32_to_cpu(*val);
514
515 val = fdt_getprop(gd->fdt_blob, node, "tx-prioprity", NULL);
516 if (val)
517 info->tx_pri = fdt32_to_cpu(*val);
518
519 val = fdt_getprop(gd->fdt_blob, node, "rx-init", NULL);
520 if (val)
521 info->rx_init = fdt32_to_cpu(*val);
522
523 val = fdt_getprop(gd->fdt_blob, node, "tx-init", NULL);
524 if (val)
525 info->tx_init = fdt32_to_cpu(*val);
526
527 #ifdef CFG_SYS_FEC_BUF_USE_SRAM
528 u32 tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
529 #endif
530 init_eth_info(info);
531
532 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
533 info->bus = mdio_alloc();
534 if (!info->bus)
535 return -ENOMEM;
536 strlcpy(info->bus->name, dev->name, MDIO_NAME_LEN);
537 info->bus->read = mcffec_miiphy_read;
538 info->bus->write = mcffec_miiphy_write;
539
540 retval = mdio_register(info->bus);
541 if (retval < 0)
542 return retval;
543 #endif
544
545 return 0;
546 }
547
mcdmafec_remove(struct udevice * dev)548 static int mcdmafec_remove(struct udevice *dev)
549 {
550 struct fec_info_dma *priv = dev_get_priv(dev);
551
552 mdio_unregister(priv->bus);
553 mdio_free(priv->bus);
554
555 return 0;
556 }
557
558 /*
559 * Boot sequence, called 1st
560 */
mcdmafec_of_to_plat(struct udevice * dev)561 static int mcdmafec_of_to_plat(struct udevice *dev)
562 {
563 struct eth_pdata *pdata = dev_get_plat(dev);
564 const u32 *val;
565
566 pdata->iobase = dev_read_addr(dev);
567 /* Default to 10Mbit/s */
568 pdata->max_speed = 10;
569
570 val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
571 if (val)
572 pdata->max_speed = fdt32_to_cpu(*val);
573
574 return 0;
575 }
576
577 static const struct udevice_id mcdmafec_ids[] = {
578 { .compatible = "fsl,mcf-dma-fec" },
579 { }
580 };
581
582 U_BOOT_DRIVER(mcffec) = {
583 .name = "mcdmafec",
584 .id = UCLASS_ETH,
585 .of_match = mcdmafec_ids,
586 .of_to_plat = mcdmafec_of_to_plat,
587 .probe = mcdmafec_probe,
588 .remove = mcdmafec_remove,
589 .ops = &mcdmafec_ops,
590 .priv_auto = sizeof(struct fec_info_dma),
591 .plat_auto = sizeof(struct eth_pdata),
592 };
593