1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 */
6
7 #include <common.h>
8 #include <config.h>
9 #include <net.h>
10 #include <netdev.h>
11 #include <asm/global_data.h>
12 #include <linux/delay.h>
13
14 #include <asm/fec.h>
15 #include <asm/immap.h>
16 #include <linux/mii.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 #if defined(CONFIG_CMD_NET)
21 #undef MII_DEBUG
22 #undef ET_DEBUG
23
24 /*extern int fecpin_setclear(struct eth_device *dev, int setclear);*/
25
26 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
27 #include <miiphy.h>
28
29 /* Make MII read/write commands for the FEC. */
30 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
31 (REG & 0x1f) << 18))
32 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
33 (REG & 0x1f) << 18) | (VAL & 0xffff))
34
35 #ifndef CFG_SYS_UNSPEC_PHYID
36 # define CFG_SYS_UNSPEC_PHYID 0
37 #endif
38 #ifndef CFG_SYS_UNSPEC_STRID
39 # define CFG_SYS_UNSPEC_STRID 0
40 #endif
41
42 typedef struct phy_info_struct {
43 u32 phyid;
44 char *strid;
45 } phy_info_t;
46
47 phy_info_t phyinfo[] = {
48 {0x0022561B, "AMD79C784VC"}, /* AMD 79C784VC */
49 {0x00406322, "BCM5222"}, /* Broadcom 5222 */
50 {0x02a80150, "Intel82555"}, /* Intel 82555 */
51 {0x0016f870, "LSI80225"}, /* LSI 80225 */
52 {0x0016f880, "LSI80225/B"}, /* LSI 80225/B */
53 {0x78100000, "LXT970"}, /* LXT970 */
54 {0x001378e0, "LXT971"}, /* LXT971 and 972 */
55 {0x00221619, "KS8721BL"}, /* Micrel KS8721BL/SL */
56 {0x00221512, "KSZ8041NL"}, /* Micrel KSZ8041NL */
57 {0x20005CE1, "N83640"}, /* National 83640 */
58 {0x20005C90, "N83848"}, /* National 83848 */
59 {0x20005CA2, "N83849"}, /* National 83849 */
60 {0x01814400, "QS6612"}, /* QS6612 */
61 #if defined(CFG_SYS_UNSPEC_PHYID) && defined(CFG_SYS_UNSPEC_STRID)
62 {CFG_SYS_UNSPEC_PHYID, CFG_SYS_UNSPEC_STRID},
63 #endif
64 {0, 0}
65 };
66
67 /*
68 * mii_init -- Initialize the MII for MII command without ethernet
69 * This function is a subset of eth_init
70 */
mii_reset(fec_info_t * info)71 void mii_reset(fec_info_t *info)
72 {
73 volatile FEC_T *fecp = (FEC_T *) (info->miibase);
74 int i;
75
76 fecp->ecr = FEC_ECR_RESET;
77
78 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
79 udelay(1);
80 }
81 if (i == FEC_RESET_DELAY)
82 printf("FEC_RESET_DELAY timeout\n");
83 }
84
85 /* send command to phy using mii, wait for result */
mii_send(uint mii_cmd)86 uint mii_send(uint mii_cmd)
87 {
88 struct udevice *dev;
89 fec_info_t *info;
90 volatile FEC_T *ep;
91 uint mii_reply;
92 int j = 0;
93
94 /* retrieve from register structure */
95 dev = eth_get_dev();
96 info = dev_get_priv(dev);
97
98 ep = (FEC_T *) info->miibase;
99
100 ep->mmfr = mii_cmd; /* command to phy */
101
102 /* wait for mii complete */
103 while (!(ep->eir & FEC_EIR_MII) && (j < info->to_loop)) {
104 udelay(1);
105 j++;
106 }
107 if (j >= info->to_loop) {
108 printf("MII not complete\n");
109 return -1;
110 }
111
112 mii_reply = ep->mmfr; /* result from phy */
113 ep->eir = FEC_EIR_MII; /* clear MII complete */
114 #ifdef ET_DEBUG
115 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
116 __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
117 #endif
118
119 return (mii_reply & 0xffff); /* data read from phy */
120 }
121 #endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
122
123 #if defined(CONFIG_SYS_DISCOVER_PHY)
mii_discover_phy(fec_info_t * info)124 int mii_discover_phy(fec_info_t *info)
125 {
126 #define MAX_PHY_PASSES 11
127 int phyaddr, pass;
128 uint phyno, phytype;
129 int i, found = 0;
130
131 if (info->phyname_init)
132 return info->phy_addr;
133
134 phyaddr = -1; /* didn't find a PHY yet */
135 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
136 if (pass > 1) {
137 /* PHY may need more time to recover from reset.
138 * The LXT970 needs 50ms typical, no maximum is
139 * specified, so wait 10ms before try again.
140 * With 11 passes this gives it 100ms to wake up.
141 */
142 udelay(10000); /* wait 10ms */
143 }
144
145 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
146
147 phytype = mii_send(mk_mii_read(phyno, MII_PHYSID1));
148 #ifdef ET_DEBUG
149 printf("PHY type 0x%x pass %d\n", phytype, pass);
150 #endif
151 if (phytype == 0xffff)
152 continue;
153 phyaddr = phyno;
154 phytype <<= 16;
155 phytype |=
156 mii_send(mk_mii_read(phyno, MII_PHYSID2));
157
158 #ifdef ET_DEBUG
159 printf("PHY @ 0x%x pass %d\n", phyno, pass);
160 #endif
161
162 for (i = 0; (i < ARRAY_SIZE(phyinfo))
163 && (phyinfo[i].phyid != 0); i++) {
164 if (phyinfo[i].phyid == phytype) {
165 #ifdef ET_DEBUG
166 printf("phyid %x - %s\n",
167 phyinfo[i].phyid,
168 phyinfo[i].strid);
169 #endif
170 strcpy(info->phy_name, phyinfo[i].strid);
171 info->phyname_init = 1;
172 found = 1;
173 break;
174 }
175 }
176
177 if (!found) {
178 #ifdef ET_DEBUG
179 printf("0x%08x\n", phytype);
180 #endif
181 strcpy(info->phy_name, "unknown");
182 info->phyname_init = 1;
183 break;
184 }
185 }
186 }
187
188 if (phyaddr < 0)
189 printf("No PHY device found.\n");
190
191 return phyaddr;
192 }
193 #endif /* CONFIG_SYS_DISCOVER_PHY */
194
mii_init(void)195 __weak void mii_init(void)
196 {
197 struct udevice *dev;
198 fec_info_t *info;
199 volatile FEC_T *fecp;
200 int miispd = 0, i = 0;
201 u16 status = 0;
202 u16 linkgood = 0;
203
204 /* retrieve from register structure */
205 dev = eth_get_dev();
206 info = dev_get_priv(dev);
207
208 fecp = (FEC_T *) info->miibase;
209
210 fecpin_setclear(info, 1);
211
212 mii_reset(info);
213
214 /* We use strictly polling mode only */
215 fecp->eimr = 0;
216
217 /* Clear any pending interrupt */
218 fecp->eir = 0xffffffff;
219
220 /* Set MII speed */
221 miispd = (gd->bus_clk / 1000000) / 5;
222 fecp->mscr = miispd << 1;
223
224 #ifdef CONFIG_SYS_DISCOVER_PHY
225 info->phy_addr = mii_discover_phy(info);
226 #endif
227 if (info->phy_addr == -1)
228 return;
229
230 while (i < info->to_loop) {
231 status = 0;
232 i++;
233 /* Read PHY control register */
234 miiphy_read(dev->name, info->phy_addr, MII_BMCR, &status);
235
236 /* If phy set to autonegotiate, wait for autonegotiation done,
237 * if phy is not autonegotiating, just wait for link up.
238 */
239 if ((status & BMCR_ANENABLE) == BMCR_ANENABLE) {
240 linkgood = (BMSR_ANEGCOMPLETE | BMSR_LSTATUS);
241 } else {
242 linkgood = BMSR_LSTATUS;
243 }
244 /* Read PHY status register */
245 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status);
246 if ((status & linkgood) == linkgood)
247 break;
248
249 udelay(1);
250 }
251 if (i >= info->to_loop)
252 printf("Link UP timeout\n");
253
254 /* adapt to the duplex and speed settings of the phy */
255 info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
256 info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
257 }
258
259 /*
260 * Read and write a MII PHY register, routines used by MII Utilities
261 *
262 * FIXME: These routines are expected to return 0 on success, but mii_send
263 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
264 * no PHY connected...
265 * For now always return 0.
266 * FIXME: These routines only work after calling eth_init() at least once!
267 * Otherwise they hang in mii_send() !!! Sorry!
268 */
269
mcffec_miiphy_read(struct mii_dev * bus,int addr,int devad,int reg)270 int mcffec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
271 {
272 short rdreg; /* register working value */
273
274 #ifdef MII_DEBUG
275 printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
276 #endif
277 rdreg = mii_send(mk_mii_read(addr, reg));
278
279 #ifdef MII_DEBUG
280 printf("0x%04x\n", rdreg);
281 #endif
282
283 return rdreg;
284 }
285
mcffec_miiphy_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)286 int mcffec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
287 u16 value)
288 {
289 #ifdef MII_DEBUG
290 printf("miiphy_write(0x%x) @ 0x%x = 0x%04x\n", reg, addr, value);
291 #endif
292
293 mii_send(mk_mii_write(addr, reg, value));
294
295 return 0;
296 }
297
298 #endif /* CONFIG_CMD_NET */
299