1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
4 *
5 * This driver for AMD PCnet network controllers is derived from the
6 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
7 */
8
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <dm.h>
12 #include <log.h>
13 #include <malloc.h>
14 #include <memalign.h>
15 #include <net.h>
16 #include <netdev.h>
17 #include <asm/cache.h>
18 #include <asm/io.h>
19 #include <pci.h>
20 #include <linux/delay.h>
21
22 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
23
24 #define PCNET_DEBUG1(fmt,args...) \
25 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
26 #define PCNET_DEBUG2(fmt,args...) \
27 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
28
29 /*
30 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
31 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
32 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
33 */
34 #define PCNET_LOG_TX_BUFFERS 0
35 #define PCNET_LOG_RX_BUFFERS 2
36
37 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
38 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
39
40 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
41 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
42
43 #define PKT_BUF_SZ 1544
44
45 /* The PCNET Rx and Tx ring descriptors. */
46 struct pcnet_rx_head {
47 u32 base;
48 s16 buf_length;
49 s16 status;
50 u32 msg_length;
51 u32 reserved;
52 };
53
54 struct pcnet_tx_head {
55 u32 base;
56 s16 length;
57 s16 status;
58 u32 misc;
59 u32 reserved;
60 };
61
62 /* The PCNET 32-Bit initialization block, described in databook. */
63 struct pcnet_init_block {
64 u16 mode;
65 u16 tlen_rlen;
66 u8 phys_addr[6];
67 u16 reserved;
68 u32 filter[2];
69 /* Receive and transmit ring base, along with extra bits. */
70 u32 rx_ring;
71 u32 tx_ring;
72 u32 reserved2;
73 };
74
75 struct pcnet_uncached_priv {
76 struct pcnet_rx_head rx_ring[RX_RING_SIZE];
77 struct pcnet_tx_head tx_ring[TX_RING_SIZE];
78 struct pcnet_init_block init_block;
79 } __aligned(ARCH_DMA_MINALIGN);
80
81 struct pcnet_priv {
82 struct pcnet_uncached_priv ucp;
83 /* Receive Buffer space */
84 unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
85 struct pcnet_uncached_priv *uc;
86 struct udevice *dev;
87 const char *name;
88 void __iomem *iobase;
89 u8 *enetaddr;
90 u16 status;
91 int cur_rx;
92 int cur_tx;
93 };
94
95 /* Offsets from base I/O address for WIO mode */
96 #define PCNET_RDP 0x10
97 #define PCNET_RAP 0x12
98 #define PCNET_RESET 0x14
99 #define PCNET_BDP 0x16
100
pcnet_read_csr(struct pcnet_priv * lp,int index)101 static u16 pcnet_read_csr(struct pcnet_priv *lp, int index)
102 {
103 writew(index, lp->iobase + PCNET_RAP);
104 return readw(lp->iobase + PCNET_RDP);
105 }
106
pcnet_write_csr(struct pcnet_priv * lp,int index,u16 val)107 static void pcnet_write_csr(struct pcnet_priv *lp, int index, u16 val)
108 {
109 writew(index, lp->iobase + PCNET_RAP);
110 writew(val, lp->iobase + PCNET_RDP);
111 }
112
pcnet_read_bcr(struct pcnet_priv * lp,int index)113 static u16 pcnet_read_bcr(struct pcnet_priv *lp, int index)
114 {
115 writew(index, lp->iobase + PCNET_RAP);
116 return readw(lp->iobase + PCNET_BDP);
117 }
118
pcnet_write_bcr(struct pcnet_priv * lp,int index,u16 val)119 static void pcnet_write_bcr(struct pcnet_priv *lp, int index, u16 val)
120 {
121 writew(index, lp->iobase + PCNET_RAP);
122 writew(val, lp->iobase + PCNET_BDP);
123 }
124
pcnet_reset(struct pcnet_priv * lp)125 static void pcnet_reset(struct pcnet_priv *lp)
126 {
127 readw(lp->iobase + PCNET_RESET);
128 }
129
pcnet_check(struct pcnet_priv * lp)130 static int pcnet_check(struct pcnet_priv *lp)
131 {
132 writew(88, lp->iobase + PCNET_RAP);
133 return readw(lp->iobase + PCNET_RAP) == 88;
134 }
135
pcnet_virt_to_mem(struct pcnet_priv * lp,void * addr)136 static inline pci_addr_t pcnet_virt_to_mem(struct pcnet_priv *lp, void *addr)
137 {
138 void *virt_addr = addr;
139
140 return dm_pci_virt_to_mem(lp->dev, virt_addr);
141 }
142
143 static struct pci_device_id supported[] = {
144 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE) },
145 {}
146 };
147
pcnet_probe_common(struct pcnet_priv * lp)148 static int pcnet_probe_common(struct pcnet_priv *lp)
149 {
150 int chip_version;
151 char *chipname;
152 int i;
153
154 /* Reset the PCnet controller */
155 pcnet_reset(lp);
156
157 /* Check if register access is working */
158 if (pcnet_read_csr(lp, 0) != 4 || !pcnet_check(lp)) {
159 printf("%s: CSR register access check failed\n", lp->name);
160 return -1;
161 }
162
163 /* Identify the chip */
164 chip_version = pcnet_read_csr(lp, 88) | (pcnet_read_csr(lp, 89) << 16);
165 if ((chip_version & 0xfff) != 0x003)
166 return -1;
167 chip_version = (chip_version >> 12) & 0xffff;
168 switch (chip_version) {
169 case 0x2621:
170 chipname = "PCnet/PCI II 79C970A"; /* PCI */
171 break;
172 case 0x2625:
173 chipname = "PCnet/FAST III 79C973"; /* PCI */
174 break;
175 case 0x2627:
176 chipname = "PCnet/FAST III 79C975"; /* PCI */
177 break;
178 default:
179 printf("%s: PCnet version %#x not supported\n",
180 lp->name, chip_version);
181 return -1;
182 }
183
184 PCNET_DEBUG1("AMD %s\n", chipname);
185
186 /*
187 * In most chips, after a chip reset, the ethernet address is read from
188 * the station address PROM at the base address and programmed into the
189 * "Physical Address Registers" CSR12-14.
190 */
191 for (i = 0; i < 3; i++) {
192 unsigned int val;
193
194 val = pcnet_read_csr(lp, i + 12) & 0x0ffff;
195 /* There may be endianness issues here. */
196 lp->enetaddr[2 * i] = val & 0x0ff;
197 lp->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
198 }
199
200 return 0;
201 }
202
pcnet_init_common(struct pcnet_priv * lp)203 static int pcnet_init_common(struct pcnet_priv *lp)
204 {
205 struct pcnet_uncached_priv *uc;
206 int i, val;
207 unsigned long addr;
208
209 PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
210
211 /* Switch pcnet to 32bit mode */
212 pcnet_write_bcr(lp, 20, 2);
213
214 /* Set/reset autoselect bit */
215 val = pcnet_read_bcr(lp, 2) & ~2;
216 val |= 2;
217 pcnet_write_bcr(lp, 2, val);
218
219 /* Enable auto negotiate, setup, disable fd */
220 val = pcnet_read_bcr(lp, 32) & ~0x98;
221 val |= 0x20;
222 pcnet_write_bcr(lp, 32, val);
223
224 /*
225 * Enable NOUFLO on supported controllers, with the transmit
226 * start point set to the full packet. This will cause entire
227 * packets to be buffered by the ethernet controller before
228 * transmission, eliminating underflows which are common on
229 * slower devices. Controllers which do not support NOUFLO will
230 * simply be left with a larger transmit FIFO threshold.
231 */
232 val = pcnet_read_bcr(lp, 18);
233 val |= 1 << 11;
234 pcnet_write_bcr(lp, 18, val);
235 val = pcnet_read_csr(lp, 80);
236 val |= 0x3 << 10;
237 pcnet_write_csr(lp, 80, val);
238
239 uc = lp->uc;
240
241 uc->init_block.mode = cpu_to_le16(0x0000);
242 uc->init_block.filter[0] = 0x00000000;
243 uc->init_block.filter[1] = 0x00000000;
244
245 /*
246 * Initialize the Rx ring.
247 */
248 lp->cur_rx = 0;
249 for (i = 0; i < RX_RING_SIZE; i++) {
250 addr = pcnet_virt_to_mem(lp, lp->rx_buf[i]);
251 uc->rx_ring[i].base = cpu_to_le32(addr);
252 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
253 uc->rx_ring[i].status = cpu_to_le16(0x8000);
254 PCNET_DEBUG1
255 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
256 uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
257 uc->rx_ring[i].status);
258 }
259
260 /*
261 * Initialize the Tx ring. The Tx buffer address is filled in as
262 * needed, but we do need to clear the upper ownership bit.
263 */
264 lp->cur_tx = 0;
265 for (i = 0; i < TX_RING_SIZE; i++) {
266 uc->tx_ring[i].base = 0;
267 uc->tx_ring[i].status = 0;
268 }
269
270 /*
271 * Setup Init Block.
272 */
273 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
274
275 for (i = 0; i < 6; i++) {
276 lp->uc->init_block.phys_addr[i] = lp->enetaddr[i];
277 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
278 }
279
280 uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
281 RX_RING_LEN_BITS);
282 addr = pcnet_virt_to_mem(lp, uc->rx_ring);
283 uc->init_block.rx_ring = cpu_to_le32(addr);
284 addr = pcnet_virt_to_mem(lp, uc->tx_ring);
285 uc->init_block.tx_ring = cpu_to_le32(addr);
286
287 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
288 uc->init_block.tlen_rlen,
289 uc->init_block.rx_ring, uc->init_block.tx_ring);
290
291 /*
292 * Tell the controller where the Init Block is located.
293 */
294 barrier();
295 addr = pcnet_virt_to_mem(lp, &lp->uc->init_block);
296 pcnet_write_csr(lp, 1, addr & 0xffff);
297 pcnet_write_csr(lp, 2, (addr >> 16) & 0xffff);
298
299 pcnet_write_csr(lp, 4, 0x0915);
300 pcnet_write_csr(lp, 0, 0x0001); /* start */
301
302 /* Wait for Init Done bit */
303 for (i = 10000; i > 0; i--) {
304 if (pcnet_read_csr(lp, 0) & 0x0100)
305 break;
306 udelay(10);
307 }
308 if (i <= 0) {
309 printf("%s: TIMEOUT: controller init failed\n", lp->name);
310 pcnet_reset(lp);
311 return -1;
312 }
313
314 /*
315 * Finally start network controller operation.
316 */
317 pcnet_write_csr(lp, 0, 0x0002);
318
319 return 0;
320 }
321
pcnet_send_common(struct pcnet_priv * lp,void * packet,int pkt_len)322 static int pcnet_send_common(struct pcnet_priv *lp, void *packet, int pkt_len)
323 {
324 int i, status;
325 u32 addr;
326 struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
327
328 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
329 packet);
330
331 flush_dcache_range((unsigned long)packet,
332 (unsigned long)packet + pkt_len);
333
334 /* Wait for completion by testing the OWN bit */
335 for (i = 1000; i > 0; i--) {
336 status = readw(&entry->status);
337 if ((status & 0x8000) == 0)
338 break;
339 udelay(100);
340 PCNET_DEBUG2(".");
341 }
342 if (i <= 0) {
343 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
344 lp->name, lp->cur_tx, status);
345 pkt_len = 0;
346 goto failure;
347 }
348
349 /*
350 * Setup Tx ring. Caution: the write order is important here,
351 * set the status with the "ownership" bits last.
352 */
353 addr = pcnet_virt_to_mem(lp, packet);
354 writew(-pkt_len, &entry->length);
355 writel(0, &entry->misc);
356 writel(addr, &entry->base);
357 writew(0x8300, &entry->status);
358
359 /* Trigger an immediate send poll. */
360 pcnet_write_csr(lp, 0, 0x0008);
361
362 failure:
363 if (++lp->cur_tx >= TX_RING_SIZE)
364 lp->cur_tx = 0;
365
366 PCNET_DEBUG2("done\n");
367 return pkt_len;
368 }
369
pcnet_recv_common(struct pcnet_priv * lp,unsigned char ** bufp)370 static int pcnet_recv_common(struct pcnet_priv *lp, unsigned char **bufp)
371 {
372 struct pcnet_rx_head *entry;
373 unsigned char *buf;
374 int pkt_len = 0;
375 u16 err_status;
376
377 entry = &lp->uc->rx_ring[lp->cur_rx];
378 /*
379 * If we own the next entry, it's a new packet. Send it up.
380 */
381 lp->status = readw(&entry->status);
382 if ((lp->status & 0x8000) != 0)
383 return 0;
384 err_status = lp->status >> 8;
385
386 if (err_status != 0x03) { /* There was an error. */
387 printf("%s: Rx%d", lp->name, lp->cur_rx);
388 PCNET_DEBUG1(" (status=0x%x)", err_status);
389 if (err_status & 0x20)
390 printf(" Frame");
391 if (err_status & 0x10)
392 printf(" Overflow");
393 if (err_status & 0x08)
394 printf(" CRC");
395 if (err_status & 0x04)
396 printf(" Fifo");
397 printf(" Error\n");
398 lp->status &= 0x03ff;
399 return 0;
400 }
401
402 pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
403 if (pkt_len < 60) {
404 printf("%s: Rx%d: invalid packet length %d\n",
405 lp->name, lp->cur_rx, pkt_len);
406 return 0;
407 }
408
409 *bufp = lp->rx_buf[lp->cur_rx];
410 invalidate_dcache_range((unsigned long)*bufp,
411 (unsigned long)*bufp + pkt_len);
412
413 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
414 lp->cur_rx, pkt_len, buf);
415
416 return pkt_len;
417 }
418
pcnet_free_pkt_common(struct pcnet_priv * lp,unsigned int len)419 static void pcnet_free_pkt_common(struct pcnet_priv *lp, unsigned int len)
420 {
421 struct pcnet_rx_head *entry;
422
423 entry = &lp->uc->rx_ring[lp->cur_rx];
424
425 lp->status |= 0x8000;
426 writew(lp->status, &entry->status);
427
428 if (++lp->cur_rx >= RX_RING_SIZE)
429 lp->cur_rx = 0;
430 }
431
pcnet_halt_common(struct pcnet_priv * lp)432 static void pcnet_halt_common(struct pcnet_priv *lp)
433 {
434 int i;
435
436 PCNET_DEBUG1("%s: %s...\n", lp->name, __func__);
437
438 /* Reset the PCnet controller */
439 pcnet_reset(lp);
440
441 /* Wait for Stop bit */
442 for (i = 1000; i > 0; i--) {
443 if (pcnet_read_csr(lp, 0) & 0x4)
444 break;
445 udelay(10);
446 }
447 if (i <= 0)
448 printf("%s: TIMEOUT: controller reset failed\n", lp->name);
449 }
450
pcnet_start(struct udevice * dev)451 static int pcnet_start(struct udevice *dev)
452 {
453 struct eth_pdata *plat = dev_get_plat(dev);
454 struct pcnet_priv *priv = dev_get_priv(dev);
455
456 memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
457
458 return pcnet_init_common(priv);
459 }
460
pcnet_stop(struct udevice * dev)461 static void pcnet_stop(struct udevice *dev)
462 {
463 struct pcnet_priv *priv = dev_get_priv(dev);
464
465 pcnet_halt_common(priv);
466 }
467
pcnet_send(struct udevice * dev,void * packet,int length)468 static int pcnet_send(struct udevice *dev, void *packet, int length)
469 {
470 struct pcnet_priv *priv = dev_get_priv(dev);
471 int ret;
472
473 ret = pcnet_send_common(priv, packet, length);
474
475 return ret ? 0 : -ETIMEDOUT;
476 }
477
pcnet_recv(struct udevice * dev,int flags,uchar ** packetp)478 static int pcnet_recv(struct udevice *dev, int flags, uchar **packetp)
479 {
480 struct pcnet_priv *priv = dev_get_priv(dev);
481
482 return pcnet_recv_common(priv, packetp);
483 }
484
pcnet_free_pkt(struct udevice * dev,uchar * packet,int length)485 static int pcnet_free_pkt(struct udevice *dev, uchar *packet, int length)
486 {
487 struct pcnet_priv *priv = dev_get_priv(dev);
488
489 pcnet_free_pkt_common(priv, length);
490
491 return 0;
492 }
493
pcnet_bind(struct udevice * dev)494 static int pcnet_bind(struct udevice *dev)
495 {
496 static int card_number;
497 char name[16];
498
499 sprintf(name, "pcnet#%u", card_number++);
500
501 return device_set_name(dev, name);
502 }
503
pcnet_probe(struct udevice * dev)504 static int pcnet_probe(struct udevice *dev)
505 {
506 struct eth_pdata *plat = dev_get_plat(dev);
507 struct pcnet_priv *lp = dev_get_priv(dev);
508 u16 command, status;
509 u32 iobase;
510 int ret;
511
512 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
513 iobase &= ~0xf;
514
515 lp->uc = map_physmem((phys_addr_t)&lp->ucp,
516 sizeof(lp->ucp), MAP_NOCACHE);
517 lp->dev = dev;
518 lp->name = dev->name;
519 lp->enetaddr = plat->enetaddr;
520 lp->iobase = (void *)dm_pci_mem_to_phys(dev, iobase);
521
522 flush_dcache_range((unsigned long)lp,
523 (unsigned long)lp + sizeof(*lp));
524
525 command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
526 dm_pci_write_config16(dev, PCI_COMMAND, command);
527 dm_pci_read_config16(dev, PCI_COMMAND, &status);
528 if ((status & command) != command) {
529 printf("%s: Couldn't enable IO access or Bus Mastering\n",
530 lp->name);
531 return -EINVAL;
532 }
533
534 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
535
536 ret = pcnet_probe_common(lp);
537 if (ret)
538 return ret;
539
540 return 0;
541 }
542
543 static const struct eth_ops pcnet_ops = {
544 .start = pcnet_start,
545 .send = pcnet_send,
546 .recv = pcnet_recv,
547 .stop = pcnet_stop,
548 .free_pkt = pcnet_free_pkt,
549 };
550
551 U_BOOT_DRIVER(eth_pcnet) = {
552 .name = "eth_pcnet",
553 .id = UCLASS_ETH,
554 .bind = pcnet_bind,
555 .probe = pcnet_probe,
556 .ops = &pcnet_ops,
557 .priv_auto = sizeof(struct pcnet_priv),
558 .plat_auto = sizeof(struct eth_pdata),
559 .flags = DM_UC_FLAG_ALLOC_PRIV_DMA,
560 };
561
562 U_BOOT_PCI_DEVICE(eth_pcnet, supported);
563