1 // SPDX-License-Identifier: GPL-2.0+
2 /**
3 * Driver for Analog Devices Industrial Ethernet PHYs
4 *
5 * Copyright 2019 Analog Devices Inc.
6 * Copyright 2022 Variscite Ltd.
7 * Copyright 2022 Josua Mayer <josua@solid-run.com>
8 */
9 #include <common.h>
10 #include <phy.h>
11 #include <linux/bitops.h>
12 #include <linux/bitfield.h>
13
14 #define PHY_ID_ADIN1300 0x0283bc30
15 #define ADIN1300_EXT_REG_PTR 0x10
16 #define ADIN1300_EXT_REG_DATA 0x11
17
18 #define ADIN1300_GE_CLK_CFG_REG 0xff1f
19 #define ADIN1300_GE_CLK_CFG_MASK GENMASK(5, 0)
20 #define ADIN1300_GE_CLK_CFG_RCVR_125 BIT(5)
21 #define ADIN1300_GE_CLK_CFG_FREE_125 BIT(4)
22 #define ADIN1300_GE_CLK_CFG_REF_EN BIT(3)
23 #define ADIN1300_GE_CLK_CFG_HRT_RCVR BIT(2)
24 #define ADIN1300_GE_CLK_CFG_HRT_FREE BIT(1)
25 #define ADIN1300_GE_CLK_CFG_25 BIT(0)
26
27 #define ADIN1300_GE_RGMII_CFG 0xff23
28 #define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)
29 #define ADIN1300_GE_RGMII_RX_SEL(x) \
30 FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x)
31 #define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3)
32 #define ADIN1300_GE_RGMII_GTX_SEL(x) \
33 FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x)
34 #define ADIN1300_GE_RGMII_RXID_EN BIT(2)
35 #define ADIN1300_GE_RGMII_TXID_EN BIT(1)
36 #define ADIN1300_GE_RGMII_EN BIT(0)
37
38 /* RGMII internal delay settings for rx and tx for ADIN1300 */
39 #define ADIN1300_RGMII_1_60_NS 0x0001
40 #define ADIN1300_RGMII_1_80_NS 0x0002
41 #define ADIN1300_RGMII_2_00_NS 0x0000
42 #define ADIN1300_RGMII_2_20_NS 0x0006
43 #define ADIN1300_RGMII_2_40_NS 0x0007
44
45 /**
46 * struct adin_cfg_reg_map - map a config value to aregister value
47 * @cfg value in device configuration
48 * @reg value in the register
49 */
50 struct adin_cfg_reg_map {
51 int cfg;
52 int reg;
53 };
54
55 static const struct adin_cfg_reg_map adin_rgmii_delays[] = {
56 { 1600, ADIN1300_RGMII_1_60_NS },
57 { 1800, ADIN1300_RGMII_1_80_NS },
58 { 2000, ADIN1300_RGMII_2_00_NS },
59 { 2200, ADIN1300_RGMII_2_20_NS },
60 { 2400, ADIN1300_RGMII_2_40_NS },
61 { },
62 };
63
adin_lookup_reg_value(const struct adin_cfg_reg_map * tbl,int cfg)64 static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg)
65 {
66 size_t i;
67
68 for (i = 0; tbl[i].cfg; i++) {
69 if (tbl[i].cfg == cfg)
70 return tbl[i].reg;
71 }
72
73 return -EINVAL;
74 }
75
adin_get_reg_value(struct phy_device * phydev,const char * prop_name,const struct adin_cfg_reg_map * tbl,u32 dflt)76 static u32 adin_get_reg_value(struct phy_device *phydev,
77 const char *prop_name,
78 const struct adin_cfg_reg_map *tbl,
79 u32 dflt)
80 {
81 u32 val;
82 int rc;
83
84 ofnode node = phy_get_ofnode(phydev);
85 if (!ofnode_valid(node)) {
86 printf("%s: failed to get node\n", __func__);
87 return -EINVAL;
88 }
89
90 if (ofnode_read_u32(node, prop_name, &val)) {
91 printf("%s: failed to find %s, using default %d\n",
92 __func__, prop_name, dflt);
93 return dflt;
94 }
95
96 debug("%s: %s = '%d'\n", __func__, prop_name, val);
97
98 rc = adin_lookup_reg_value(tbl, val);
99 if (rc < 0) {
100 printf("%s: Unsupported value %u for %s using default (%u)\n",
101 __func__, val, prop_name, dflt);
102 return dflt;
103 }
104
105 return rc;
106 }
107
108 /**
109 * adin_get_phy_mode_override - Get phy-mode override for adin PHY
110 *
111 * The function gets phy-mode string from property 'adi,phy-mode-override'
112 * and return its index in phy_interface_strings table, or -1 in error case.
113 */
adin_get_phy_mode_override(struct phy_device * phydev)114 phy_interface_t adin_get_phy_mode_override(struct phy_device *phydev)
115 {
116 ofnode node = phy_get_ofnode(phydev);
117 const char *phy_mode_override;
118 const char *prop_phy_mode_override = "adi,phy-mode-override";
119 int i;
120
121 phy_mode_override = ofnode_read_string(node, prop_phy_mode_override);
122 if (!phy_mode_override)
123 return PHY_INTERFACE_MODE_NA;
124
125 debug("%s: %s = '%s'\n",
126 __func__, prop_phy_mode_override, phy_mode_override);
127
128 for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++)
129 if (!strcmp(phy_mode_override, phy_interface_strings[i]))
130 return (phy_interface_t) i;
131
132 printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode_override);
133
134 return PHY_INTERFACE_MODE_NA;
135 }
136
adin_ext_read(struct phy_device * phydev,const u32 regnum)137 static u16 adin_ext_read(struct phy_device *phydev, const u32 regnum)
138 {
139 u16 val;
140
141 phy_write(phydev, MDIO_DEVAD_NONE, ADIN1300_EXT_REG_PTR, regnum);
142 val = phy_read(phydev, MDIO_DEVAD_NONE, ADIN1300_EXT_REG_DATA);
143
144 debug("%s: adin@0x%x 0x%x=0x%x\n", __func__, phydev->addr, regnum, val);
145
146 return val;
147 }
148
adin_ext_write(struct phy_device * phydev,const u32 regnum,const u16 val)149 static int adin_ext_write(struct phy_device *phydev, const u32 regnum, const u16 val)
150 {
151 debug("%s: adin@0x%x 0x%x=0x%x\n", __func__, phydev->addr, regnum, val);
152
153 phy_write(phydev, MDIO_DEVAD_NONE, ADIN1300_EXT_REG_PTR, regnum);
154
155 return phy_write(phydev, MDIO_DEVAD_NONE, ADIN1300_EXT_REG_DATA, val);
156 }
157
adin_config_clk_out(struct phy_device * phydev)158 static int adin_config_clk_out(struct phy_device *phydev)
159 {
160 ofnode node = phy_get_ofnode(phydev);
161 const char *val = NULL;
162 u8 sel = 0;
163
164 val = ofnode_read_string(node, "adi,phy-output-clock");
165 if (!val) {
166 /* property not present, do not enable GP_CLK pin */
167 } else if (strcmp(val, "25mhz-reference") == 0) {
168 sel |= ADIN1300_GE_CLK_CFG_25;
169 } else if (strcmp(val, "125mhz-free-running") == 0) {
170 sel |= ADIN1300_GE_CLK_CFG_FREE_125;
171 } else if (strcmp(val, "adaptive-free-running") == 0) {
172 sel |= ADIN1300_GE_CLK_CFG_HRT_FREE;
173 } else {
174 pr_err("%s: invalid adi,phy-output-clock\n", __func__);
175 return -EINVAL;
176 }
177
178 if (ofnode_read_bool(node, "adi,phy-output-reference-clock"))
179 sel |= ADIN1300_GE_CLK_CFG_REF_EN;
180
181 return adin_ext_write(phydev, ADIN1300_GE_CLK_CFG_REG,
182 ADIN1300_GE_CLK_CFG_MASK & sel);
183 }
184
adin_config_rgmii_mode(struct phy_device * phydev)185 static int adin_config_rgmii_mode(struct phy_device *phydev)
186 {
187 u16 reg_val;
188 u32 val;
189 phy_interface_t phy_mode_override = adin_get_phy_mode_override(phydev);
190
191 if (phy_mode_override != PHY_INTERFACE_MODE_NA) {
192 phydev->interface = phy_mode_override;
193 }
194
195 reg_val = adin_ext_read(phydev, ADIN1300_GE_RGMII_CFG);
196
197 if (!phy_interface_is_rgmii(phydev)) {
198 /* Disable RGMII */
199 reg_val &= ~ADIN1300_GE_RGMII_EN;
200 return adin_ext_write(phydev, ADIN1300_GE_RGMII_CFG, reg_val);
201 }
202
203 /* Enable RGMII */
204 reg_val |= ADIN1300_GE_RGMII_EN;
205
206 /* Enable / Disable RGMII RX Delay */
207 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
208 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
209 reg_val |= ADIN1300_GE_RGMII_RXID_EN;
210
211 val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps",
212 adin_rgmii_delays,
213 ADIN1300_RGMII_2_00_NS);
214 reg_val &= ~ADIN1300_GE_RGMII_RX_MSK;
215 reg_val |= ADIN1300_GE_RGMII_RX_SEL(val);
216 } else {
217 reg_val &= ~ADIN1300_GE_RGMII_RXID_EN;
218 }
219
220 /* Enable / Disable RGMII RX Delay */
221 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
222 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
223 reg_val |= ADIN1300_GE_RGMII_TXID_EN;
224
225 val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps",
226 adin_rgmii_delays,
227 ADIN1300_RGMII_2_00_NS);
228 reg_val &= ~ADIN1300_GE_RGMII_GTX_MSK;
229 reg_val |= ADIN1300_GE_RGMII_GTX_SEL(val);
230 } else {
231 reg_val &= ~ADIN1300_GE_RGMII_TXID_EN;
232 }
233
234 return adin_ext_write(phydev, ADIN1300_GE_RGMII_CFG, reg_val);
235 }
236
adin1300_config(struct phy_device * phydev)237 static int adin1300_config(struct phy_device *phydev)
238 {
239 int ret;
240
241 printf("ADIN1300 PHY detected at addr %d\n", phydev->addr);
242
243 ret = adin_config_clk_out(phydev);
244 if (ret < 0)
245 return ret;
246
247 ret = adin_config_rgmii_mode(phydev);
248
249 if (ret < 0)
250 return ret;
251
252 return genphy_config(phydev);
253 }
254
255 U_BOOT_PHY_DRIVER(ADIN1300) = {
256 .name = "ADIN1300",
257 .uid = PHY_ID_ADIN1300,
258 .mask = 0xffffffff,
259 .features = PHY_GBIT_FEATURES,
260 .config = adin1300_config,
261 .startup = genphy_startup,
262 .shutdown = genphy_shutdown,
263 };
264