1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * TI PHY drivers
4 *
5 */
6
7 #include <common.h>
8 #include <phy.h>
9 #include <linux/compat.h>
10 #include <malloc.h>
11
12 #include <dm.h>
13 #include <dt-bindings/net/ti-dp83869.h>
14
15 /* TI DP83869 */
16 #define DP83869_DEVADDR 0x1f
17
18 #define MII_DP83869_PHYCTRL 0x10
19 #define MII_DP83869_MICR 0x12
20 #define MII_DP83869_CFG2 0x14
21 #define MII_DP83869_BISCR 0x16
22 #define DP83869_CTRL 0x1f
23 #define DP83869_CFG4 0x1e
24
25 /* Extended Registers */
26 #define DP83869_GEN_CFG3 0x0031
27 #define DP83869_RGMIICTL 0x0032
28 #define DP83869_STRAP_STS1 0x006E
29 #define DP83869_RGMIIDCTL 0x0086
30 #define DP83869_IO_MUX_CFG 0x0170
31 #define DP83869_OP_MODE 0x01df
32 #define DP83869_FX_CTRL 0x0c00
33
34 #define DP83869_SW_RESET BIT(15)
35 #define DP83869_SW_RESTART BIT(14)
36
37 /* MICR Interrupt bits */
38 #define MII_DP83869_MICR_AN_ERR_INT_EN BIT(15)
39 #define MII_DP83869_MICR_SPEED_CHNG_INT_EN BIT(14)
40 #define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
41 #define MII_DP83869_MICR_PAGE_RXD_INT_EN BIT(12)
42 #define MII_DP83869_MICR_AUTONEG_COMP_INT_EN BIT(11)
43 #define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN BIT(10)
44 #define MII_DP83869_MICR_FALSE_CARRIER_INT_EN BIT(8)
45 #define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
46 #define MII_DP83869_MICR_WOL_INT_EN BIT(3)
47 #define MII_DP83869_MICR_XGMII_ERR_INT_EN BIT(2)
48 #define MII_DP83869_MICR_POL_CHNG_INT_EN BIT(1)
49 #define MII_DP83869_MICR_JABBER_INT_EN BIT(0)
50
51 #define MII_DP83869_BMCR_DEFAULT (BMCR_ANENABLE | \
52 BMCR_FULLDPLX | \
53 BMCR_SPEED1000)
54
55 /* This is the same bit mask as the BMCR so re-use the BMCR default */
56 #define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT
57
58 /* CFG1 bits */
59 #define DP83869_CFG1_DEFAULT (ADVERTISE_1000HALF | \
60 ADVERTISE_1000FULL | \
61 CTL1000_AS_MASTER)
62
63 /* RGMIICTL bits */
64 #define DP83869_RGMII_TX_CLK_DELAY_EN BIT(1)
65 #define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0)
66
67 /* STRAP_STS1 bits */
68 #define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0)
69 #define DP83869_STRAP_STS1_RESERVED BIT(11)
70 #define DP83869_STRAP_MIRROR_ENABLED BIT(12)
71
72 /* PHY CTRL bits */
73 #define DP83869_PHYCR_RX_FIFO_DEPTH_SHIFT 12
74 #define DP83869_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
75 #define DP83869_PHYCR_TX_FIFO_DEPTH_SHIFT 14
76 #define DP83869_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
77 #define DP83869_PHYCR_RESERVED_MASK BIT(11)
78 #define DP83869_PHYCR_MDI_CROSSOVER_SHIFT 5
79 #define DP83869_PHYCR_MDI_CROSSOVER_MDIX 2
80 #define DP83869_PHY_CTRL_DEFAULT 0x48
81
82 /* RGMIIDCTL bits */
83 #define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4
84 #define DP83869_CLK_DELAY_DEF 7
85
86 /* CFG2 bits */
87 #define MII_DP83869_CFG2_SPEEDOPT_10EN 0x0040
88 #define MII_DP83869_CFG2_SGMII_AUTONEGEN 0x0080
89 #define MII_DP83869_CFG2_SPEEDOPT_ENH 0x0100
90 #define MII_DP83869_CFG2_SPEEDOPT_CNT 0x0800
91 #define MII_DP83869_CFG2_SPEEDOPT_INTLOW 0x2000
92 #define MII_DP83869_CFG2_MASK 0x003F
93
94 /* User setting - can be taken from DTS */
95 #define DEFAULT_FIFO_DEPTH DP83869_PHYCR_FIFO_DEPTH_4_B_NIB
96
97 /* IO_MUX_CFG bits */
98 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
99
100 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
101 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
102 #define DP83869_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
103 #define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
104 #define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK \
105 GENMASK(0x1f, DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT)
106
107 /* CFG3 bits */
108 #define DP83869_CFG3_PORT_MIRROR_EN BIT(0)
109
110 /* OP MODE bits */
111 #define DP83869_OP_MODE_MII BIT(5)
112 #define DP83869_SGMII_RGMII_BRIDGE BIT(6)
113
114 enum {
115 DP83869_PORT_MIRRORING_KEEP,
116 DP83869_PORT_MIRRORING_EN,
117 DP83869_PORT_MIRRORING_DIS,
118 };
119
120 struct dp83869_private {
121 int tx_fifo_depth;
122 int rx_fifo_depth;
123 s32 rx_int_delay;
124 s32 tx_int_delay;
125 int io_impedance;
126 int port_mirroring;
127 bool set_clk_output;
128 int clk_output_sel;
129 int mode;
130 };
131
dp83869_readext(struct phy_device * phydev,int addr,int devad,int reg)132 static int dp83869_readext(struct phy_device *phydev, int addr, int devad, int reg)
133 {
134 return phy_read_mmd(phydev, devad, reg);
135 }
136
dp83869_writeext(struct phy_device * phydev,int addr,int devad,int reg,u16 val)137 static int dp83869_writeext(struct phy_device *phydev, int addr, int devad, int reg, u16 val)
138 {
139 return phy_write_mmd(phydev, devad, reg, val);
140 }
141
dp83869_config_port_mirroring(struct phy_device * phydev)142 static int dp83869_config_port_mirroring(struct phy_device *phydev)
143 {
144 struct dp83869_private *dp83869 =
145 (struct dp83869_private *)phydev->priv;
146 u16 val;
147
148 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_CFG4);
149
150 if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN)
151 val |= DP83869_CFG3_PORT_MIRROR_EN;
152 else
153 val &= ~DP83869_CFG3_PORT_MIRROR_EN;
154
155 phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_CFG4, val);
156
157 return 0;
158 }
159
160 static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500,
161 1750, 2000, 2250, 2500, 2750, 3000,
162 3250, 3500, 3750, 4000};
163
dp83869_set_strapped_mode(struct phy_device * phydev)164 static int dp83869_set_strapped_mode(struct phy_device *phydev)
165 {
166 struct dp83869_private *dp83869 = phydev->priv;
167 int val;
168
169 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
170 if (val < 0)
171 return val;
172
173 dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK;
174
175 return 0;
176 }
177
178 /**
179 * dp83869_data_init - Convenience function for setting PHY specific data
180 *
181 * @phydev: the phy_device struct
182 */
dp83869_of_init(struct phy_device * phydev)183 static int dp83869_of_init(struct phy_device *phydev)
184 {
185 struct dp83869_private * const dp83869 = phydev->priv;
186 const int delay_entries = ARRAY_SIZE(dp83869_internal_delay);
187 int ret;
188 ofnode node;
189
190 node = phy_get_ofnode(phydev);
191 if (!ofnode_valid(node))
192 return -EINVAL;
193
194 dp83869->io_impedance = -EINVAL;
195
196 /* Optional configuration, set to default if required */
197 dp83869->clk_output_sel = ofnode_read_u32_default(node, "ti,clk-output-sel",
198 DP83869_CLK_O_SEL_CHN_A_RCLK);
199
200 if (dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK &&
201 dp83869->clk_output_sel != DP83869_CLK_O_SEL_OFF)
202 dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK;
203
204 /* If operation mode is not set use setting from straps */
205 ret = ofnode_read_s32(node, "ti,op-mode", &dp83869->mode);
206 if (ret == 0) {
207 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
208 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
209 return -EINVAL;
210 } else {
211 ret = dp83869_set_strapped_mode(phydev);
212 if (ret)
213 return ret;
214 }
215
216 if (ofnode_read_bool(node, "ti,max-output-impedance"))
217 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX;
218 else if (ofnode_read_bool(node, "ti,min-output-impedance"))
219 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN;
220
221 if (ofnode_read_bool(node, "enet-phy-lane-swap")) {
222 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
223 } else {
224 ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
225
226 if (ret < 0)
227 return ret;
228
229 if (ret & DP83869_STRAP_MIRROR_ENABLED)
230 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
231 else
232 dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS;
233 }
234
235 dp83869->rx_fifo_depth = ofnode_read_s32_default(node, "rx-fifo-depth",
236 DP83869_PHYCR_FIFO_DEPTH_4_B_NIB);
237
238 dp83869->tx_fifo_depth = ofnode_read_s32_default(node, "tx-fifo-depth",
239 DP83869_PHYCR_FIFO_DEPTH_4_B_NIB);
240
241 /* RX delay *must* be specified if internal delay of RX is used. */
242 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
243 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
244 dp83869->rx_int_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps",
245 DP83869_CLK_DELAY_DEF);
246 if (dp83869->rx_int_delay > delay_entries) {
247 dp83869->rx_int_delay = DP83869_CLK_DELAY_DEF;
248 pr_debug("rx-internal-delay-ps not set/invalid, default to %ups\n",
249 dp83869_internal_delay[dp83869->rx_int_delay]);
250 }
251
252 dp83869->rx_int_delay = dp83869_internal_delay[dp83869->rx_int_delay];
253 }
254
255 /* TX delay *must* be specified if internal delay of RX is used. */
256 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
257 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
258 dp83869->tx_int_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps",
259 DP83869_CLK_DELAY_DEF);
260 if (dp83869->tx_int_delay > delay_entries) {
261 dp83869->tx_int_delay = DP83869_CLK_DELAY_DEF;
262 pr_debug("tx-internal-delay-ps not set/invalid, default to %ups\n",
263 dp83869_internal_delay[dp83869->tx_int_delay]);
264 }
265
266 dp83869->tx_int_delay = dp83869_internal_delay[dp83869->tx_int_delay];
267 }
268
269 return 0;
270 }
271
dp83869_configure_rgmii(struct phy_device * phydev,struct dp83869_private * dp83869)272 static int dp83869_configure_rgmii(struct phy_device *phydev,
273 struct dp83869_private *dp83869)
274 {
275 int ret = 0, val;
276
277 if (phy_interface_is_rgmii(phydev)) {
278 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL);
279 if (val < 0)
280 return val;
281
282 val &= ~(DP83869_PHYCR_TX_FIFO_DEPTH_MASK | DP83869_PHYCR_RX_FIFO_DEPTH_MASK);
283 val |= (dp83869->tx_fifo_depth << DP83869_PHYCR_TX_FIFO_DEPTH_SHIFT);
284 val |= (dp83869->rx_fifo_depth << DP83869_PHYCR_RX_FIFO_DEPTH_SHIFT);
285
286 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL, val);
287 if (ret)
288 return ret;
289 }
290
291 if (dp83869->io_impedance >= 0) {
292 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG);
293
294 val &= ~DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
295 val |= dp83869->io_impedance & DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
296
297 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG, val);
298
299 if (ret)
300 return ret;
301 }
302
303 return ret;
304 }
305
dp83869_configure_mode(struct phy_device * phydev,struct dp83869_private * dp83869)306 static int dp83869_configure_mode(struct phy_device *phydev,
307 struct dp83869_private *dp83869)
308 {
309 int phy_ctrl_val;
310 int ret, val;
311
312 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
313 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
314 return -EINVAL;
315
316 /* Below init sequence for each operational mode is defined in
317 * section 9.4.8 of the datasheet.
318 */
319 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
320 dp83869->mode);
321 if (ret)
322 return ret;
323
324 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, MII_DP83869_BMCR_DEFAULT);
325 if (ret)
326 return ret;
327
328 phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_PHYCR_RX_FIFO_DEPTH_SHIFT |
329 dp83869->tx_fifo_depth << DP83869_PHYCR_TX_FIFO_DEPTH_SHIFT |
330 DP83869_PHY_CTRL_DEFAULT);
331
332 switch (dp83869->mode) {
333 case DP83869_RGMII_COPPER_ETHERNET:
334 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL,
335 phy_ctrl_val);
336 if (ret)
337 return ret;
338
339 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, DP83869_CFG1_DEFAULT);
340 if (ret)
341 return ret;
342
343 ret = dp83869_configure_rgmii(phydev, dp83869);
344 if (ret)
345 return ret;
346 break;
347 case DP83869_RGMII_SGMII_BRIDGE:
348 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE);
349
350 val |= DP83869_SGMII_RGMII_BRIDGE;
351
352 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, val);
353
354 if (ret)
355 return ret;
356
357 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
358 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
359 if (ret)
360 return ret;
361
362 break;
363 case DP83869_1000M_MEDIA_CONVERT:
364 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL,
365 phy_ctrl_val);
366 if (ret)
367 return ret;
368
369 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
370 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
371 if (ret)
372 return ret;
373 break;
374 case DP83869_100M_MEDIA_CONVERT:
375 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL,
376 phy_ctrl_val);
377 if (ret)
378 return ret;
379 break;
380 case DP83869_SGMII_COPPER_ETHERNET:
381 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL,
382 phy_ctrl_val);
383 if (ret)
384 return ret;
385
386 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, DP83869_CFG1_DEFAULT);
387 if (ret)
388 return ret;
389
390 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
391 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
392 if (ret)
393 return ret;
394
395 break;
396 default:
397 return -EINVAL;
398 }
399
400 return ret;
401 }
402
dp83869_config(struct phy_device * phydev)403 static int dp83869_config(struct phy_device *phydev)
404 {
405 struct dp83869_private *dp83869;
406 unsigned int val;
407 int ret;
408
409 dp83869 = (struct dp83869_private *)phydev->priv;
410
411 ret = dp83869_of_init(phydev);
412 if (ret)
413 return ret;
414
415 ret = dp83869_configure_mode(phydev, dp83869);
416 if (ret)
417 return ret;
418
419 if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP)
420 dp83869_config_port_mirroring(phydev);
421
422 /* Clock output selection if muxing property is set */
423 if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) {
424 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG);
425
426 val &= ~DP83869_IO_MUX_CFG_CLK_O_SEL_MASK;
427 val |= dp83869->clk_output_sel << DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT;
428
429 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG, val);
430
431 if (ret)
432 return ret;
433 }
434
435 if (phy_interface_is_rgmii(phydev)) {
436 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL,
437 dp83869->rx_int_delay |
438 dp83869->tx_int_delay << DP83869_RGMII_TX_CLK_DELAY_SHIFT);
439 if (ret)
440 return ret;
441
442 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL);
443 val |= (DP83869_RGMII_TX_CLK_DELAY_EN |
444 DP83869_RGMII_RX_CLK_DELAY_EN);
445
446 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
447 val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN |
448 DP83869_RGMII_RX_CLK_DELAY_EN);
449
450 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
451 val &= ~DP83869_RGMII_TX_CLK_DELAY_EN;
452
453 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
454 val &= ~DP83869_RGMII_RX_CLK_DELAY_EN;
455
456 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL,
457 val);
458 }
459
460 genphy_config_aneg(phydev);
461 return 0;
462 }
463
dp83869_probe(struct phy_device * phydev)464 static int dp83869_probe(struct phy_device *phydev)
465 {
466 struct dp83869_private *dp83869;
467
468 dp83869 = kzalloc(sizeof(*dp83869), GFP_KERNEL);
469 if (!dp83869)
470 return -ENOMEM;
471
472 phydev->priv = dp83869;
473 return 0;
474 }
475
476 U_BOOT_PHY_DRIVER(dp83869) = {
477 .name = "TI DP83869",
478 .uid = 0x2000a0f1,
479 .mask = 0xfffffff0,
480 .features = PHY_GBIT_FEATURES,
481 .probe = dp83869_probe,
482 .config = &dp83869_config,
483 .startup = &genphy_startup,
484 .shutdown = &genphy_shutdown,
485 .readext = dp83869_readext,
486 .writeext = dp83869_writeext
487 };
488