1 // SPDX-License-Identifier: GPL-2.0+
2 /**
3 * netsec.c - Socionext Synquacer Netsec driver
4 * Copyright 2021 Linaro Ltd.
5 */
6
7 #include <clk.h>
8 #include <cpu_func.h>
9 #include <dm.h>
10 #include <fdt_support.h>
11 #include <log.h>
12 #include <malloc.h>
13 #include <miiphy.h>
14 #include <net.h>
15 #include <regmap.h>
16 #include <reset.h>
17 #include <syscon.h>
18 #include <asm/cache.h>
19 #include <asm/global_data.h>
20 #include <dm/device_compat.h>
21 #include <linux/bitops.h>
22 #include <linux/delay.h>
23 #include <linux/err.h>
24 #include <linux/io.h>
25 #include <linux/iopoll.h>
26 #include <spi.h>
27 #include <spi_flash.h>
28
29 #define NETSEC_REG_SOFT_RST 0x104
30 #define NETSEC_REG_COM_INIT 0x120
31
32 #define NETSEC_REG_TOP_STATUS 0x200
33 #define NETSEC_IRQ_RX BIT(1)
34 #define NETSEC_IRQ_TX BIT(0)
35
36 #define NETSEC_REG_TOP_INTEN 0x204
37 #define NETSEC_REG_INTEN_SET 0x234
38 #define NETSEC_REG_INTEN_CLR 0x238
39
40 #define NETSEC_REG_NRM_TX_STATUS 0x400
41 #define NETSEC_REG_NRM_TX_INTEN 0x404
42 #define NETSEC_REG_NRM_TX_INTEN_SET 0x428
43 #define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c
44 #define NRM_TX_ST_NTOWNR BIT(17)
45 #define NRM_TX_ST_TR_ERR BIT(16)
46 #define NRM_TX_ST_TXDONE BIT(15)
47 #define NRM_TX_ST_TMREXP BIT(14)
48
49 #define NETSEC_REG_NRM_RX_STATUS 0x440
50 #define NETSEC_REG_NRM_RX_INTEN 0x444
51 #define NETSEC_REG_NRM_RX_INTEN_SET 0x468
52 #define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c
53 #define NRM_RX_ST_RC_ERR BIT(16)
54 #define NRM_RX_ST_PKTCNT BIT(15)
55 #define NRM_RX_ST_TMREXP BIT(14)
56
57 #define NETSEC_REG_PKT_CMD_BUF 0xd0
58
59 #define NETSEC_REG_CLK_EN 0x100
60
61 #define NETSEC_REG_PKT_CTRL 0x140
62
63 #define NETSEC_REG_DMA_TMR_CTRL 0x20c
64 #define NETSEC_REG_F_TAIKI_MC_VER 0x22c
65 #define NETSEC_REG_F_TAIKI_VER 0x230
66 #define NETSEC_REG_DMA_HM_CTRL 0x214
67 #define NETSEC_REG_DMA_MH_CTRL 0x220
68 #define NETSEC_REG_ADDR_DIS_CORE 0x218
69 #define NETSEC_REG_DMAC_HM_CMD_BUF 0x210
70 #define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c
71
72 #define NETSEC_REG_NRM_TX_PKTCNT 0x410
73
74 #define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414
75 #define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418
76
77 #define NETSEC_REG_NRM_TX_TMR 0x41c
78
79 #define NETSEC_REG_NRM_RX_PKTCNT 0x454
80 #define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458
81 #define NETSEC_REG_NRM_TX_TXINT_TMR 0x420
82 #define NETSEC_REG_NRM_RX_RXINT_TMR 0x460
83
84 #define NETSEC_REG_NRM_RX_TMR 0x45c
85
86 #define NETSEC_REG_NRM_TX_DESC_START_UP 0x434
87 #define NETSEC_REG_NRM_TX_DESC_START_LW 0x408
88 #define NETSEC_REG_NRM_RX_DESC_START_UP 0x474
89 #define NETSEC_REG_NRM_RX_DESC_START_LW 0x448
90
91 #define NETSEC_REG_NRM_TX_CONFIG 0x430
92 #define NETSEC_REG_NRM_RX_CONFIG 0x470
93
94 #define MAC_REG_STATUS 0x1024
95 #define MAC_REG_DATA 0x11c0
96 #define MAC_REG_CMD 0x11c4
97 #define MAC_REG_FLOW_TH 0x11cc
98 #define MAC_REG_INTF_SEL 0x11d4
99 #define MAC_REG_DESC_INIT 0x11fc
100 #define MAC_REG_DESC_SOFT_RST 0x1204
101 #define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500
102
103 #define GMAC_REG_MCR 0x0000
104 #define GMAC_REG_MFFR 0x0004
105 #define GMAC_REG_GAR 0x0010
106 #define GMAC_REG_GDR 0x0014
107 #define GMAC_REG_FCR 0x0018
108 #define GMAC_REG_BMR 0x1000
109 #define GMAC_REG_RDLAR 0x100c
110 #define GMAC_REG_TDLAR 0x1010
111 #define GMAC_REG_OMR 0x1018
112
113 #define MHZ(n) ((n) * 1000 * 1000)
114
115 #define NETSEC_TX_SHIFT_OWN_FIELD 31
116 #define NETSEC_TX_SHIFT_LD_FIELD 30
117 #define NETSEC_TX_SHIFT_DRID_FIELD 24
118 #define NETSEC_TX_SHIFT_PT_FIELD 21
119 #define NETSEC_TX_SHIFT_TDRID_FIELD 16
120 #define NETSEC_TX_SHIFT_CC_FIELD 15
121 #define NETSEC_TX_SHIFT_FS_FIELD 9
122 #define NETSEC_TX_LAST 8
123 #define NETSEC_TX_SHIFT_CO 7
124 #define NETSEC_TX_SHIFT_SO 6
125 #define NETSEC_TX_SHIFT_TRS_FIELD 4
126
127 #define NETSEC_RX_PKT_OWN_FIELD 31
128 #define NETSEC_RX_PKT_LD_FIELD 30
129 #define NETSEC_RX_PKT_SDRID_FIELD 24
130 #define NETSEC_RX_PKT_FR_FIELD 23
131 #define NETSEC_RX_PKT_ER_FIELD 21
132 #define NETSEC_RX_PKT_ERR_FIELD 16
133 #define NETSEC_RX_PKT_TDRID_FIELD 12
134 #define NETSEC_RX_PKT_FS_FIELD 9
135 #define NETSEC_RX_PKT_LS_FIELD 8
136 #define NETSEC_RX_PKT_CO_FIELD 6
137
138 #define NETSEC_RX_PKT_ERR_MASK 3
139
140 #define NETSEC_MAX_TX_PKT_LEN 1518
141 #define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018
142
143 #define NETSEC_RING_GMAC 15
144 #define NETSEC_RING_MAX 2
145
146 #define NETSEC_TCP_SEG_LEN_MAX 1460
147 #define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960
148
149 #define NETSEC_RX_CKSUM_NOTAVAIL 0
150 #define NETSEC_RX_CKSUM_OK 1
151 #define NETSEC_RX_CKSUM_NG 2
152
153 #define NETSEC_TOP_IRQ_REG_ME_START BIT(20)
154 #define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4)
155
156 #define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20)
157 #define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19)
158
159 #define NETSEC_INT_PKTCNT_MAX 2047
160
161 #define NETSEC_FLOW_START_TH_MAX 95
162 #define NETSEC_FLOW_STOP_TH_MAX 95
163 #define NETSEC_FLOW_PAUSE_TIME_MIN 5
164
165 #define NETSEC_CLK_EN_REG_DOM_ALL 0x3f
166
167 #define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28)
168 #define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27)
169 #define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3)
170 #define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2)
171 #define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1)
172 #define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0)
173
174 #define NETSEC_CLK_EN_REG_DOM_G BIT(5)
175 #define NETSEC_CLK_EN_REG_DOM_C BIT(1)
176 #define NETSEC_CLK_EN_REG_DOM_D BIT(0)
177
178 #define NETSEC_COM_INIT_REG_DB BIT(2)
179 #define NETSEC_COM_INIT_REG_CLS BIT(1)
180 #define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \
181 NETSEC_COM_INIT_REG_DB)
182
183 #define NETSEC_SOFT_RST_REG_RESET 0
184 #define NETSEC_SOFT_RST_REG_RUN BIT(31)
185
186 #define NETSEC_DMA_CTRL_REG_STOP 1
187 #define MH_CTRL__MODE_TRANS BIT(20)
188
189 #define NETSEC_GMAC_CMD_ST_READ 0
190 #define NETSEC_GMAC_CMD_ST_WRITE BIT(28)
191 #define NETSEC_GMAC_CMD_ST_BUSY BIT(31)
192
193 #define NETSEC_GMAC_BMR_REG_COMMON 0x00412080
194 #define NETSEC_GMAC_BMR_REG_RESET 0x00020181
195 #define NETSEC_GMAC_BMR_REG_SWR 0x00000001
196
197 #define NETSEC_GMAC_OMR_REG_ST BIT(13)
198 #define NETSEC_GMAC_OMR_REG_SR BIT(1)
199
200 #define NETSEC_GMAC_MCR_REG_IBN BIT(30)
201 #define NETSEC_GMAC_MCR_REG_CST BIT(25)
202 #define NETSEC_GMAC_MCR_REG_JE BIT(20)
203 #define NETSEC_MCR_PS BIT(15)
204 #define NETSEC_GMAC_MCR_REG_FES BIT(14)
205 #define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c
206 #define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c
207
208 #define NETSEC_FCR_RFE BIT(2)
209 #define NETSEC_FCR_TFE BIT(1)
210
211 #define NETSEC_GMAC_GAR_REG_GW BIT(1)
212 #define NETSEC_GMAC_GAR_REG_GB BIT(0)
213
214 #define NETSEC_GMAC_GAR_REG_SHIFT_PA 11
215 #define NETSEC_GMAC_GAR_REG_SHIFT_GR 6
216 #define GMAC_REG_SHIFT_CR_GAR 2
217
218 #define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2
219 #define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3
220 #define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0
221 #define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1
222 #define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4
223 #define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5
224
225 #define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000
226 #define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000
227
228 #define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000
229
230 #define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31)
231 #define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30)
232 #define NETSEC_REG_DESC_TMR_MODE 4
233 #define NETSEC_REG_DESC_ENDIAN 0
234
235 #define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1
236 #define NETSEC_MAC_DESC_INIT_REG_INIT 1
237
238 #define NETSEC_EEPROM_MAC_ADDRESS 0x00
239 #define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08
240 #define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C
241 #define NETSEC_EEPROM_HM_ME_SIZE 0x10
242 #define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14
243 #define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18
244 #define NETSEC_EEPROM_MH_ME_SIZE 0x1C
245 #define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20
246 #define NETSEC_EEPROM_PKT_ME_SIZE 0x24
247
248 #define DESC_SZ sizeof(struct netsec_de)
249
250 #define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000)
251
252 #define EERPROM_MAP_OFFSET 0x8000000
253 #define NOR_BLOCK 1024
254
255 struct netsec_de { /* Netsec Descriptor layout */
256 u32 attr;
257 u32 data_buf_addr_up;
258 u32 data_buf_addr_lw;
259 u32 buf_len_info;
260 };
261
262 struct netsec_priv {
263 struct netsec_de rxde[PKTBUFSRX];
264 struct netsec_de txde[1];
265 u16 rxat;
266
267 phys_addr_t eeprom_base;
268 phys_addr_t ioaddr;
269
270 struct mii_dev *bus;
271 struct phy_device *phydev;
272 u32 phy_addr, freq;
273 int phy_mode;
274 int max_speed;
275 };
276
277 struct netsec_tx_pkt_ctrl {
278 u16 tcp_seg_len;
279 bool tcp_seg_offload_flag;
280 bool cksum_offload_flag;
281 };
282
283 struct netsec_rx_pkt_info {
284 int rx_cksum_result;
285 int err_code;
286 bool err_flag;
287 };
288
netsec_write_reg(struct netsec_priv * priv,u32 reg_addr,u32 val)289 static void netsec_write_reg(struct netsec_priv *priv, u32 reg_addr, u32 val)
290 {
291 writel(val, priv->ioaddr + reg_addr);
292 }
293
netsec_read_reg(struct netsec_priv * priv,u32 reg_addr)294 static u32 netsec_read_reg(struct netsec_priv *priv, u32 reg_addr)
295 {
296 return readl(priv->ioaddr + reg_addr);
297 }
298
299 /************* MDIO BUS OPS FOLLOW *************/
300
301 #define TIMEOUT_SPINS_MAC 1000
302 #define TIMEOUT_SECONDARY_MS_MAC 100
303
netsec_clk_type(u32 freq)304 static u32 netsec_clk_type(u32 freq)
305 {
306 if (freq < MHZ(35))
307 return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ;
308 if (freq < MHZ(60))
309 return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ;
310 if (freq < MHZ(100))
311 return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ;
312 if (freq < MHZ(150))
313 return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ;
314 if (freq < MHZ(250))
315 return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ;
316
317 return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ;
318 }
319
netsec_wait_while_busy(struct netsec_priv * priv,u32 addr,u32 mask)320 static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask)
321 {
322 u32 timeout = TIMEOUT_SPINS_MAC;
323
324 while (--timeout && netsec_read_reg(priv, addr) & mask)
325 cpu_relax();
326 if (timeout)
327 return 0;
328
329 timeout = TIMEOUT_SECONDARY_MS_MAC;
330 while (--timeout && netsec_read_reg(priv, addr) & mask)
331 udelay(2000);
332
333 if (timeout)
334 return 0;
335
336 pr_err("%s: timeout\n", __func__);
337
338 return -ETIMEDOUT;
339 }
340
netsec_set_mac_reg(struct netsec_priv * priv,u32 addr,u32 value)341 static int netsec_set_mac_reg(struct netsec_priv *priv, u32 addr, u32 value)
342 {
343 netsec_write_reg(priv, MAC_REG_DATA, value);
344 netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);
345 return netsec_wait_while_busy(priv,
346 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
347 }
348
netsec_get_mac_reg(struct netsec_priv * priv,u32 addr,u32 * read)349 static int netsec_get_mac_reg(struct netsec_priv *priv, u32 addr, u32 *read)
350 {
351 int ret;
352
353 netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);
354 ret = netsec_wait_while_busy(priv,
355 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
356 if (ret)
357 return ret;
358
359 *read = netsec_read_reg(priv, MAC_REG_DATA);
360
361 return 0;
362 }
363
netsec_mac_wait_while_busy(struct netsec_priv * priv,u32 addr,u32 mask)364 static int netsec_mac_wait_while_busy(struct netsec_priv *priv,
365 u32 addr, u32 mask)
366 {
367 u32 timeout = TIMEOUT_SPINS_MAC;
368 u32 data;
369 int ret;
370
371 do {
372 ret = netsec_get_mac_reg(priv, addr, &data);
373 if (ret)
374 break;
375 udelay(1);
376 } while (--timeout && (data & mask));
377
378 if (timeout)
379 return 0;
380
381 timeout = TIMEOUT_SECONDARY_MS_MAC;
382 do {
383 udelay(2000);
384
385 ret = netsec_get_mac_reg(priv, addr, &data);
386 if (ret)
387 break;
388 cpu_relax();
389 } while (--timeout && (data & mask));
390
391 if (timeout && !ret)
392 return 0;
393
394 return -ETIMEDOUT;
395 }
396
netsec_cache_invalidate(uintptr_t vaddr,int len)397 static void netsec_cache_invalidate(uintptr_t vaddr, int len)
398 {
399 invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
400 roundup(vaddr + len, ARCH_DMA_MINALIGN));
401 }
402
netsec_cache_flush(uintptr_t vaddr,int len)403 static void netsec_cache_flush(uintptr_t vaddr, int len)
404 {
405 flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
406 roundup(vaddr + len, ARCH_DMA_MINALIGN));
407 }
408
netsec_set_rx_de(struct netsec_priv * priv,u16 idx,void * addr)409 static void netsec_set_rx_de(struct netsec_priv *priv, u16 idx, void *addr)
410 {
411 struct netsec_de *de = &priv->rxde[idx];
412 u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) |
413 (1 << NETSEC_RX_PKT_FS_FIELD) |
414 (1 << NETSEC_RX_PKT_LS_FIELD);
415
416 if (idx == PKTBUFSRX - 1)
417 attr |= (1 << NETSEC_RX_PKT_LD_FIELD);
418
419 de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr);
420 de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr);
421 de->buf_len_info = PKTSIZE;
422 de->attr = attr;
423 dmb();
424 netsec_cache_flush((uintptr_t)de, sizeof(*de));
425 }
426
netsec_set_tx_de(struct netsec_priv * priv,void * addr,int len)427 static void netsec_set_tx_de(struct netsec_priv *priv, void *addr, int len)
428 {
429 struct netsec_de *de = &priv->txde[0];
430 u32 attr;
431
432 attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) |
433 (1 << NETSEC_TX_SHIFT_PT_FIELD) |
434 (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) |
435 (1 << NETSEC_TX_SHIFT_FS_FIELD) |
436 (1 << NETSEC_TX_LAST) |
437 (1 << NETSEC_TX_SHIFT_TRS_FIELD) |
438 (1 << NETSEC_TX_SHIFT_LD_FIELD);
439
440 de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr);
441 de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr);
442 de->buf_len_info = len;
443 de->attr = attr;
444 dmb();
445 netsec_cache_flush((uintptr_t)de, sizeof(*de));
446 }
447
netsec_get_phy_reg(struct netsec_priv * priv,int phy_addr,int reg_addr)448 static int netsec_get_phy_reg(struct netsec_priv *priv,
449 int phy_addr, int reg_addr)
450 {
451 u32 data;
452 int ret;
453
454 if (phy_addr != 7)
455 return -EINVAL;
456
457 if (netsec_set_mac_reg(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB |
458 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
459 reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
460 (netsec_clk_type(priv->freq) <<
461 GMAC_REG_SHIFT_CR_GAR)))
462 return -ETIMEDOUT;
463
464 ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
465 NETSEC_GMAC_GAR_REG_GB);
466 if (ret)
467 return ret;
468
469 ret = netsec_get_mac_reg(priv, GMAC_REG_GDR, &data);
470 if (ret)
471 return ret;
472
473 return data;
474 }
475
netsec_set_phy_reg(struct netsec_priv * priv,int phy_addr,int reg_addr,u16 val)476 static int netsec_set_phy_reg(struct netsec_priv *priv,
477 int phy_addr, int reg_addr, u16 val)
478 {
479 int ret;
480
481 if (phy_addr != 7)
482 return -EINVAL;
483 if (netsec_set_mac_reg(priv, GMAC_REG_GDR, val))
484 return -ETIMEDOUT;
485
486 if (netsec_set_mac_reg(priv, GMAC_REG_GAR,
487 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
488 reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
489 NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB |
490 (netsec_clk_type(priv->freq) <<
491 GMAC_REG_SHIFT_CR_GAR)))
492 return -ETIMEDOUT;
493
494 ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
495 NETSEC_GMAC_GAR_REG_GB);
496
497 /* Developerbox implements RTL8211E PHY and there is
498 * a compatibility problem with F_GMAC4.
499 * RTL8211E expects MDC clock must be kept toggling for several
500 * clock cycle with MDIO high before entering the IDLE state.
501 * To meet this requirement, netsec driver needs to issue dummy
502 * read(e.g. read PHYID1(offset 0x2) register) right after write.
503 */
504 netsec_get_phy_reg(priv, phy_addr, MII_PHYSID1);
505
506 return ret;
507 }
508
netsec_mac_update_to_phy_state(struct netsec_priv * priv)509 static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
510 {
511 struct phy_device *phydev = priv->phydev;
512 u32 value = 0;
513
514 value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON :
515 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON;
516
517 if (phydev->speed != SPEED_1000)
518 value |= NETSEC_MCR_PS;
519
520 if (phydev->interface != PHY_INTERFACE_MODE_GMII &&
521 phydev->speed == SPEED_100)
522 value |= NETSEC_GMAC_MCR_REG_FES;
523
524 value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE;
525
526 if (phy_interface_is_rgmii(phydev))
527 value |= NETSEC_GMAC_MCR_REG_IBN;
528
529 if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value))
530 return -ETIMEDOUT;
531
532 return 0;
533 }
534
netsec_start_gmac(struct netsec_priv * priv)535 static int netsec_start_gmac(struct netsec_priv *priv)
536 {
537 u32 value = 0;
538 int ret;
539
540 if (priv->max_speed != SPEED_1000)
541 value = (NETSEC_GMAC_MCR_REG_CST |
542 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON);
543
544 if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value))
545 return -ETIMEDOUT;
546
547 if (netsec_set_mac_reg(priv, GMAC_REG_BMR,
548 NETSEC_GMAC_BMR_REG_RESET))
549 return -ETIMEDOUT;
550
551 /* Wait soft reset */
552 mdelay(5);
553
554 ret = netsec_get_mac_reg(priv, GMAC_REG_BMR, &value);
555 if (ret)
556 return ret;
557
558 if (value & NETSEC_GMAC_BMR_REG_SWR)
559 return -EAGAIN;
560
561 netsec_write_reg(priv, MAC_REG_DESC_SOFT_RST, 1);
562 if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1))
563 return -ETIMEDOUT;
564
565 netsec_write_reg(priv, MAC_REG_DESC_INIT, 1);
566 if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1))
567 return -ETIMEDOUT;
568
569 if (netsec_set_mac_reg(priv, GMAC_REG_BMR,
570 NETSEC_GMAC_BMR_REG_COMMON))
571 return -ETIMEDOUT;
572
573 if (netsec_set_mac_reg(priv, GMAC_REG_RDLAR,
574 NETSEC_GMAC_RDLAR_REG_COMMON))
575 return -ETIMEDOUT;
576
577 if (netsec_set_mac_reg(priv, GMAC_REG_TDLAR,
578 NETSEC_GMAC_TDLAR_REG_COMMON))
579 return -ETIMEDOUT;
580
581 if (netsec_set_mac_reg(priv, GMAC_REG_MFFR, 0x80000001))
582 return -ETIMEDOUT;
583
584 ret = netsec_mac_update_to_phy_state(priv);
585 if (ret)
586 return ret;
587
588 ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value);
589 if (ret)
590 return ret;
591
592 value |= NETSEC_GMAC_OMR_REG_SR;
593 value |= NETSEC_GMAC_OMR_REG_ST;
594
595 netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
596 netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
597
598 if (netsec_set_mac_reg(priv, GMAC_REG_OMR, value))
599 return -ETIMEDOUT;
600
601 return 0;
602 }
603
netsec_stop_gmac(struct netsec_priv * priv)604 static int netsec_stop_gmac(struct netsec_priv *priv)
605 {
606 u32 value;
607 int ret;
608
609 ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value);
610 if (ret)
611 return ret;
612 value &= ~NETSEC_GMAC_OMR_REG_SR;
613 value &= ~NETSEC_GMAC_OMR_REG_ST;
614
615 /* disable all interrupts */
616 netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
617 netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
618
619 return netsec_set_mac_reg(priv, GMAC_REG_OMR, value);
620 }
621
netsec_spi_read(char * buf,loff_t len,loff_t offset)622 static void netsec_spi_read(char *buf, loff_t len, loff_t offset)
623 {
624 struct spi_flash *flash;
625
626 flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
627 CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
628
629 spi_flash_read(flash, offset, len, buf);
630 }
631
netsec_read_rom_hwaddr(struct udevice * dev)632 static int netsec_read_rom_hwaddr(struct udevice *dev)
633 {
634 struct netsec_priv *priv = dev_get_priv(dev);
635 struct eth_pdata *pdata = dev_get_plat(dev);
636 char macp[NOR_BLOCK];
637
638 netsec_spi_read(macp, sizeof(macp), priv->eeprom_base);
639
640 pdata->enetaddr[0] = readb(macp + 3);
641 pdata->enetaddr[1] = readb(macp + 2);
642 pdata->enetaddr[2] = readb(macp + 1);
643 pdata->enetaddr[3] = readb(macp + 0);
644 pdata->enetaddr[4] = readb(macp + 7);
645 pdata->enetaddr[5] = readb(macp + 6);
646 return 0;
647 }
648
netsec_send(struct udevice * dev,void * packet,int length)649 static int netsec_send(struct udevice *dev, void *packet, int length)
650 {
651 struct netsec_priv *priv = dev_get_priv(dev);
652 u32 val, tout;
653
654 val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_STATUS);
655 netsec_cache_flush((uintptr_t)packet, length);
656 netsec_set_tx_de(priv, packet, length);
657 netsec_write_reg(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */
658
659 val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT);
660
661 tout = 10000;
662 do {
663 val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT);
664 udelay(2);
665 } while (--tout && !val);
666
667 if (!tout) {
668 val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT);
669 pr_err("%s: ETIMEDOUT: %dpackets\n", __func__, val);
670 return -ETIMEDOUT;
671 }
672
673 return 0;
674 }
675
netsec_free_packet(struct udevice * dev,uchar * packet,int length)676 static int netsec_free_packet(struct udevice *dev, uchar *packet, int length)
677 {
678 struct netsec_priv *priv = dev_get_priv(dev);
679
680 netsec_set_rx_de(priv, priv->rxat, net_rx_packets[priv->rxat]);
681
682 priv->rxat++;
683 if (priv->rxat == PKTBUFSRX)
684 priv->rxat = 0;
685
686 return 0;
687 }
688
netsec_recv(struct udevice * dev,int flags,uchar ** packetp)689 static int netsec_recv(struct udevice *dev, int flags, uchar **packetp)
690 {
691 struct netsec_priv *priv = dev_get_priv(dev);
692 int idx = priv->rxat;
693 uchar *ptr = net_rx_packets[idx];
694 struct netsec_de *de = &priv->rxde[idx];
695 int length = 0;
696
697 netsec_cache_invalidate((uintptr_t)de, sizeof(*de));
698
699 if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD))
700 return -EAGAIN;
701
702 length = de->buf_len_info >> 16;
703
704 /* invalidate after DMA is done */
705 netsec_cache_invalidate((uintptr_t)ptr, length);
706 *packetp = ptr;
707
708 return length;
709 }
710
_netsec_get_phy_reg(struct mii_dev * bus,int phy_addr,int devad,int reg_addr)711 static int _netsec_get_phy_reg(struct mii_dev *bus,
712 int phy_addr, int devad, int reg_addr)
713 {
714 return netsec_get_phy_reg(bus->priv, phy_addr, reg_addr);
715 }
716
_netsec_set_phy_reg(struct mii_dev * bus,int phy_addr,int devad,int reg_addr,u16 val)717 static int _netsec_set_phy_reg(struct mii_dev *bus,
718 int phy_addr, int devad, int reg_addr, u16 val)
719 {
720 return netsec_set_phy_reg(bus->priv, phy_addr, reg_addr, val);
721 }
722
netsec_mdiobus_init(struct netsec_priv * priv,const char * name)723 static int netsec_mdiobus_init(struct netsec_priv *priv, const char *name)
724 {
725 struct mii_dev *bus = mdio_alloc();
726
727 if (!bus)
728 return -ENOMEM;
729
730 bus->read = _netsec_get_phy_reg;
731 bus->write = _netsec_set_phy_reg;
732 snprintf(bus->name, sizeof(bus->name), "%s", name);
733 bus->priv = priv;
734
735 return mdio_register(bus);
736 }
737
netsec_phy_init(struct netsec_priv * priv,void * dev)738 static int netsec_phy_init(struct netsec_priv *priv, void *dev)
739 {
740 struct phy_device *phydev;
741 int ret;
742
743 phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
744
745 phydev->supported &= PHY_GBIT_FEATURES;
746 if (priv->max_speed) {
747 ret = phy_set_supported(phydev, priv->max_speed);
748 if (ret)
749 return ret;
750 }
751 phydev->advertising = phydev->supported;
752
753 priv->phydev = phydev;
754 phy_config(phydev);
755
756 return 0;
757 }
758
netsec_netdev_load_ucode_region(struct netsec_priv * priv,u32 reg,u32 addr_h,u32 addr_l,u32 size)759 static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg,
760 u32 addr_h, u32 addr_l, u32 size)
761 {
762 u64 base = ((u64)addr_h << 32 | addr_l) - EERPROM_MAP_OFFSET;
763
764 while (size > 0) {
765 char buf[NOR_BLOCK];
766 u32 *ucode = (u32 *)buf;
767 u64 off;
768 int i;
769
770 off = base % NOR_BLOCK;
771 base -= off;
772 netsec_spi_read(buf, sizeof(buf), base);
773
774 for (i = off / 4; i < sizeof(buf) / 4 && size > 0; i++, size--)
775 netsec_write_reg(priv, reg, ucode[i]);
776 base += NOR_BLOCK;
777 }
778
779 return 0;
780 }
781
netsec_netdev_load_microcode(struct netsec_priv * priv)782 static int netsec_netdev_load_microcode(struct netsec_priv *priv)
783 {
784 u32 addr_h, addr_l, size;
785 char buf[NOR_BLOCK];
786 u32 *ucinfo = (u32 *)buf;
787 int err;
788
789 netsec_spi_read(buf, sizeof(buf), priv->eeprom_base);
790
791 addr_h = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_H >> 2];
792 addr_l = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_L >> 2];
793 size = ucinfo[NETSEC_EEPROM_HM_ME_SIZE >> 2];
794
795 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF,
796 addr_h, addr_l, size);
797 if (err)
798 return err;
799
800 addr_h = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_H >> 2];
801 addr_l = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_L >> 2];
802 size = ucinfo[NETSEC_EEPROM_MH_ME_SIZE >> 2];
803
804 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF,
805 addr_h, addr_l, size);
806 if (err)
807 return err;
808
809 addr_h = 0;
810 addr_l = ucinfo[NETSEC_EEPROM_PKT_ME_ADDRESS >> 2];
811 size = ucinfo[NETSEC_EEPROM_PKT_ME_SIZE >> 2];
812
813 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF,
814 addr_h, addr_l, size);
815 if (err)
816 return err;
817
818 return 0;
819 }
820
netsec_pre_init_microengine(struct netsec_priv * priv)821 void netsec_pre_init_microengine(struct netsec_priv *priv)
822 {
823 u32 data;
824
825 /* Remove dormant settings */
826 data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR);
827 data &= ~BMCR_PDOWN;
828 data |= BMCR_ISOLATE;
829 netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
830 mdelay(100);
831
832 /* Put phy in loopback mode to guarantee RXCLK input */
833 data |= BMCR_LOOPBACK;
834 netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
835 mdelay(100);
836 }
837
netsec_post_init_microengine(struct netsec_priv * priv)838 void netsec_post_init_microengine(struct netsec_priv *priv)
839 {
840 u32 data;
841
842 /* Get phy back to normal operation */
843 data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR);
844 data &= ~BMCR_LOOPBACK;
845 netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
846 mdelay(100);
847
848 /* Apply software reset */
849 data |= BMCR_RESET;
850 netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
851 mdelay(100);
852 }
853
netsec_reset_hardware(struct netsec_priv * priv,bool load_ucode)854 static int netsec_reset_hardware(struct netsec_priv *priv, bool load_ucode)
855 {
856 u32 value;
857 int err;
858
859 netsec_write_reg(priv, NETSEC_REG_CLK_EN, 0x24);
860
861 /* stop DMA engines */
862 if (!netsec_read_reg(priv, NETSEC_REG_ADDR_DIS_CORE)) {
863 netsec_write_reg(priv, NETSEC_REG_DMA_HM_CTRL,
864 NETSEC_DMA_CTRL_REG_STOP);
865 netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL,
866 NETSEC_DMA_CTRL_REG_STOP);
867
868 value = 100;
869 while (netsec_read_reg(priv, NETSEC_REG_DMA_HM_CTRL) &
870 NETSEC_DMA_CTRL_REG_STOP) {
871 udelay(1000);
872 if (--value == 0) {
873 pr_err("%s:%d timeout!\n", __func__, __LINE__);
874 break;
875 }
876 }
877
878 value = 100;
879 while (netsec_read_reg(priv, NETSEC_REG_DMA_MH_CTRL) &
880 NETSEC_DMA_CTRL_REG_STOP) {
881 udelay(1000);
882 if (--value == 0) {
883 pr_err("%s:%d timeout!\n", __func__, __LINE__);
884 break;
885 }
886 }
887 }
888
889 netsec_set_mac_reg(priv, GMAC_REG_BMR, NETSEC_GMAC_BMR_REG_RESET);
890
891 netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET);
892 netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);
893 netsec_write_reg(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);
894
895 value = 100;
896 while (netsec_read_reg(priv, NETSEC_REG_COM_INIT) != 0) {
897 udelay(1000);
898 if (--value == 0) {
899 pr_err("%s:%d COM_INIT timeout!\n", __func__, __LINE__);
900 break;
901 }
902 }
903
904 /* MAC desc init */
905 netsec_write_reg(priv, MAC_REG_DESC_INIT, 1);
906 netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1);
907 /* set MAC_INTF_SEL */
908 netsec_write_reg(priv, MAC_REG_INTF_SEL, 1);
909
910 netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
911
912 /* set desc_start addr */
913 netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
914 upper_32_bits((dma_addr_t)priv->rxde));
915 netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
916 lower_32_bits((dma_addr_t)priv->rxde));
917
918 netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
919 upper_32_bits((dma_addr_t)priv->txde));
920 netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
921 lower_32_bits((dma_addr_t)priv->txde));
922
923 /* set normal tx dring ring config */
924 netsec_write_reg(priv, NETSEC_REG_NRM_TX_CONFIG,
925 1 << NETSEC_REG_DESC_ENDIAN);
926 netsec_write_reg(priv, NETSEC_REG_NRM_RX_CONFIG,
927 1 << NETSEC_REG_DESC_ENDIAN);
928
929 if (load_ucode) {
930 err = netsec_netdev_load_microcode(priv);
931 if (err) {
932 pr_err("%s: failed to load microcode (%d)\n",
933 __func__, err);
934 return err;
935 }
936 }
937
938 /* set desc_start addr */
939 netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
940 upper_32_bits((dma_addr_t)priv->rxde));
941 netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
942 lower_32_bits((dma_addr_t)priv->rxde));
943
944 netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
945 upper_32_bits((dma_addr_t)priv->txde));
946 netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
947 lower_32_bits((dma_addr_t)priv->txde));
948
949 netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
950
951 /* start DMA engines */
952 netsec_write_reg(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1);
953
954 netsec_pre_init_microengine(priv);
955
956 netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 0);
957
958 mdelay(100);
959
960 if (!(netsec_read_reg(priv, NETSEC_REG_TOP_STATUS) &
961 NETSEC_TOP_IRQ_REG_ME_START)) {
962 pr_err("microengine start failed\n");
963 return -ENXIO;
964 }
965
966 netsec_post_init_microengine(priv);
967
968 /* clear microcode load end status */
969 netsec_write_reg(priv, NETSEC_REG_TOP_STATUS,
970 NETSEC_TOP_IRQ_REG_ME_START);
971
972 netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
973
974 value = netsec_read_reg(priv, NETSEC_REG_PKT_CTRL);
975 value |= NETSEC_PKT_CTRL_REG_MODE_NRM;
976 /* change to normal mode */
977 netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);
978 netsec_write_reg(priv, NETSEC_REG_PKT_CTRL, value);
979
980 value = 100;
981 while ((netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) &
982 NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) {
983 udelay(1000);
984 if (--value == 0) {
985 value = netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS);
986 pr_err("%s:%d timeout! val=%x\n", __func__, __LINE__, value);
987 break;
988 }
989 }
990
991 /* clear any pending EMPTY/ERR irq status */
992 netsec_write_reg(priv, NETSEC_REG_NRM_TX_STATUS, ~0);
993
994 /* Disable TX & RX intr */
995 netsec_write_reg(priv, NETSEC_REG_INTEN_CLR, ~0);
996
997 return 0;
998 }
999
netsec_stop(struct udevice * dev)1000 static void netsec_stop(struct udevice *dev)
1001 {
1002 struct netsec_priv *priv = dev_get_priv(dev);
1003
1004 netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 7);
1005 netsec_stop_gmac(priv);
1006 phy_shutdown(priv->phydev);
1007 netsec_reset_hardware(priv, false);
1008 }
1009
netsec_start(struct udevice * dev)1010 static int netsec_start(struct udevice *dev)
1011 {
1012 struct netsec_priv *priv = dev_get_priv(dev);
1013 int i;
1014
1015 phy_startup(priv->phydev);
1016 netsec_start_gmac(priv);
1017
1018 priv->rxat = 0;
1019 for (i = 0; i < PKTBUFSRX; i++)
1020 netsec_set_rx_de(priv, i, net_rx_packets[i]);
1021
1022 return 0;
1023 }
1024
netsec_of_to_plat(struct udevice * dev)1025 static int netsec_of_to_plat(struct udevice *dev)
1026 {
1027 struct eth_pdata *pdata = dev_get_plat(dev);
1028 struct netsec_priv *priv = dev_get_priv(dev);
1029 struct ofnode_phandle_args phandle_args;
1030
1031 pdata->iobase = dev_read_addr_index(dev, 0);
1032 priv->eeprom_base = dev_read_addr_index(dev, 1) - EERPROM_MAP_OFFSET;
1033
1034 pdata->phy_interface = dev_read_phy_mode(dev);
1035 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
1036 return -EINVAL;
1037
1038 if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1039 &phandle_args))
1040 priv->phy_addr = ofnode_read_u32_default(phandle_args.node, "reg", 7);
1041 else
1042 priv->phy_addr = 7;
1043
1044 pdata->max_speed = dev_read_u32_default(dev, "max-speed", SPEED_1000);
1045
1046 priv->ioaddr = pdata->iobase;
1047 priv->phy_mode = pdata->phy_interface;
1048 priv->max_speed = pdata->max_speed;
1049 priv->freq = 250000000UL;
1050
1051 return 0;
1052 }
1053
netsec_probe(struct udevice * dev)1054 static int netsec_probe(struct udevice *dev)
1055 {
1056 struct netsec_priv *priv = dev_get_priv(dev);
1057 int ret;
1058
1059 netsec_reset_hardware(priv, true);
1060
1061 ret = netsec_mdiobus_init(priv, dev->name);
1062 if (ret) {
1063 pr_err("Failed to initialize mdiobus: %d\n", ret);
1064 return ret;
1065 }
1066
1067 priv->bus = miiphy_get_dev_by_name(dev->name);
1068
1069 ret = netsec_phy_init(priv, dev);
1070 if (ret) {
1071 pr_err("Failed to initialize phy: %d\n", ret);
1072 goto out_mdiobus_release;
1073 }
1074
1075 return 0;
1076 out_mdiobus_release:
1077 mdio_unregister(priv->bus);
1078 mdio_free(priv->bus);
1079 return ret;
1080 }
1081
netsec_remove(struct udevice * dev)1082 static int netsec_remove(struct udevice *dev)
1083 {
1084 struct netsec_priv *priv = dev_get_priv(dev);
1085
1086 free(priv->phydev);
1087 mdio_unregister(priv->bus);
1088 mdio_free(priv->bus);
1089
1090 return 0;
1091 }
1092
1093 static const struct eth_ops netsec_ops = {
1094 .start = netsec_start,
1095 .stop = netsec_stop,
1096 .send = netsec_send,
1097 .recv = netsec_recv,
1098 .free_pkt = netsec_free_packet,
1099 .read_rom_hwaddr = netsec_read_rom_hwaddr,
1100 };
1101
1102 static const struct udevice_id netsec_ids[] = {
1103 {
1104 .compatible = "socionext,synquacer-netsec",
1105 },
1106 {}
1107 };
1108
1109 U_BOOT_DRIVER(ave) = {
1110 .name = "synquacer_netsec",
1111 .id = UCLASS_ETH,
1112 .of_match = netsec_ids,
1113 .probe = netsec_probe,
1114 .remove = netsec_remove,
1115 .of_to_plat = netsec_of_to_plat,
1116 .ops = &netsec_ops,
1117 .priv_auto = sizeof(struct netsec_priv),
1118 .plat_auto = sizeof(struct eth_pdata),
1119 };
1120