1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * sunxi_emac.c -- Allwinner A10 ethernet driver
4 *
5 * (C) Copyright 2012, Stefan Roese <sr@denx.de>
6 */
7
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <log.h>
12 #include <dm/device_compat.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <malloc.h>
16 #include <miiphy.h>
17 #include <net.h>
18 #include <asm/io.h>
19 #include <asm/arch/clock.h>
20
21 /* EMAC register */
22 struct emac_regs {
23 u32 ctl; /* 0x00 */
24 u32 tx_mode; /* 0x04 */
25 u32 tx_flow; /* 0x08 */
26 u32 tx_ctl0; /* 0x0c */
27 u32 tx_ctl1; /* 0x10 */
28 u32 tx_ins; /* 0x14 */
29 u32 tx_pl0; /* 0x18 */
30 u32 tx_pl1; /* 0x1c */
31 u32 tx_sta; /* 0x20 */
32 u32 tx_io_data; /* 0x24 */
33 u32 tx_io_data1;/* 0x28 */
34 u32 tx_tsvl0; /* 0x2c */
35 u32 tx_tsvh0; /* 0x30 */
36 u32 tx_tsvl1; /* 0x34 */
37 u32 tx_tsvh1; /* 0x38 */
38 u32 rx_ctl; /* 0x3c */
39 u32 rx_hash0; /* 0x40 */
40 u32 rx_hash1; /* 0x44 */
41 u32 rx_sta; /* 0x48 */
42 u32 rx_io_data; /* 0x4c */
43 u32 rx_fbc; /* 0x50 */
44 u32 int_ctl; /* 0x54 */
45 u32 int_sta; /* 0x58 */
46 u32 mac_ctl0; /* 0x5c */
47 u32 mac_ctl1; /* 0x60 */
48 u32 mac_ipgt; /* 0x64 */
49 u32 mac_ipgr; /* 0x68 */
50 u32 mac_clrt; /* 0x6c */
51 u32 mac_maxf; /* 0x70 */
52 u32 mac_supp; /* 0x74 */
53 u32 mac_test; /* 0x78 */
54 u32 mac_mcfg; /* 0x7c */
55 u32 mac_mcmd; /* 0x80 */
56 u32 mac_madr; /* 0x84 */
57 u32 mac_mwtd; /* 0x88 */
58 u32 mac_mrdd; /* 0x8c */
59 u32 mac_mind; /* 0x90 */
60 u32 mac_ssrr; /* 0x94 */
61 u32 mac_a0; /* 0x98 */
62 u32 mac_a1; /* 0x9c */
63 };
64
65 /* SRAMC register */
66 struct sunxi_sramc_regs {
67 u32 ctrl0;
68 u32 ctrl1;
69 };
70
71 /* 0: Disable 1: Aborted frame enable(default) */
72 #define EMAC_TX_AB_M (0x1 << 0)
73 /* 0: CPU 1: DMA(default) */
74 #define EMAC_TX_TM (0x1 << 1)
75
76 #define EMAC_TX_SETUP (0)
77
78 /* 0: DRQ asserted 1: DRQ automatically(default) */
79 #define EMAC_RX_DRQ_MODE (0x1 << 1)
80 /* 0: CPU 1: DMA(default) */
81 #define EMAC_RX_TM (0x1 << 2)
82 /* 0: Normal(default) 1: Pass all Frames */
83 #define EMAC_RX_PA (0x1 << 4)
84 /* 0: Normal(default) 1: Pass Control Frames */
85 #define EMAC_RX_PCF (0x1 << 5)
86 /* 0: Normal(default) 1: Pass Frames with CRC Error */
87 #define EMAC_RX_PCRCE (0x1 << 6)
88 /* 0: Normal(default) 1: Pass Frames with Length Error */
89 #define EMAC_RX_PLE (0x1 << 7)
90 /* 0: Normal 1: Pass Frames length out of range(default) */
91 #define EMAC_RX_POR (0x1 << 8)
92 /* 0: Not accept 1: Accept unicast Packets(default) */
93 #define EMAC_RX_UCAD (0x1 << 16)
94 /* 0: Normal(default) 1: DA Filtering */
95 #define EMAC_RX_DAF (0x1 << 17)
96 /* 0: Not accept 1: Accept multicast Packets(default) */
97 #define EMAC_RX_MCO (0x1 << 20)
98 /* 0: Disable(default) 1: Enable Hash filter */
99 #define EMAC_RX_MHF (0x1 << 21)
100 /* 0: Not accept 1: Accept Broadcast Packets(default) */
101 #define EMAC_RX_BCO (0x1 << 22)
102 /* 0: Disable(default) 1: Enable SA Filtering */
103 #define EMAC_RX_SAF (0x1 << 24)
104 /* 0: Normal(default) 1: Inverse Filtering */
105 #define EMAC_RX_SAIF (0x1 << 25)
106
107 #define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
108 EMAC_RX_MCO | EMAC_RX_BCO)
109
110 /* 0: Disable 1: Enable Receive Flow Control(default) */
111 #define EMAC_MAC_CTL0_RFC (0x1 << 2)
112 /* 0: Disable 1: Enable Transmit Flow Control(default) */
113 #define EMAC_MAC_CTL0_TFC (0x1 << 3)
114
115 #define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
116
117 /* 0: Disable 1: Enable MAC Frame Length Checking(default) */
118 #define EMAC_MAC_CTL1_FLC (0x1 << 1)
119 /* 0: Disable(default) 1: Enable Huge Frame */
120 #define EMAC_MAC_CTL1_HF (0x1 << 2)
121 /* 0: Disable(default) 1: Enable MAC Delayed CRC */
122 #define EMAC_MAC_CTL1_DCRC (0x1 << 3)
123 /* 0: Disable 1: Enable MAC CRC(default) */
124 #define EMAC_MAC_CTL1_CRC (0x1 << 4)
125 /* 0: Disable 1: Enable MAC PAD Short frames(default) */
126 #define EMAC_MAC_CTL1_PC (0x1 << 5)
127 /* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
128 #define EMAC_MAC_CTL1_VC (0x1 << 6)
129 /* 0: Disable(default) 1: Enable MAC auto detect Short frames */
130 #define EMAC_MAC_CTL1_ADP (0x1 << 7)
131 /* 0: Disable(default) 1: Enable */
132 #define EMAC_MAC_CTL1_PRE (0x1 << 8)
133 /* 0: Disable(default) 1: Enable */
134 #define EMAC_MAC_CTL1_LPE (0x1 << 9)
135 /* 0: Disable(default) 1: Enable no back off */
136 #define EMAC_MAC_CTL1_NB (0x1 << 12)
137 /* 0: Disable(default) 1: Enable */
138 #define EMAC_MAC_CTL1_BNB (0x1 << 13)
139 /* 0: Disable(default) 1: Enable */
140 #define EMAC_MAC_CTL1_ED (0x1 << 14)
141
142 #define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
143 EMAC_MAC_CTL1_PC)
144
145 #define EMAC_MAC_IPGT 0x15
146
147 #define EMAC_MAC_NBTB_IPG1 0xc
148 #define EMAC_MAC_NBTB_IPG2 0x12
149
150 #define EMAC_MAC_CW 0x37
151 #define EMAC_MAC_RM 0xf
152
153 #define EMAC_MAC_MFL 0x0600
154
155 /* Receive status */
156 #define EMAC_CRCERR (0x1 << 4)
157 #define EMAC_LENERR (0x3 << 5)
158
159 #define EMAC_RX_BUFSIZE 2000
160
161 struct emac_eth_dev {
162 struct emac_regs *regs;
163 struct clk clk;
164 struct mii_dev *bus;
165 struct phy_device *phydev;
166 int link_printed;
167 uchar rx_buf[EMAC_RX_BUFSIZE];
168 };
169
170 struct emac_rxhdr {
171 s16 rx_len;
172 u16 rx_status;
173 };
174
emac_inblk_32bit(void * reg,void * data,int count)175 static void emac_inblk_32bit(void *reg, void *data, int count)
176 {
177 int cnt = (count + 3) >> 2;
178
179 if (cnt) {
180 u32 *buf = data;
181
182 do {
183 u32 x = readl(reg);
184 *buf++ = x;
185 } while (--cnt);
186 }
187 }
188
emac_outblk_32bit(void * reg,void * data,int count)189 static void emac_outblk_32bit(void *reg, void *data, int count)
190 {
191 int cnt = (count + 3) >> 2;
192
193 if (cnt) {
194 const u32 *buf = data;
195
196 do {
197 writel(*buf++, reg);
198 } while (--cnt);
199 }
200 }
201
202 /* Read a word from phyxcer */
emac_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)203 static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
204 {
205 struct emac_eth_dev *priv = bus->priv;
206 struct emac_regs *regs = priv->regs;
207
208 /* issue the phy address and reg */
209 writel(addr << 8 | reg, ®s->mac_madr);
210
211 /* pull up the phy io line */
212 writel(0x1, ®s->mac_mcmd);
213
214 /* Wait read complete */
215 mdelay(1);
216
217 /* push down the phy io line */
218 writel(0x0, ®s->mac_mcmd);
219
220 /* And read data */
221 return readl(®s->mac_mrdd);
222 }
223
224 /* Write a word to phyxcer */
emac_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)225 static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
226 u16 value)
227 {
228 struct emac_eth_dev *priv = bus->priv;
229 struct emac_regs *regs = priv->regs;
230
231 /* issue the phy address and reg */
232 writel(addr << 8 | reg, ®s->mac_madr);
233
234 /* pull up the phy io line */
235 writel(0x1, ®s->mac_mcmd);
236
237 /* Wait write complete */
238 mdelay(1);
239
240 /* push down the phy io line */
241 writel(0x0, ®s->mac_mcmd);
242
243 /* and write data */
244 writel(value, ®s->mac_mwtd);
245
246 return 0;
247 }
248
sunxi_emac_init_phy(struct emac_eth_dev * priv,void * dev)249 static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev)
250 {
251 int ret, mask = 0xffffffff;
252
253 #ifdef CONFIG_PHY_ADDR
254 mask = 1 << CONFIG_PHY_ADDR;
255 #endif
256
257 priv->bus = mdio_alloc();
258 if (!priv->bus) {
259 printf("Failed to allocate MDIO bus\n");
260 return -ENOMEM;
261 }
262
263 priv->bus->read = emac_mdio_read;
264 priv->bus->write = emac_mdio_write;
265 priv->bus->priv = priv;
266 strcpy(priv->bus->name, "emac");
267
268 ret = mdio_register(priv->bus);
269 if (ret)
270 return ret;
271
272 priv->phydev = phy_find_by_mask(priv->bus, mask);
273 if (!priv->phydev)
274 return -ENODEV;
275
276 phy_connect_dev(priv->phydev, dev, PHY_INTERFACE_MODE_MII);
277 phy_config(priv->phydev);
278
279 return 0;
280 }
281
emac_setup(struct emac_eth_dev * priv)282 static void emac_setup(struct emac_eth_dev *priv)
283 {
284 struct emac_regs *regs = priv->regs;
285 u32 reg_val;
286
287 /* Set up TX */
288 writel(EMAC_TX_SETUP, ®s->tx_mode);
289
290 /* Set up RX */
291 writel(EMAC_RX_SETUP, ®s->rx_ctl);
292
293 /* Set MAC */
294 /* Set MAC CTL0 */
295 writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0);
296
297 /* Set MAC CTL1 */
298 reg_val = 0;
299 if (priv->phydev->duplex == DUPLEX_FULL)
300 reg_val = (0x1 << 0);
301 writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1);
302
303 /* Set up IPGT */
304 writel(EMAC_MAC_IPGT, ®s->mac_ipgt);
305
306 /* Set up IPGR */
307 writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr);
308
309 /* Set up Collison window */
310 writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt);
311
312 /* Set up Max Frame Length */
313 writel(EMAC_MAC_MFL, ®s->mac_maxf);
314 }
315
emac_reset(struct emac_eth_dev * priv)316 static void emac_reset(struct emac_eth_dev *priv)
317 {
318 struct emac_regs *regs = priv->regs;
319
320 debug("resetting device\n");
321
322 /* RESET device */
323 writel(0, ®s->ctl);
324 udelay(200);
325
326 writel(1, ®s->ctl);
327 udelay(200);
328 }
329
_sunxi_write_hwaddr(struct emac_eth_dev * priv,u8 * enetaddr)330 static int _sunxi_write_hwaddr(struct emac_eth_dev *priv, u8 *enetaddr)
331 {
332 struct emac_regs *regs = priv->regs;
333 u32 enetaddr_lo, enetaddr_hi;
334
335 enetaddr_lo = enetaddr[2] | (enetaddr[1] << 8) | (enetaddr[0] << 16);
336 enetaddr_hi = enetaddr[5] | (enetaddr[4] << 8) | (enetaddr[3] << 16);
337
338 writel(enetaddr_hi, ®s->mac_a0);
339 writel(enetaddr_lo, ®s->mac_a1);
340
341 return 0;
342 }
343
_sunxi_emac_eth_init(struct emac_eth_dev * priv,u8 * enetaddr)344 static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
345 {
346 struct emac_regs *regs = priv->regs;
347 int ret;
348
349 /* Init EMAC */
350
351 /* Flush RX FIFO */
352 setbits_le32(®s->rx_ctl, 0x8);
353 udelay(1);
354
355 /* Init MAC */
356
357 /* Soft reset MAC */
358 clrbits_le32(®s->mac_ctl0, 0x1 << 15);
359
360 /* Clear RX counter */
361 writel(0x0, ®s->rx_fbc);
362 udelay(1);
363
364 /* Set up EMAC */
365 emac_setup(priv);
366
367 _sunxi_write_hwaddr(priv, enetaddr);
368
369 mdelay(1);
370
371 emac_reset(priv);
372
373 /* PHY POWER UP */
374 ret = phy_startup(priv->phydev);
375 if (ret) {
376 printf("Could not initialize PHY %s\n",
377 priv->phydev->dev->name);
378 return ret;
379 }
380
381 /* Print link status only once */
382 if (!priv->link_printed) {
383 printf("ENET Speed is %d Mbps - %s duplex connection\n",
384 priv->phydev->speed,
385 priv->phydev->duplex ? "FULL" : "HALF");
386 priv->link_printed = 1;
387 }
388
389 /* Set EMAC SPEED depend on PHY */
390 if (priv->phydev->speed == SPEED_100)
391 setbits_le32(®s->mac_supp, 1 << 8);
392 else
393 clrbits_le32(®s->mac_supp, 1 << 8);
394
395 /* Set duplex depend on phy */
396 if (priv->phydev->duplex == DUPLEX_FULL)
397 setbits_le32(®s->mac_ctl1, 1 << 0);
398 else
399 clrbits_le32(®s->mac_ctl1, 1 << 0);
400
401 /* Enable RX/TX */
402 setbits_le32(®s->ctl, 0x7);
403
404 return 0;
405 }
406
_sunxi_emac_eth_recv(struct emac_eth_dev * priv,void * packet)407 static int _sunxi_emac_eth_recv(struct emac_eth_dev *priv, void *packet)
408 {
409 struct emac_regs *regs = priv->regs;
410 struct emac_rxhdr rxhdr;
411 u32 rxcount;
412 u32 reg_val;
413 int rx_len;
414 int rx_status;
415 int good_packet;
416
417 /* Check packet ready or not */
418
419 /* Race warning: The first packet might arrive with
420 * the interrupts disabled, but the second will fix
421 */
422 rxcount = readl(®s->rx_fbc);
423 if (!rxcount) {
424 /* Had one stuck? */
425 rxcount = readl(®s->rx_fbc);
426 if (!rxcount)
427 return -EAGAIN;
428 }
429
430 reg_val = readl(®s->rx_io_data);
431 if (reg_val != 0x0143414d) {
432 /* Disable RX */
433 clrbits_le32(®s->ctl, 0x1 << 2);
434
435 /* Flush RX FIFO */
436 setbits_le32(®s->rx_ctl, 0x1 << 3);
437 while (readl(®s->rx_ctl) & (0x1 << 3))
438 ;
439
440 /* Enable RX */
441 setbits_le32(®s->ctl, 0x1 << 2);
442
443 return -EAGAIN;
444 }
445
446 /* A packet ready now
447 * Get status/length
448 */
449 good_packet = 1;
450
451 emac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr));
452
453 rx_len = rxhdr.rx_len;
454 rx_status = rxhdr.rx_status;
455
456 /* Packet Status check */
457 if (rx_len < 0x40) {
458 good_packet = 0;
459 debug("RX: Bad Packet (runt)\n");
460 }
461
462 /* rx_status is identical to RSR register. */
463 if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
464 good_packet = 0;
465 if (rx_status & EMAC_CRCERR)
466 printf("crc error\n");
467 if (rx_status & EMAC_LENERR)
468 printf("length error\n");
469 }
470
471 /* Move data from EMAC */
472 if (good_packet) {
473 if (rx_len > EMAC_RX_BUFSIZE) {
474 printf("Received packet is too big (len=%d)\n", rx_len);
475 return -EMSGSIZE;
476 }
477 emac_inblk_32bit((void *)®s->rx_io_data, packet, rx_len);
478 return rx_len;
479 }
480
481 return -EIO; /* Bad packet */
482 }
483
_sunxi_emac_eth_send(struct emac_eth_dev * priv,void * packet,int len)484 static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet,
485 int len)
486 {
487 struct emac_regs *regs = priv->regs;
488
489 /* Select channel 0 */
490 writel(0, ®s->tx_ins);
491
492 /* Write packet */
493 emac_outblk_32bit((void *)®s->tx_io_data, packet, len);
494
495 /* Set TX len */
496 writel(len, ®s->tx_pl0);
497
498 /* Start translate from fifo to phy */
499 setbits_le32(®s->tx_ctl0, 1);
500
501 return 0;
502 }
503
sunxi_emac_board_setup(struct udevice * dev,struct emac_eth_dev * priv)504 static int sunxi_emac_board_setup(struct udevice *dev,
505 struct emac_eth_dev *priv)
506 {
507 struct sunxi_sramc_regs *sram =
508 (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
509 struct emac_regs *regs = priv->regs;
510 int ret;
511
512 /* Map SRAM to EMAC */
513 setbits_le32(&sram->ctrl1, 0x5 << 2);
514
515 /* Set up clock gating */
516 ret = clk_enable(&priv->clk);
517 if (ret) {
518 dev_err(dev, "failed to enable emac clock\n");
519 return ret;
520 }
521
522 /* Set MII clock */
523 clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
524
525 return 0;
526 }
527
sunxi_emac_eth_start(struct udevice * dev)528 static int sunxi_emac_eth_start(struct udevice *dev)
529 {
530 struct eth_pdata *pdata = dev_get_plat(dev);
531
532 return _sunxi_emac_eth_init(dev_get_priv(dev), pdata->enetaddr);
533 }
534
sunxi_emac_eth_send(struct udevice * dev,void * packet,int length)535 static int sunxi_emac_eth_send(struct udevice *dev, void *packet, int length)
536 {
537 struct emac_eth_dev *priv = dev_get_priv(dev);
538
539 return _sunxi_emac_eth_send(priv, packet, length);
540 }
541
sunxi_emac_eth_recv(struct udevice * dev,int flags,uchar ** packetp)542 static int sunxi_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
543 {
544 struct emac_eth_dev *priv = dev_get_priv(dev);
545 int rx_len;
546
547 rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf);
548 *packetp = priv->rx_buf;
549
550 return rx_len;
551 }
552
sunxi_emac_eth_stop(struct udevice * dev)553 static void sunxi_emac_eth_stop(struct udevice *dev)
554 {
555 /* Nothing to do here */
556 }
557
sunxi_emac_eth_probe(struct udevice * dev)558 static int sunxi_emac_eth_probe(struct udevice *dev)
559 {
560 struct eth_pdata *pdata = dev_get_plat(dev);
561 struct emac_eth_dev *priv = dev_get_priv(dev);
562 int ret;
563
564 priv->regs = (struct emac_regs *)pdata->iobase;
565
566 ret = clk_get_by_index(dev, 0, &priv->clk);
567 if (ret) {
568 dev_err(dev, "failed to get emac clock\n");
569 return ret;
570 }
571
572 ret = sunxi_emac_board_setup(dev, priv);
573 if (ret)
574 return ret;
575
576 return sunxi_emac_init_phy(priv, dev);
577 }
578
579 static const struct eth_ops sunxi_emac_eth_ops = {
580 .start = sunxi_emac_eth_start,
581 .send = sunxi_emac_eth_send,
582 .recv = sunxi_emac_eth_recv,
583 .stop = sunxi_emac_eth_stop,
584 };
585
sunxi_emac_eth_of_to_plat(struct udevice * dev)586 static int sunxi_emac_eth_of_to_plat(struct udevice *dev)
587 {
588 struct eth_pdata *pdata = dev_get_plat(dev);
589
590 pdata->iobase = dev_read_addr(dev);
591
592 return 0;
593 }
594
595 static const struct udevice_id sunxi_emac_eth_ids[] = {
596 { .compatible = "allwinner,sun4i-a10-emac" },
597 { }
598 };
599
600 U_BOOT_DRIVER(eth_sunxi_emac) = {
601 .name = "eth_sunxi_emac",
602 .id = UCLASS_ETH,
603 .of_match = sunxi_emac_eth_ids,
604 .of_to_plat = sunxi_emac_eth_of_to_plat,
605 .probe = sunxi_emac_eth_probe,
606 .ops = &sunxi_emac_eth_ops,
607 .priv_auto = sizeof(struct emac_eth_dev),
608 .plat_auto = sizeof(struct eth_pdata),
609 };
610