1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale Three Speed Ethernet Controller driver
4 *
5 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
6 * (C) Copyright 2003, Motorola, Inc.
7 * author Andy Fleming
8 */
9
10 #include <config.h>
11 #include <common.h>
12 #include <dm.h>
13 #include <malloc.h>
14 #include <net.h>
15 #include <command.h>
16 #include <tsec.h>
17 #include <fsl_mdio.h>
18 #include <linux/bitops.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <miiphy.h>
22 #include <asm/processor.h>
23 #include <asm/io.h>
24
25 #define TBIANA_SETTINGS ( \
26 TBIANA_ASYMMETRIC_PAUSE \
27 | TBIANA_SYMMETRIC_PAUSE \
28 | TBIANA_FULL_DUPLEX \
29 )
30
31 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
32 #ifndef CFG_TSEC_TBICR_SETTINGS
33 #define CFG_TSEC_TBICR_SETTINGS ( \
34 TBICR_PHY_RESET \
35 | TBICR_ANEG_ENABLE \
36 | TBICR_FULL_DUPLEX \
37 | TBICR_SPEED1_SET \
38 )
39 #endif /* CFG_TSEC_TBICR_SETTINGS */
40
41 /* Configure the TBI for SGMII operation */
tsec_configure_serdes(struct tsec_private * priv)42 static void tsec_configure_serdes(struct tsec_private *priv)
43 {
44 /*
45 * Access TBI PHY registers at given TSEC register offset as opposed
46 * to the register offset used for external PHY accesses
47 */
48 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
49 0, TBI_ANA, TBIANA_SETTINGS);
50 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
51 0, TBI_TBICON, TBICON_CLK_SELECT);
52 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
53 0, TBI_CR, CFG_TSEC_TBICR_SETTINGS);
54 }
55
56 /* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
57 * and this is the ethernet-crc method needed for TSEC -- and perhaps
58 * some other adapter -- hash tables
59 */
60 #define CRCPOLY_LE 0xedb88320
ether_crc(size_t len,unsigned char const * p)61 static u32 ether_crc(size_t len, unsigned char const *p)
62 {
63 int i;
64 u32 crc;
65
66 crc = ~0;
67 while (len--) {
68 crc ^= *p++;
69 for (i = 0; i < 8; i++)
70 crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
71 }
72 /* an reverse the bits, cuz of way they arrive -- last-first */
73 crc = (crc >> 16) | (crc << 16);
74 crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
75 crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
76 crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
77 crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
78 return crc;
79 }
80
81 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
82
83 /* Set the appropriate hash bit for the given addr */
84
85 /*
86 * The algorithm works like so:
87 * 1) Take the Destination Address (ie the multicast address), and
88 * do a CRC on it (little endian), and reverse the bits of the
89 * result.
90 * 2) Use the 8 most significant bits as a hash into a 256-entry
91 * table. The table is controlled through 8 32-bit registers:
92 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
93 * 255. This means that the 3 most significant bits in the
94 * hash index which gaddr register to use, and the 5 other bits
95 * indicate which bit (assuming an IBM numbering scheme, which
96 * for PowerPC (tm) is usually the case) in the register holds
97 * the entry.
98 */
tsec_mcast_addr(struct udevice * dev,const u8 * mcast_mac,int join)99 static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
100 {
101 struct tsec_private *priv;
102 struct tsec __iomem *regs;
103 u32 result, value;
104 u8 whichbit, whichreg;
105
106 priv = dev_get_priv(dev);
107 regs = priv->regs;
108 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
109 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
110 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
111
112 value = BIT(31 - whichbit);
113
114 if (join)
115 setbits_be32(®s->hash.gaddr0 + whichreg, value);
116 else
117 clrbits_be32(®s->hash.gaddr0 + whichreg, value);
118
119 return 0;
120 }
121
tsec_set_promisc(struct udevice * dev,bool enable)122 static int __maybe_unused tsec_set_promisc(struct udevice *dev, bool enable)
123 {
124 struct tsec_private *priv = dev_get_priv(dev);
125 struct tsec __iomem *regs = priv->regs;
126
127 if (enable)
128 setbits_be32(®s->rctrl, RCTRL_PROM);
129 else
130 clrbits_be32(®s->rctrl, RCTRL_PROM);
131
132 return 0;
133 }
134
135 /*
136 * Initialized required registers to appropriate values, zeroing
137 * those we don't care about (unless zero is bad, in which case,
138 * choose a more appropriate value)
139 */
init_registers(struct tsec __iomem * regs)140 static void init_registers(struct tsec __iomem *regs)
141 {
142 /* Clear IEVENT */
143 out_be32(®s->ievent, IEVENT_INIT_CLEAR);
144
145 out_be32(®s->imask, IMASK_INIT_CLEAR);
146
147 out_be32(®s->hash.iaddr0, 0);
148 out_be32(®s->hash.iaddr1, 0);
149 out_be32(®s->hash.iaddr2, 0);
150 out_be32(®s->hash.iaddr3, 0);
151 out_be32(®s->hash.iaddr4, 0);
152 out_be32(®s->hash.iaddr5, 0);
153 out_be32(®s->hash.iaddr6, 0);
154 out_be32(®s->hash.iaddr7, 0);
155
156 out_be32(®s->hash.gaddr0, 0);
157 out_be32(®s->hash.gaddr1, 0);
158 out_be32(®s->hash.gaddr2, 0);
159 out_be32(®s->hash.gaddr3, 0);
160 out_be32(®s->hash.gaddr4, 0);
161 out_be32(®s->hash.gaddr5, 0);
162 out_be32(®s->hash.gaddr6, 0);
163 out_be32(®s->hash.gaddr7, 0);
164
165 /* Init RMON mib registers */
166 memset((void *)®s->rmon, 0, sizeof(regs->rmon));
167
168 out_be32(®s->rmon.cam1, 0xffffffff);
169 out_be32(®s->rmon.cam2, 0xffffffff);
170
171 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
172
173 out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
174
175 out_be32(®s->attr, ATTR_INIT_SETTINGS);
176 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
177 }
178
179 /*
180 * Configure maccfg2 based on negotiated speed and duplex
181 * reported by PHY handling code
182 */
adjust_link(struct tsec_private * priv,struct phy_device * phydev)183 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
184 {
185 struct tsec __iomem *regs = priv->regs;
186 u32 ecntrl, maccfg2;
187
188 if (!phydev->link) {
189 printf("%s: No link.\n", phydev->dev->name);
190 return;
191 }
192
193 /* clear all bits relative with interface mode */
194 ecntrl = in_be32(®s->ecntrl);
195 ecntrl &= ~ECNTRL_R100;
196
197 maccfg2 = in_be32(®s->maccfg2);
198 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
199
200 if (phydev->duplex)
201 maccfg2 |= MACCFG2_FULL_DUPLEX;
202
203 switch (phydev->speed) {
204 case 1000:
205 maccfg2 |= MACCFG2_GMII;
206 break;
207 case 100:
208 case 10:
209 maccfg2 |= MACCFG2_MII;
210
211 /*
212 * Set R100 bit in all modes although
213 * it is only used in RGMII mode
214 */
215 if (phydev->speed == 100)
216 ecntrl |= ECNTRL_R100;
217 break;
218 default:
219 printf("%s: Speed was bad\n", phydev->dev->name);
220 break;
221 }
222
223 out_be32(®s->ecntrl, ecntrl);
224 out_be32(®s->maccfg2, maccfg2);
225
226 printf("Speed: %d, %s duplex%s\n", phydev->speed,
227 (phydev->duplex) ? "full" : "half",
228 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
229 }
230
231 /*
232 * This returns the status bits of the device. The return value
233 * is never checked, and this is what the 8260 driver did, so we
234 * do the same. Presumably, this would be zero if there were no
235 * errors
236 */
tsec_send(struct udevice * dev,void * packet,int length)237 static int tsec_send(struct udevice *dev, void *packet, int length)
238 {
239 struct tsec_private *priv;
240 struct tsec __iomem *regs;
241 int result = 0;
242 u16 status;
243 int i;
244
245 priv = dev_get_priv(dev);
246 regs = priv->regs;
247 /* Find an empty buffer descriptor */
248 for (i = 0;
249 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
250 i++) {
251 if (i >= TOUT_LOOP) {
252 printf("%s: tsec: tx buffers full\n", dev->name);
253 return result;
254 }
255 }
256
257 out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
258 out_be16(&priv->txbd[priv->tx_idx].length, length);
259 status = in_be16(&priv->txbd[priv->tx_idx].status);
260 out_be16(&priv->txbd[priv->tx_idx].status, status |
261 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
262
263 /* Tell the DMA to go */
264 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
265
266 /* Wait for buffer to be transmitted */
267 for (i = 0;
268 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
269 i++) {
270 if (i >= TOUT_LOOP) {
271 printf("%s: tsec: tx error\n", dev->name);
272 return result;
273 }
274 }
275
276 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
277 result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
278
279 return result;
280 }
281
tsec_recv(struct udevice * dev,int flags,uchar ** packetp)282 static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
283 {
284 struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
285 struct tsec __iomem *regs = priv->regs;
286 int ret = -1;
287
288 if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
289 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
290 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
291 u32 buf;
292
293 /* Send the packet up if there were no errors */
294 if (!(status & RXBD_STATS)) {
295 buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
296 *packetp = (uchar *)buf;
297 ret = length - 4;
298 } else {
299 printf("Got error %x\n", (status & RXBD_STATS));
300 }
301 }
302
303 if (in_be32(®s->ievent) & IEVENT_BSY) {
304 out_be32(®s->ievent, IEVENT_BSY);
305 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
306 }
307
308 return ret;
309 }
310
tsec_free_pkt(struct udevice * dev,uchar * packet,int length)311 static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
312 {
313 struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
314 u16 status;
315
316 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
317
318 status = RXBD_EMPTY;
319 /* Set the wrap bit if this is the last element in the list */
320 if ((priv->rx_idx + 1) == PKTBUFSRX)
321 status |= RXBD_WRAP;
322 out_be16(&priv->rxbd[priv->rx_idx].status, status);
323
324 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
325
326 return 0;
327 }
328
tsec_halt(struct udevice * dev)329 static void tsec_halt(struct udevice *dev)
330 {
331 struct tsec_private *priv;
332 struct tsec __iomem *regs;
333 priv = dev_get_priv(dev);
334 regs = priv->regs;
335
336 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
337 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
338
339 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
340 != (IEVENT_GRSC | IEVENT_GTSC))
341 ;
342
343 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
344
345 /* Shut down the PHY, as needed */
346 phy_shutdown(priv->phydev);
347 }
348
349 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
350 /*
351 * When MACCFG1[Rx_EN] is enabled during system boot as part
352 * of the eTSEC port initialization sequence,
353 * the eTSEC Rx logic may not be properly initialized.
354 */
redundant_init(struct tsec_private * priv)355 static void redundant_init(struct tsec_private *priv)
356 {
357 struct tsec __iomem *regs = priv->regs;
358 uint t, count = 0;
359 int fail = 1;
360 static const u8 pkt[] = {
361 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
362 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
363 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
364 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
365 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
366 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
367 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
368 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
369 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
370 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
371 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
372 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
373 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
374 0x71, 0x72};
375
376 /* Enable promiscuous mode */
377 setbits_be32(®s->rctrl, RCTRL_PROM);
378 /* Enable loopback mode */
379 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
380 /* Enable transmit and receive */
381 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
382
383 /* Tell the DMA it is clear to go */
384 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
385 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
386 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
387 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
388
389 do {
390 u16 status;
391
392 tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
393
394 /* Wait for buffer to be received */
395 for (t = 0;
396 in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
397 t++) {
398 if (t >= 10 * TOUT_LOOP) {
399 printf("%s: tsec: rx error\n", priv->dev->name);
400 break;
401 }
402 }
403
404 if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
405 fail = 0;
406
407 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
408 status = RXBD_EMPTY;
409 if ((priv->rx_idx + 1) == PKTBUFSRX)
410 status |= RXBD_WRAP;
411 out_be16(&priv->rxbd[priv->rx_idx].status, status);
412 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
413
414 if (in_be32(®s->ievent) & IEVENT_BSY) {
415 out_be32(®s->ievent, IEVENT_BSY);
416 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
417 }
418 if (fail) {
419 printf("loopback recv packet error!\n");
420 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
421 udelay(1000);
422 setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
423 }
424 } while ((count++ < 4) && (fail == 1));
425
426 if (fail)
427 panic("eTSEC init fail!\n");
428 /* Disable promiscuous mode */
429 clrbits_be32(®s->rctrl, RCTRL_PROM);
430 /* Disable loopback mode */
431 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
432 }
433 #endif
434
435 /*
436 * Set up the buffers and their descriptors, and bring up the
437 * interface
438 */
startup_tsec(struct tsec_private * priv)439 static void startup_tsec(struct tsec_private *priv)
440 {
441 struct tsec __iomem *regs = priv->regs;
442 u16 status;
443 int i;
444
445 /* reset the indices to zero */
446 priv->rx_idx = 0;
447 priv->tx_idx = 0;
448 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
449 uint svr;
450 #endif
451
452 /* Point to the buffer descriptors */
453 out_be32(®s->tbase, (u32)&priv->txbd[0]);
454 out_be32(®s->rbase, (u32)&priv->rxbd[0]);
455
456 /* Initialize the Rx Buffer descriptors */
457 for (i = 0; i < PKTBUFSRX; i++) {
458 out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
459 out_be16(&priv->rxbd[i].length, 0);
460 out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
461 }
462 status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
463 out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
464
465 /* Initialize the TX Buffer Descriptors */
466 for (i = 0; i < TX_BUF_CNT; i++) {
467 out_be16(&priv->txbd[i].status, 0);
468 out_be16(&priv->txbd[i].length, 0);
469 out_be32(&priv->txbd[i].bufptr, 0);
470 }
471 status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
472 out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
473
474 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
475 svr = get_svr();
476 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
477 redundant_init(priv);
478 #endif
479 /* Enable Transmit and Receive */
480 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
481
482 /* Tell the DMA it is clear to go */
483 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
484 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
485 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
486 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
487 }
488
489 /*
490 * Initializes data structures and registers for the controller,
491 * and brings the interface up. Returns the link status, meaning
492 * that it returns success if the link is up, failure otherwise.
493 * This allows U-Boot to find the first active controller.
494 */
tsec_init(struct udevice * dev)495 static int tsec_init(struct udevice *dev)
496 {
497 struct tsec_private *priv;
498 struct tsec __iomem *regs;
499 struct eth_pdata *pdata = dev_get_plat(dev);
500 u32 tempval;
501 int ret;
502
503 priv = dev_get_priv(dev);
504 regs = priv->regs;
505 /* Make sure the controller is stopped */
506 tsec_halt(dev);
507
508 /* Init MACCFG2. Defaults to GMII */
509 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
510
511 /* Init ECNTRL */
512 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
513
514 /*
515 * Copy the station address into the address registers.
516 * For a station address of 0x12345678ABCD in transmission
517 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
518 * MACnADDR2 is set to 0x34120000.
519 */
520 tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
521 (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
522
523 out_be32(®s->macstnaddr1, tempval);
524
525 tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
526
527 out_be32(®s->macstnaddr2, tempval);
528
529 /* Clear out (for the most part) the other registers */
530 init_registers(regs);
531
532 /* Ready the device for tx/rx */
533 startup_tsec(priv);
534
535 /* Start up the PHY */
536 ret = phy_startup(priv->phydev);
537 if (ret) {
538 printf("Could not initialize PHY %s\n",
539 priv->phydev->dev->name);
540 return ret;
541 }
542
543 adjust_link(priv, priv->phydev);
544
545 /* If there's no link, fail */
546 return priv->phydev->link ? 0 : -1;
547 }
548
tsec_get_interface(struct tsec_private * priv)549 static phy_interface_t __maybe_unused tsec_get_interface(struct tsec_private *priv)
550 {
551 struct tsec __iomem *regs = priv->regs;
552 u32 ecntrl;
553
554 ecntrl = in_be32(®s->ecntrl);
555
556 if (ecntrl & ECNTRL_SGMII_MODE)
557 return PHY_INTERFACE_MODE_SGMII;
558
559 if (ecntrl & ECNTRL_TBI_MODE) {
560 if (ecntrl & ECNTRL_REDUCED_MODE)
561 return PHY_INTERFACE_MODE_RTBI;
562 else
563 return PHY_INTERFACE_MODE_TBI;
564 }
565
566 if (ecntrl & ECNTRL_REDUCED_MODE) {
567 phy_interface_t interface;
568
569 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
570 return PHY_INTERFACE_MODE_RMII;
571
572 interface = priv->interface;
573
574 /*
575 * This isn't autodetected, so it must
576 * be set by the platform code.
577 */
578 if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
579 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
580 interface == PHY_INTERFACE_MODE_RGMII_RXID)
581 return interface;
582
583 return PHY_INTERFACE_MODE_RGMII;
584 }
585
586 if (priv->flags & TSEC_GIGABIT)
587 return PHY_INTERFACE_MODE_GMII;
588
589 return PHY_INTERFACE_MODE_MII;
590 }
591
592 /*
593 * Discover which PHY is attached to the device, and configure it
594 * properly. If the PHY is not recognized, then return 0
595 * (failure). Otherwise, return 1
596 */
init_phy(struct tsec_private * priv)597 static int init_phy(struct tsec_private *priv)
598 {
599 struct phy_device *phydev;
600 struct tsec __iomem *regs = priv->regs;
601 u32 supported = (SUPPORTED_10baseT_Half |
602 SUPPORTED_10baseT_Full |
603 SUPPORTED_100baseT_Half |
604 SUPPORTED_100baseT_Full);
605
606 if (priv->flags & TSEC_GIGABIT)
607 supported |= SUPPORTED_1000baseT_Full;
608
609 /* Assign a Physical address to the TBI */
610 out_be32(®s->tbipa, priv->tbiaddr);
611
612 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
613 tsec_configure_serdes(priv);
614
615 #if defined(CONFIG_DM_MDIO)
616 phydev = dm_eth_phy_connect(priv->dev);
617 #else
618 phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
619 priv->interface);
620 #endif
621 if (!phydev)
622 return 0;
623
624 phydev->supported &= supported;
625 phydev->advertising = phydev->supported;
626
627 priv->phydev = phydev;
628
629 phy_config(phydev);
630
631 return 1;
632 }
633
tsec_probe(struct udevice * dev)634 int tsec_probe(struct udevice *dev)
635 {
636 struct eth_pdata *pdata = dev_get_plat(dev);
637 struct tsec_private *priv = dev_get_priv(dev);
638 struct ofnode_phandle_args phandle_args;
639 u32 tbiaddr = CFG_SYS_TBIPA_VALUE;
640 struct tsec_data *data;
641 ofnode parent, child;
642 fdt_addr_t reg;
643 u32 max_speed;
644 int ret;
645
646 data = (struct tsec_data *)dev_get_driver_data(dev);
647
648 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
649 if (pdata->iobase == FDT_ADDR_T_NONE) {
650 ofnode_for_each_subnode(child, dev_ofnode(dev)) {
651 if (strncmp(ofnode_get_name(child), "queue-group",
652 strlen("queue-group")))
653 continue;
654
655 reg = ofnode_get_addr(child);
656 if (reg == FDT_ADDR_T_NONE) {
657 printf("No 'reg' property of <queue-group>\n");
658 return -ENOENT;
659 }
660 pdata->iobase = reg;
661
662 /*
663 * if there are multiple queue groups,
664 * only the first one is used.
665 */
666 break;
667 }
668
669 if (!ofnode_valid(child)) {
670 printf("No child node for <queue-group>?\n");
671 return -ENOENT;
672 }
673 }
674
675 priv->regs = map_physmem(pdata->iobase, 0, MAP_NOCACHE);
676
677 ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
678 &phandle_args);
679 if (ret == 0) {
680 ofnode_read_u32(phandle_args.node, "reg", &tbiaddr);
681
682 parent = ofnode_get_parent(phandle_args.node);
683 if (!ofnode_valid(parent)) {
684 printf("No parent node for TBI PHY?\n");
685 return -ENOENT;
686 }
687
688 reg = ofnode_get_addr_index(parent, 0);
689 if (reg == FDT_ADDR_T_NONE) {
690 printf("No 'reg' property of MII for TBI PHY\n");
691 return -ENOENT;
692 }
693
694 priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off,
695 0, MAP_NOCACHE);
696 }
697
698 priv->tbiaddr = tbiaddr;
699
700 pdata->phy_interface = dev_read_phy_mode(dev);
701 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
702 pdata->phy_interface = tsec_get_interface(priv);
703
704 priv->interface = pdata->phy_interface;
705
706 /* Check for speed limit, default is 1000Mbps */
707 max_speed = dev_read_u32_default(dev, "max-speed", 1000);
708
709 /* Initialize flags */
710 if (max_speed == 1000)
711 priv->flags = TSEC_GIGABIT;
712 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
713 priv->flags |= TSEC_SGMII;
714
715 /* Reset the MAC */
716 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
717 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
718 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
719
720 priv->dev = dev;
721 priv->bus = miiphy_get_dev_by_name(dev->name);
722
723 /* Try to initialize PHY here, and return */
724 return !init_phy(priv);
725 }
726
tsec_remove(struct udevice * dev)727 int tsec_remove(struct udevice *dev)
728 {
729 struct tsec_private *priv = dev_get_priv(dev);
730
731 free(priv->phydev);
732 mdio_unregister(priv->bus);
733 mdio_free(priv->bus);
734
735 return 0;
736 }
737
738 static const struct eth_ops tsec_ops = {
739 .start = tsec_init,
740 .send = tsec_send,
741 .recv = tsec_recv,
742 .free_pkt = tsec_free_pkt,
743 .stop = tsec_halt,
744 .mcast = tsec_mcast_addr,
745 .set_promisc = tsec_set_promisc,
746 };
747
748 static struct tsec_data etsec2_data = {
749 .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
750 };
751
752 static struct tsec_data gianfar_data = {
753 .mdio_regs_off = 0x0,
754 };
755
756 static const struct udevice_id tsec_ids[] = {
757 { .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data },
758 { .compatible = "gianfar", .data = (ulong)&gianfar_data },
759 { }
760 };
761
762 U_BOOT_DRIVER(eth_tsec) = {
763 .name = "tsec",
764 .id = UCLASS_ETH,
765 .of_match = tsec_ids,
766 .probe = tsec_probe,
767 .remove = tsec_remove,
768 .ops = &tsec_ops,
769 .priv_auto = sizeof(struct tsec_private),
770 .plat_auto = sizeof(struct eth_pdata),
771 .flags = DM_FLAG_ALLOC_PRIV_DMA,
772 };
773