1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2021 Waymo LLC
4 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
5 * Copyright (C) 2011 PetaLogix
6 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
7 */
8
9 #include <config.h>
10 #include <common.h>
11 #include <cpu_func.h>
12 #include <display_options.h>
13 #include <dm.h>
14 #include <dm/device_compat.h>
15 #include <log.h>
16 #include <net.h>
17 #include <malloc.h>
18 #include <asm/global_data.h>
19 #include <asm/io.h>
20 #include <phy.h>
21 #include <miiphy.h>
22 #include <wait_bit.h>
23 #include <linux/delay.h>
24 #include <eth_phy.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 /* Link setup */
29 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
30 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
31 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
32 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
33
34 /* Interrupt Status/Enable/Mask Registers bit definitions */
35 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
36 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
37
38 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
39 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
40
41 /* Transmitter Configuration (TC) Register bit definitions */
42 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
43
44 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
45
46 /* MDIO Management Configuration (MC) Register bit definitions */
47 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
48
49 /* MDIO Management Control Register (MCR) Register bit definitions */
50 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
51 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
52 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
53 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
54 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
55 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
56 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
57 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
58
59 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
60
61 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
62
63 /* DMA macros */
64 /* Bitmasks of XAXIDMA_CR_OFFSET register */
65 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
66 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
67
68 /* Bitmasks of XAXIDMA_SR_OFFSET register */
69 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
70
71 /* Bitmask for interrupts */
72 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
73 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
74 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
75
76 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
77 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
78 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
79
80 /* Bitmasks for XXV Ethernet MAC */
81 #define XXV_TC_TX_MASK 0x00000001
82 #define XXV_TC_FCS_MASK 0x00000002
83 #define XXV_RCW1_RX_MASK 0x00000001
84 #define XXV_RCW1_FCS_MASK 0x00000002
85
86 #define DMAALIGN 128
87 #define XXV_MIN_PKT_SIZE 60
88
89 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
90 static u8 txminframe[XXV_MIN_PKT_SIZE] __attribute((aligned(DMAALIGN)));
91
92 enum emac_variant {
93 EMAC_1G = 0,
94 EMAC_10G_25G = 1,
95 };
96
97 /* Reflect dma offsets */
98 struct axidma_reg {
99 u32 control; /* DMACR */
100 u32 status; /* DMASR */
101 u32 current; /* CURDESC low 32 bit */
102 u32 current_hi; /* CURDESC high 32 bit */
103 u32 tail; /* TAILDESC low 32 bit */
104 u32 tail_hi; /* TAILDESC high 32 bit */
105 };
106
107 /* Platform data structures */
108 struct axidma_plat {
109 struct eth_pdata eth_pdata;
110 struct axidma_reg *dmatx;
111 struct axidma_reg *dmarx;
112 int pcsaddr;
113 int phyaddr;
114 u8 eth_hasnobuf;
115 int phy_of_handle;
116 enum emac_variant mactype;
117 };
118
119 /* Private driver structures */
120 struct axidma_priv {
121 struct axidma_reg *dmatx;
122 struct axidma_reg *dmarx;
123 int pcsaddr;
124 int phyaddr;
125 struct axi_regs *iobase;
126 phy_interface_t interface;
127 struct phy_device *phydev;
128 struct mii_dev *bus;
129 u8 eth_hasnobuf;
130 int phy_of_handle;
131 enum emac_variant mactype;
132 };
133
134 /* BD descriptors */
135 struct axidma_bd {
136 u32 next_desc; /* Next descriptor pointer */
137 u32 next_desc_msb;
138 u32 buf_addr; /* Buffer address */
139 u32 buf_addr_msb;
140 u32 reserved3;
141 u32 reserved4;
142 u32 cntrl; /* Control */
143 u32 status; /* Status */
144 u32 app0;
145 u32 app1; /* TX start << 16 | insert */
146 u32 app2; /* TX csum seed */
147 u32 app3;
148 u32 app4;
149 u32 sw_id_offset;
150 u32 reserved5;
151 u32 reserved6;
152 };
153
154 /* Static BDs - driver uses only one BD */
155 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
156 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
157
158 struct axi_regs {
159 u32 reserved[3];
160 u32 is; /* 0xC: Interrupt status */
161 u32 reserved2;
162 u32 ie; /* 0x14: Interrupt enable */
163 u32 reserved3[251];
164 u32 rcw1; /* 0x404: Rx Configuration Word 1 */
165 u32 tc; /* 0x408: Tx Configuration */
166 u32 reserved4;
167 u32 emmc; /* 0x410: EMAC mode configuration */
168 u32 reserved5[59];
169 u32 mdio_mc; /* 0x500: MII Management Config */
170 u32 mdio_mcr; /* 0x504: MII Management Control */
171 u32 mdio_mwd; /* 0x508: MII Management Write Data */
172 u32 mdio_mrd; /* 0x50C: MII Management Read Data */
173 u32 reserved6[124];
174 u32 uaw0; /* 0x700: Unicast address word 0 */
175 u32 uaw1; /* 0x704: Unicast address word 1 */
176 };
177
178 struct xxv_axi_regs {
179 u32 gt_reset; /* 0x0 */
180 u32 reserved[2];
181 u32 tc; /* 0xC: Tx Configuration */
182 u32 reserved2;
183 u32 rcw1; /* 0x14: Rx Configuration Word 1 */
184 };
185
186 /* Use MII register 1 (MII status register) to detect PHY */
187 #define PHY_DETECT_REG 1
188
189 /*
190 * Mask used to verify certain PHY features (or register contents)
191 * in the register above:
192 * 0x1000: 10Mbps full duplex support
193 * 0x0800: 10Mbps half duplex support
194 * 0x0008: Auto-negotiation support
195 */
196 #define PHY_DETECT_MASK 0x1808
197
mdio_wait(struct axi_regs * regs)198 static inline int mdio_wait(struct axi_regs *regs)
199 {
200 u32 timeout = 200;
201
202 /* Wait till MDIO interface is ready to accept a new transaction. */
203 while (timeout && (!(readl(®s->mdio_mcr)
204 & XAE_MDIO_MCR_READY_MASK))) {
205 timeout--;
206 udelay(1);
207 }
208 if (!timeout) {
209 printf("%s: Timeout\n", __func__);
210 return 1;
211 }
212 return 0;
213 }
214
215 /**
216 * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
217 * @bd: pointer to BD descriptor structure
218 * @desc: Address offset of DMA descriptors
219 *
220 * This function writes the value into the corresponding Axi DMA register.
221 */
axienet_dma_write(struct axidma_bd * bd,u32 * desc)222 static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
223 {
224 #if defined(CONFIG_PHYS_64BIT)
225 writeq((unsigned long)bd, desc);
226 #else
227 writel((u32)bd, desc);
228 #endif
229 }
230
phyread(struct axidma_priv * priv,u32 phyaddress,u32 registernum,u16 * val)231 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
232 u16 *val)
233 {
234 struct axi_regs *regs = priv->iobase;
235 u32 mdioctrlreg = 0;
236
237 if (mdio_wait(regs))
238 return 1;
239
240 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
241 XAE_MDIO_MCR_PHYAD_MASK) |
242 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
243 & XAE_MDIO_MCR_REGAD_MASK) |
244 XAE_MDIO_MCR_INITIATE_MASK |
245 XAE_MDIO_MCR_OP_READ_MASK;
246
247 writel(mdioctrlreg, ®s->mdio_mcr);
248
249 if (mdio_wait(regs))
250 return 1;
251
252 /* Read data */
253 *val = readl(®s->mdio_mrd);
254 return 0;
255 }
256
phywrite(struct axidma_priv * priv,u32 phyaddress,u32 registernum,u32 data)257 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
258 u32 data)
259 {
260 struct axi_regs *regs = priv->iobase;
261 u32 mdioctrlreg = 0;
262
263 if (mdio_wait(regs))
264 return 1;
265
266 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
267 XAE_MDIO_MCR_PHYAD_MASK) |
268 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
269 & XAE_MDIO_MCR_REGAD_MASK) |
270 XAE_MDIO_MCR_INITIATE_MASK |
271 XAE_MDIO_MCR_OP_WRITE_MASK;
272
273 /* Write data */
274 writel(data, ®s->mdio_mwd);
275
276 writel(mdioctrlreg, ®s->mdio_mcr);
277
278 if (mdio_wait(regs))
279 return 1;
280
281 return 0;
282 }
283
axiemac_phy_init(struct udevice * dev)284 static int axiemac_phy_init(struct udevice *dev)
285 {
286 u16 phyreg;
287 int i;
288 u32 ret;
289 struct axidma_priv *priv = dev_get_priv(dev);
290 struct axi_regs *regs = priv->iobase;
291 struct phy_device *phydev;
292
293 u32 supported = SUPPORTED_10baseT_Half |
294 SUPPORTED_10baseT_Full |
295 SUPPORTED_100baseT_Half |
296 SUPPORTED_100baseT_Full |
297 SUPPORTED_1000baseT_Half |
298 SUPPORTED_1000baseT_Full;
299
300 /* Set default MDIO divisor */
301 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
302
303 if (IS_ENABLED(CONFIG_DM_ETH_PHY))
304 priv->phyaddr = eth_phy_get_addr(dev);
305
306 /*
307 * Set address of PCS/PMA PHY to the one pointed by phy-handle for
308 * backward compatibility.
309 */
310 if (priv->phyaddr != -1 && priv->pcsaddr == 0)
311 priv->pcsaddr = priv->phyaddr;
312
313 if (priv->phyaddr == -1) {
314 /* Detect the PHY address */
315 for (i = 31; i >= 0; i--) {
316 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
317 if (!ret && (phyreg != 0xFFFF) &&
318 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
319 /* Found a valid PHY address */
320 priv->phyaddr = i;
321 debug("axiemac: Found valid phy address, %x\n",
322 i);
323 break;
324 }
325 }
326 }
327
328 /* Interface - look at tsec */
329 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
330 if (IS_ERR_OR_NULL(phydev)) {
331 dev_err(dev, "phy_connect() failed\n");
332 return -ENODEV;
333 }
334
335 phydev->supported &= supported;
336 phydev->advertising = phydev->supported;
337 priv->phydev = phydev;
338 if (priv->phy_of_handle)
339 priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
340 phy_config(phydev);
341
342 return 0;
343 }
344
pcs_pma_startup(struct axidma_priv * priv)345 static int pcs_pma_startup(struct axidma_priv *priv)
346 {
347 u32 rc, retry_cnt = 0;
348 u16 mii_reg;
349
350 rc = phyread(priv, priv->pcsaddr, MII_BMCR, &mii_reg);
351 if (rc)
352 goto failed_mdio;
353
354 if (!(mii_reg & BMCR_ANENABLE)) {
355 mii_reg |= BMCR_ANENABLE;
356 if (phywrite(priv, priv->pcsaddr, MII_BMCR, mii_reg))
357 goto failed_mdio;
358 }
359
360 /*
361 * Check the internal PHY status and warn user if the link between it
362 * and the external PHY is not obtained.
363 */
364 debug("axiemac: waiting for link status of the PCS/PMA PHY");
365 while (retry_cnt * 10 < PHY_ANEG_TIMEOUT) {
366 rc = phyread(priv, priv->pcsaddr, MII_BMSR, &mii_reg);
367 if ((mii_reg & BMSR_LSTATUS) && mii_reg != 0xffff && !rc) {
368 debug(".Done\n");
369 return 0;
370 }
371 if ((retry_cnt++ % 10) == 0)
372 debug(".");
373 mdelay(10);
374 }
375 debug("\n");
376 printf("axiemac: Warning, PCS/PMA PHY@%d is not ready, link is down\n",
377 priv->pcsaddr);
378 return 1;
379 failed_mdio:
380 printf("axiemac: MDIO to the PCS/PMA PHY has failed\n");
381 return 1;
382 }
383
384 /* Setting axi emac and phy to proper setting */
setup_phy(struct udevice * dev)385 static int setup_phy(struct udevice *dev)
386 {
387 u16 temp;
388 u32 speed, emmc_reg, ret;
389 struct axidma_priv *priv = dev_get_priv(dev);
390 struct axi_regs *regs = priv->iobase;
391 struct phy_device *phydev = priv->phydev;
392
393 if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
394 /*
395 * In SGMII cases the isolate bit might set
396 * after DMA and ethernet resets and hence
397 * check and clear if set.
398 */
399 ret = phyread(priv, priv->pcsaddr, MII_BMCR, &temp);
400 if (ret)
401 return 0;
402 if (temp & BMCR_ISOLATE) {
403 temp &= ~BMCR_ISOLATE;
404 ret = phywrite(priv, priv->pcsaddr, MII_BMCR, temp);
405 if (ret)
406 return 0;
407 }
408 }
409
410 if (phy_startup(phydev)) {
411 printf("axiemac: could not initialize PHY %s\n",
412 phydev->dev->name);
413 return 0;
414 }
415 if (priv->interface == PHY_INTERFACE_MODE_SGMII ||
416 priv->interface == PHY_INTERFACE_MODE_1000BASEX) {
417 if (pcs_pma_startup(priv))
418 return 0;
419 }
420 if (!phydev->link) {
421 printf("%s: No link.\n", phydev->dev->name);
422 return 0;
423 }
424
425 switch (phydev->speed) {
426 case 1000:
427 speed = XAE_EMMC_LINKSPD_1000;
428 break;
429 case 100:
430 speed = XAE_EMMC_LINKSPD_100;
431 break;
432 case 10:
433 speed = XAE_EMMC_LINKSPD_10;
434 break;
435 default:
436 return 0;
437 }
438
439 /* Setup the emac for the phy speed */
440 emmc_reg = readl(®s->emmc);
441 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
442 emmc_reg |= speed;
443
444 /* Write new speed setting out to Axi Ethernet */
445 writel(emmc_reg, ®s->emmc);
446
447 /*
448 * Setting the operating speed of the MAC needs a delay. There
449 * doesn't seem to be register to poll, so please consider this
450 * during your application design.
451 */
452 udelay(1);
453
454 return 1;
455 }
456
457 /* STOP DMA transfers */
axiemac_stop(struct udevice * dev)458 static void axiemac_stop(struct udevice *dev)
459 {
460 struct axidma_priv *priv = dev_get_priv(dev);
461 u32 temp;
462
463 /* Stop the hardware */
464 temp = readl(&priv->dmatx->control);
465 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
466 writel(temp, &priv->dmatx->control);
467
468 temp = readl(&priv->dmarx->control);
469 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
470 writel(temp, &priv->dmarx->control);
471
472 debug("axiemac: Halted\n");
473 }
474
xxv_axi_ethernet_init(struct axidma_priv * priv)475 static int xxv_axi_ethernet_init(struct axidma_priv *priv)
476 {
477 struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase;
478
479 writel(readl(®s->rcw1) | XXV_RCW1_FCS_MASK, ®s->rcw1);
480 writel(readl(®s->tc) | XXV_TC_FCS_MASK, ®s->tc);
481 writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc);
482 writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1);
483
484 return 0;
485 }
486
axi_ethernet_init(struct axidma_priv * priv)487 static int axi_ethernet_init(struct axidma_priv *priv)
488 {
489 struct axi_regs *regs = priv->iobase;
490 int err;
491
492 /*
493 * Check the status of the MgtRdy bit in the interrupt status
494 * registers. This must be done to allow the MGT clock to become stable
495 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
496 * will be valid until this bit is valid.
497 * The bit is always a 1 for all other PHY interfaces.
498 * Interrupt status and enable registers are not available in non
499 * processor mode and hence bypass in this mode
500 */
501 if (!priv->eth_hasnobuf) {
502 err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK,
503 true, 200, false);
504 if (err) {
505 printf("%s: Timeout\n", __func__);
506 return 1;
507 }
508
509 /*
510 * Stop the device and reset HW
511 * Disable interrupts
512 */
513 writel(0, ®s->ie);
514 }
515
516 /* Disable the receiver */
517 writel(readl(®s->rcw1) & ~XAE_RCW1_RX_MASK, ®s->rcw1);
518
519 /*
520 * Stopping the receiver in mid-packet causes a dropped packet
521 * indication from HW. Clear it.
522 */
523 if (!priv->eth_hasnobuf) {
524 /* Set the interrupt status register to clear the interrupt */
525 writel(XAE_INT_RXRJECT_MASK, ®s->is);
526 }
527
528 /* Setup HW */
529 /* Set default MDIO divisor */
530 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
531
532 debug("axiemac: InitHw done\n");
533 return 0;
534 }
535
axiemac_write_hwaddr(struct udevice * dev)536 static int axiemac_write_hwaddr(struct udevice *dev)
537 {
538 struct eth_pdata *pdata = dev_get_plat(dev);
539 struct axidma_priv *priv = dev_get_priv(dev);
540 struct axi_regs *regs = priv->iobase;
541
542 if (priv->mactype != EMAC_1G)
543 return 0;
544
545 /* Set the MAC address */
546 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
547 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
548 writel(val, ®s->uaw0);
549
550 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
551 val |= readl(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
552 writel(val, ®s->uaw1);
553 return 0;
554 }
555
556 /* Reset DMA engine */
axi_dma_init(struct axidma_priv * priv)557 static void axi_dma_init(struct axidma_priv *priv)
558 {
559 u32 timeout = 500;
560
561 /* Reset the engine so the hardware starts from a known state */
562 writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
563 writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
564
565 /* At the initialization time, hardware should finish reset quickly */
566 while (timeout--) {
567 /* Check transmit/receive channel */
568 /* Reset is done when the reset bit is low */
569 if (!((readl(&priv->dmatx->control) |
570 readl(&priv->dmarx->control))
571 & XAXIDMA_CR_RESET_MASK)) {
572 break;
573 }
574 }
575 if (!timeout)
576 printf("%s: Timeout\n", __func__);
577 }
578
axiemac_start(struct udevice * dev)579 static int axiemac_start(struct udevice *dev)
580 {
581 struct axidma_priv *priv = dev_get_priv(dev);
582 u32 temp;
583
584 debug("axiemac: Init started\n");
585 /*
586 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
587 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
588 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
589 * would ensure a reset of AxiEthernet.
590 */
591 axi_dma_init(priv);
592
593 /* Initialize AxiEthernet hardware. */
594 if (priv->mactype == EMAC_1G) {
595 if (axi_ethernet_init(priv))
596 return -1;
597 } else {
598 if (xxv_axi_ethernet_init(priv))
599 return -1;
600 }
601
602 /* Disable all RX interrupts before RxBD space setup */
603 temp = readl(&priv->dmarx->control);
604 temp &= ~XAXIDMA_IRQ_ALL_MASK;
605 writel(temp, &priv->dmarx->control);
606
607 /* Start DMA RX channel. Now it's ready to receive data.*/
608 axienet_dma_write(&rx_bd, &priv->dmarx->current);
609
610 /* Setup the BD. */
611 memset(&rx_bd, 0, sizeof(rx_bd));
612 rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
613 rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
614 #if defined(CONFIG_PHYS_64BIT)
615 rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
616 rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
617 #endif
618 rx_bd.cntrl = sizeof(rxframe);
619 /* Flush the last BD so DMA core could see the updates */
620 flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
621
622 /* It is necessary to flush rxframe because if you don't do it
623 * then cache can contain uninitialized data */
624 flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
625
626 /* Start the hardware */
627 temp = readl(&priv->dmarx->control);
628 temp |= XAXIDMA_CR_RUNSTOP_MASK;
629 writel(temp, &priv->dmarx->control);
630
631 /* Rx BD is ready - start */
632 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
633
634 if (priv->mactype == EMAC_1G) {
635 struct axi_regs *regs = priv->iobase;
636 /* Enable TX */
637 writel(XAE_TC_TX_MASK, ®s->tc);
638 /* Enable RX */
639 writel(XAE_RCW1_RX_MASK, ®s->rcw1);
640
641 /* PHY setup */
642 if (!setup_phy(dev)) {
643 axiemac_stop(dev);
644 return -1;
645 }
646 } else {
647 struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase;
648 /* Enable TX */
649 writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc);
650
651 /* Enable RX */
652 writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1);
653 }
654
655 debug("axiemac: Init complete\n");
656 return 0;
657 }
658
axiemac_send(struct udevice * dev,void * ptr,int len)659 static int axiemac_send(struct udevice *dev, void *ptr, int len)
660 {
661 struct axidma_priv *priv = dev_get_priv(dev);
662 u32 timeout;
663
664 if (len > PKTSIZE_ALIGN)
665 len = PKTSIZE_ALIGN;
666
667 /* If size is less than min packet size, pad to min size */
668 if (priv->mactype == EMAC_10G_25G && len < XXV_MIN_PKT_SIZE) {
669 memset(txminframe, 0, XXV_MIN_PKT_SIZE);
670 memcpy(txminframe, ptr, len);
671 len = XXV_MIN_PKT_SIZE;
672 ptr = txminframe;
673 }
674
675 /* Flush packet to main memory to be trasfered by DMA */
676 flush_cache((phys_addr_t)ptr, len);
677
678 /* Setup Tx BD */
679 memset(&tx_bd, 0, sizeof(tx_bd));
680 /* At the end of the ring, link the last BD back to the top */
681 tx_bd.next_desc = lower_32_bits((unsigned long)&tx_bd);
682 tx_bd.buf_addr = lower_32_bits((unsigned long)ptr);
683 #if defined(CONFIG_PHYS_64BIT)
684 tx_bd.next_desc_msb = upper_32_bits((unsigned long)&tx_bd);
685 tx_bd.buf_addr_msb = upper_32_bits((unsigned long)ptr);
686 #endif
687 /* Save len */
688 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
689 XAXIDMA_BD_CTRL_TXEOF_MASK;
690
691 /* Flush the last BD so DMA core could see the updates */
692 flush_cache((phys_addr_t)&tx_bd, sizeof(tx_bd));
693
694 if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
695 u32 temp;
696 axienet_dma_write(&tx_bd, &priv->dmatx->current);
697 /* Start the hardware */
698 temp = readl(&priv->dmatx->control);
699 temp |= XAXIDMA_CR_RUNSTOP_MASK;
700 writel(temp, &priv->dmatx->control);
701 }
702
703 /* Start transfer */
704 axienet_dma_write(&tx_bd, &priv->dmatx->tail);
705
706 /* Wait for transmission to complete */
707 debug("axiemac: Waiting for tx to be done\n");
708 timeout = 200;
709 while (timeout && (!(readl(&priv->dmatx->status) &
710 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
711 timeout--;
712 udelay(1);
713 }
714 if (!timeout) {
715 printf("%s: Timeout\n", __func__);
716 return 1;
717 }
718
719 debug("axiemac: Sending complete\n");
720 return 0;
721 }
722
isrxready(struct axidma_priv * priv)723 static int isrxready(struct axidma_priv *priv)
724 {
725 u32 status;
726
727 /* Read pending interrupts */
728 status = readl(&priv->dmarx->status);
729
730 /* Acknowledge pending interrupts */
731 writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
732
733 /*
734 * If Reception done interrupt is asserted, call RX call back function
735 * to handle the processed BDs and then raise the according flag.
736 */
737 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
738 return 1;
739
740 return 0;
741 }
742
axiemac_recv(struct udevice * dev,int flags,uchar ** packetp)743 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
744 {
745 u32 length;
746 struct axidma_priv *priv = dev_get_priv(dev);
747 u32 temp;
748
749 /* Wait for an incoming packet */
750 if (!isrxready(priv))
751 return -1;
752
753 debug("axiemac: RX data ready\n");
754
755 /* Disable IRQ for a moment till packet is handled */
756 temp = readl(&priv->dmarx->control);
757 temp &= ~XAXIDMA_IRQ_ALL_MASK;
758 writel(temp, &priv->dmarx->control);
759 if (!priv->eth_hasnobuf && priv->mactype == EMAC_1G)
760 length = rx_bd.app4 & 0xFFFF; /* max length mask */
761 else
762 length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
763
764 #ifdef DEBUG
765 print_buffer(&rxframe, &rxframe[0], 1, length, 16);
766 #endif
767
768 *packetp = rxframe;
769 return length;
770 }
771
axiemac_free_pkt(struct udevice * dev,uchar * packet,int length)772 static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
773 {
774 struct axidma_priv *priv = dev_get_priv(dev);
775
776 #ifdef DEBUG
777 /* It is useful to clear buffer to be sure that it is consistent */
778 memset(rxframe, 0, sizeof(rxframe));
779 #endif
780 /* Setup RxBD */
781 /* Clear the whole buffer and setup it again - all flags are cleared */
782 memset(&rx_bd, 0, sizeof(rx_bd));
783 rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
784 rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
785 #if defined(CONFIG_PHYS_64BIT)
786 rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
787 rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
788 #endif
789 rx_bd.cntrl = sizeof(rxframe);
790
791 /* Write bd to HW */
792 flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
793
794 /* It is necessary to flush rxframe because if you don't do it
795 * then cache will contain previous packet */
796 flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
797
798 /* Rx BD is ready - start again */
799 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
800
801 debug("axiemac: RX completed, framelength = %d\n", length);
802
803 return 0;
804 }
805
axiemac_miiphy_read(struct mii_dev * bus,int addr,int devad,int reg)806 static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
807 int devad, int reg)
808 {
809 int ret;
810 u16 value;
811
812 ret = phyread(bus->priv, addr, reg, &value);
813 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
814 value, ret);
815 return value;
816 }
817
axiemac_miiphy_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)818 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
819 int reg, u16 value)
820 {
821 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
822 return phywrite(bus->priv, addr, reg, value);
823 }
824
axi_emac_probe(struct udevice * dev)825 static int axi_emac_probe(struct udevice *dev)
826 {
827 struct axidma_plat *plat = dev_get_plat(dev);
828 struct eth_pdata *pdata = &plat->eth_pdata;
829 struct axidma_priv *priv = dev_get_priv(dev);
830 int ret;
831
832 priv->iobase = (struct axi_regs *)pdata->iobase;
833 priv->dmatx = plat->dmatx;
834 /* RX channel offset is 0x30 */
835 priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
836 priv->mactype = plat->mactype;
837
838 if (priv->mactype == EMAC_1G) {
839 priv->eth_hasnobuf = plat->eth_hasnobuf;
840 priv->pcsaddr = plat->pcsaddr;
841 priv->phyaddr = plat->phyaddr;
842 priv->phy_of_handle = plat->phy_of_handle;
843 priv->interface = pdata->phy_interface;
844
845 if (IS_ENABLED(CONFIG_DM_ETH_PHY))
846 priv->bus = eth_phy_get_mdio_bus(dev);
847
848 if (!priv->bus) {
849 priv->bus = mdio_alloc();
850 priv->bus->read = axiemac_miiphy_read;
851 priv->bus->write = axiemac_miiphy_write;
852 priv->bus->priv = priv;
853
854 ret = mdio_register_seq(priv->bus, dev_seq(dev));
855 if (ret)
856 return ret;
857 }
858
859 if (IS_ENABLED(CONFIG_DM_ETH_PHY))
860 eth_phy_set_mdio_bus(dev, priv->bus);
861
862 axiemac_phy_init(dev);
863 }
864
865 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase,
866 priv->phyaddr, phy_string_for_interface(pdata->phy_interface));
867
868 return 0;
869 }
870
axi_emac_remove(struct udevice * dev)871 static int axi_emac_remove(struct udevice *dev)
872 {
873 struct axidma_priv *priv = dev_get_priv(dev);
874
875 if (priv->mactype == EMAC_1G) {
876 free(priv->phydev);
877 mdio_unregister(priv->bus);
878 mdio_free(priv->bus);
879 }
880
881 return 0;
882 }
883
884 static const struct eth_ops axi_emac_ops = {
885 .start = axiemac_start,
886 .send = axiemac_send,
887 .recv = axiemac_recv,
888 .free_pkt = axiemac_free_pkt,
889 .stop = axiemac_stop,
890 .write_hwaddr = axiemac_write_hwaddr,
891 };
892
axi_emac_of_to_plat(struct udevice * dev)893 static int axi_emac_of_to_plat(struct udevice *dev)
894 {
895 struct axidma_plat *plat = dev_get_plat(dev);
896 struct eth_pdata *pdata = &plat->eth_pdata;
897 int node = dev_of_offset(dev);
898 int offset = 0;
899
900 pdata->iobase = dev_read_addr(dev);
901 plat->mactype = dev_get_driver_data(dev);
902
903 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
904 "axistream-connected");
905 if (offset <= 0) {
906 printf("%s: axistream is not found\n", __func__);
907 return -EINVAL;
908 }
909 plat->dmatx = (struct axidma_reg *)fdtdec_get_addr_size_auto_parent
910 (gd->fdt_blob, 0, offset, "reg", 0, NULL, false);
911 if (!plat->dmatx) {
912 printf("%s: axi_dma register space not found\n", __func__);
913 return -EINVAL;
914 }
915
916 if (plat->mactype == EMAC_1G) {
917 plat->phyaddr = -1;
918 /* PHYAD 0 always redirects to the PCS/PMA PHY */
919 plat->pcsaddr = 0;
920
921 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
922 "phy-handle");
923 if (offset > 0) {
924 if (!(IS_ENABLED(CONFIG_DM_ETH_PHY)))
925 plat->phyaddr = fdtdec_get_int(gd->fdt_blob,
926 offset,
927 "reg", -1);
928 plat->phy_of_handle = offset;
929 }
930
931 pdata->phy_interface = dev_read_phy_mode(dev);
932 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
933 return -EINVAL;
934
935 plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
936 "xlnx,eth-hasnobuf");
937
938 if (pdata->phy_interface == PHY_INTERFACE_MODE_SGMII ||
939 pdata->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
940 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
941 "pcs-handle");
942 if (offset > 0) {
943 plat->pcsaddr = fdtdec_get_int(gd->fdt_blob,
944 offset, "reg", -1);
945 }
946 }
947 }
948
949 return 0;
950 }
951
952 static const struct udevice_id axi_emac_ids[] = {
953 { .compatible = "xlnx,axi-ethernet-1.00.a", .data = (uintptr_t)EMAC_1G },
954 { .compatible = "xlnx,xxv-ethernet-1.0", .data = (uintptr_t)EMAC_10G_25G },
955 { }
956 };
957
958 U_BOOT_DRIVER(axi_emac) = {
959 .name = "axi_emac",
960 .id = UCLASS_ETH,
961 .of_match = axi_emac_ids,
962 .of_to_plat = axi_emac_of_to_plat,
963 .probe = axi_emac_probe,
964 .remove = axi_emac_remove,
965 .ops = &axi_emac_ops,
966 .priv_auto = sizeof(struct axidma_priv),
967 .plat_auto = sizeof(struct axidma_plat),
968 };
969