1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * PCI autoconfiguration library
4 *
5 * Author: Matt Porter <mporter@mvista.com>
6 *
7 * Copyright 2000 MontaVista Software Inc.
8 * Copyright (c) 2021 Maciej W. Rozycki <macro@orcam.me.uk>
9 */
10
11 #include <common.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <log.h>
15 #include <pci.h>
16 #include <time.h>
17 #include "pci_internal.h"
18
19 /* the user can define CFG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
20 #ifndef CFG_SYS_PCI_CACHE_LINE_SIZE
21 #define CFG_SYS_PCI_CACHE_LINE_SIZE 8
22 #endif
23
dm_pciauto_setup_device(struct udevice * dev,struct pci_region * mem,struct pci_region * prefetch,struct pci_region * io)24 static void dm_pciauto_setup_device(struct udevice *dev,
25 struct pci_region *mem,
26 struct pci_region *prefetch,
27 struct pci_region *io)
28 {
29 u32 bar_response;
30 pci_size_t bar_size;
31 u16 cmdstat = 0;
32 int bar, bar_nr = 0;
33 int bars_num;
34 u8 header_type;
35 int rom_addr;
36 pci_addr_t bar_value;
37 struct pci_region *bar_res = NULL;
38 int found_mem64 = 0;
39 u16 class;
40
41 dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
42 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
43 PCI_COMMAND_MASTER;
44
45 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
46 header_type &= 0x7f;
47
48 switch (header_type) {
49 case PCI_HEADER_TYPE_NORMAL:
50 bars_num = 6;
51 break;
52 case PCI_HEADER_TYPE_BRIDGE:
53 bars_num = 2;
54 break;
55 case PCI_HEADER_TYPE_CARDBUS:
56 /* CardBus header does not have any BAR */
57 bars_num = 0;
58 break;
59 default:
60 /* Skip configuring BARs for unknown header types */
61 bars_num = 0;
62 break;
63 }
64
65 for (bar = PCI_BASE_ADDRESS_0;
66 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
67 int ret = 0;
68
69 /* Tickle the BAR and get the response */
70 dm_pci_write_config32(dev, bar, 0xffffffff);
71 dm_pci_read_config32(dev, bar, &bar_response);
72
73 /* If BAR is not implemented (or invalid) go to the next BAR */
74 if (!bar_response || bar_response == 0xffffffff)
75 continue;
76
77 found_mem64 = 0;
78
79 /* Check the BAR type and set our address mask */
80 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
81 bar_size = bar_response & PCI_BASE_ADDRESS_IO_MASK;
82 bar_size &= ~(bar_size - 1);
83
84 bar_res = io;
85
86 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
87 bar_nr, (unsigned long long)bar_size);
88 } else {
89 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
90 PCI_BASE_ADDRESS_MEM_TYPE_64) {
91 u32 bar_response_upper;
92 u64 bar64;
93
94 dm_pci_write_config32(dev, bar + 4, 0xffffffff);
95 dm_pci_read_config32(dev, bar + 4,
96 &bar_response_upper);
97
98 bar64 = ((u64)bar_response_upper << 32) |
99 bar_response;
100
101 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
102 + 1;
103 found_mem64 = 1;
104 } else {
105 bar_size = (u32)(~(bar_response &
106 PCI_BASE_ADDRESS_MEM_MASK) + 1);
107 }
108
109 if (prefetch &&
110 (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
111 bar_res = prefetch;
112 else
113 bar_res = mem;
114
115 debug("PCI Autoconfig: BAR %d, %s%s, size=0x%llx, ",
116 bar_nr, bar_res == prefetch ? "Prf" : "Mem",
117 found_mem64 ? "64" : "",
118 (unsigned long long)bar_size);
119 }
120
121 ret = pciauto_region_allocate(bar_res, bar_size,
122 &bar_value, found_mem64);
123 if (ret)
124 printf("PCI: Failed autoconfig bar %x\n", bar);
125
126 if (!ret) {
127 /* Write it out and update our limit */
128 dm_pci_write_config32(dev, bar, (u32)bar_value);
129
130 if (found_mem64) {
131 bar += 4;
132 #ifdef CONFIG_SYS_PCI_64BIT
133 dm_pci_write_config32(dev, bar,
134 (u32)(bar_value >> 32));
135 #else
136 /*
137 * If we are a 64-bit decoder then increment to
138 * the upper 32 bits of the bar and force it to
139 * locate in the lower 4GB of memory.
140 */
141 dm_pci_write_config32(dev, bar, 0x00000000);
142 #endif
143 }
144 }
145
146 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
147 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
148
149 debug("\n");
150
151 bar_nr++;
152 }
153
154 /* Configure the expansion ROM address */
155 if (header_type == PCI_HEADER_TYPE_NORMAL ||
156 header_type == PCI_HEADER_TYPE_BRIDGE) {
157 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
158 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
159 dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
160 dm_pci_read_config32(dev, rom_addr, &bar_response);
161 if (bar_response) {
162 bar_size = -(bar_response & ~1);
163 debug("PCI Autoconfig: ROM, size=%#x, ",
164 (unsigned int)bar_size);
165 if (pciauto_region_allocate(mem, bar_size, &bar_value,
166 false) == 0) {
167 dm_pci_write_config32(dev, rom_addr, bar_value);
168 }
169 cmdstat |= PCI_COMMAND_MEMORY;
170 debug("\n");
171 }
172 }
173
174 /* PCI_COMMAND_IO must be set for VGA device */
175 dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
176 if (class == PCI_CLASS_DISPLAY_VGA)
177 cmdstat |= PCI_COMMAND_IO;
178
179 dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
180 dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
181 CFG_SYS_PCI_CACHE_LINE_SIZE);
182 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
183 }
184
185 /*
186 * Check if the link of a downstream PCIe port operates correctly.
187 *
188 * For that check if the optional Data Link Layer Link Active status gets
189 * on within a 200ms period or failing that wait until the completion of
190 * that period and check if link training has shown the completed status
191 * continuously throughout the second half of that period.
192 *
193 * Observation with the ASMedia ASM2824 Gen 3 switch indicates it takes
194 * 11-44ms to indicate the Data Link Layer Link Active status at 2.5GT/s,
195 * though it may take a couple of link training iterations.
196 */
dm_pciauto_exp_link_stable(struct udevice * dev,int pcie_off)197 static bool dm_pciauto_exp_link_stable(struct udevice *dev, int pcie_off)
198 {
199 u64 loops = 0, trcount = 0, ntrcount = 0, flips = 0;
200 bool dllla, lnktr, plnktr;
201 u16 exp_lnksta;
202 pci_dev_t bdf;
203 u64 end;
204
205 dm_pci_read_config16(dev, pcie_off + PCI_EXP_LNKSTA, &exp_lnksta);
206 plnktr = !!(exp_lnksta & PCI_EXP_LNKSTA_LT);
207
208 end = get_ticks() + usec_to_tick(200000);
209 do {
210 dm_pci_read_config16(dev, pcie_off + PCI_EXP_LNKSTA,
211 &exp_lnksta);
212 dllla = !!(exp_lnksta & PCI_EXP_LNKSTA_DLLLA);
213 lnktr = !!(exp_lnksta & PCI_EXP_LNKSTA_LT);
214
215 flips += plnktr ^ lnktr;
216 if (lnktr) {
217 ntrcount = 0;
218 trcount++;
219 } else {
220 ntrcount++;
221 }
222 loops++;
223
224 plnktr = lnktr;
225 } while (!dllla && get_ticks() < end);
226
227 bdf = dm_pci_get_bdf(dev);
228 debug("PCI Autoconfig: %02x.%02x.%02x: Fixup link: DL active: %u; "
229 "%3llu flips, %6llu loops of which %6llu while training, "
230 "final %6llu stable\n",
231 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf),
232 (unsigned int)dllla,
233 (unsigned long long)flips, (unsigned long long)loops,
234 (unsigned long long)trcount, (unsigned long long)ntrcount);
235
236 return dllla || ntrcount >= loops / 2;
237 }
238
239 /*
240 * Retrain the link of a downstream PCIe port by hand if necessary.
241 *
242 * This is needed at least where a downstream port of the ASMedia ASM2824
243 * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304
244 * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 >
245 * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched
246 * board.
247 *
248 * In such a configuration the switches are supposed to negotiate the link
249 * speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link
250 * continues switching between the two speeds indefinitely and the data
251 * link layer never reaches the active state, with link training reported
252 * repeatedly active ~84% of the time. Forcing the target link speed to
253 * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to
254 * each other correctly however. And more interestingly retraining with a
255 * higher target link speed afterwards lets the two successfully negotiate
256 * 5.0GT/s.
257 *
258 * As this can potentially happen with any device and is cheap in the case
259 * of correctly operating hardware, let's do it for all downstream ports,
260 * for root complexes, PCIe switches and PCI/PCI-X to PCIe bridges.
261 *
262 * First check if automatic link training may have failed to complete, as
263 * indicated by the optional Data Link Layer Link Active status being off
264 * and the Link Bandwidth Management Status indicating that hardware has
265 * changed the link speed or width in an attempt to correct unreliable
266 * link operation. If this is the case, then check if the link operates
267 * correctly by seeing whether it is being trained excessively. If it is,
268 * then conclude the link is broken.
269 *
270 * In that case restrict the speed to 2.5GT/s, observing that the Target
271 * Link Speed field is sticky and therefore the link will stay restricted
272 * even after a device reset is later made by an OS that is unaware of the
273 * problem. With the speed restricted request that the link be retrained
274 * and check again if the link operates correctly. If not, then set the
275 * Target Link Speed back to the original value.
276 *
277 * This requires the presence of the Link Control 2 register, so make sure
278 * the PCI Express Capability Version is at least 2. Also don't try, for
279 * obvious reasons, to limit the speed if 2.5GT/s is the only link speed
280 * supported.
281 */
dm_pciauto_exp_fixup_link(struct udevice * dev,int pcie_off)282 static void dm_pciauto_exp_fixup_link(struct udevice *dev, int pcie_off)
283 {
284 u16 exp_lnksta, exp_lnkctl, exp_lnkctl2;
285 u16 exp_flags, exp_type, exp_version;
286 u32 exp_lnkcap;
287 pci_dev_t bdf;
288
289 dm_pci_read_config16(dev, pcie_off + PCI_EXP_FLAGS, &exp_flags);
290 exp_version = exp_flags & PCI_EXP_FLAGS_VERS;
291 if (exp_version < 2)
292 return;
293
294 exp_type = (exp_flags & PCI_EXP_FLAGS_TYPE) >> 4;
295 switch (exp_type) {
296 case PCI_EXP_TYPE_ROOT_PORT:
297 case PCI_EXP_TYPE_DOWNSTREAM:
298 case PCI_EXP_TYPE_PCIE_BRIDGE:
299 break;
300 default:
301 return;
302 }
303
304 dm_pci_read_config32(dev, pcie_off + PCI_EXP_LNKCAP, &exp_lnkcap);
305 if ((exp_lnkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
306 return;
307
308 dm_pci_read_config16(dev, pcie_off + PCI_EXP_LNKSTA, &exp_lnksta);
309 if ((exp_lnksta & (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_DLLLA)) !=
310 PCI_EXP_LNKSTA_LBMS)
311 return;
312
313 if (dm_pciauto_exp_link_stable(dev, pcie_off))
314 return;
315
316 bdf = dm_pci_get_bdf(dev);
317 printf("PCI Autoconfig: %02x.%02x.%02x: "
318 "Downstream link non-functional\n",
319 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
320 printf("PCI Autoconfig: %02x.%02x.%02x: "
321 "Retrying with speed restricted to 2.5GT/s...\n",
322 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
323
324 dm_pci_read_config16(dev, pcie_off + PCI_EXP_LNKCTL, &exp_lnkctl);
325 dm_pci_read_config16(dev, pcie_off + PCI_EXP_LNKCTL2, &exp_lnkctl2);
326
327 dm_pci_write_config16(dev, pcie_off + PCI_EXP_LNKCTL2,
328 (exp_lnkctl2 & ~PCI_EXP_LNKCTL2_TLS) |
329 PCI_EXP_LNKCTL2_TLS_2_5GT);
330 dm_pci_write_config16(dev, pcie_off + PCI_EXP_LNKCTL,
331 exp_lnkctl | PCI_EXP_LNKCTL_RL);
332
333 if (dm_pciauto_exp_link_stable(dev, pcie_off)) {
334 printf("PCI Autoconfig: %02x.%02x.%02x: Succeeded!\n",
335 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
336 } else {
337 printf("PCI Autoconfig: %02x.%02x.%02x: Failed!\n",
338 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
339
340 dm_pci_write_config16(dev, pcie_off + PCI_EXP_LNKCTL2,
341 exp_lnkctl2);
342 dm_pci_write_config16(dev, pcie_off + PCI_EXP_LNKCTL,
343 exp_lnkctl | PCI_EXP_LNKCTL_RL);
344 }
345 }
346
dm_pciauto_prescan_setup_bridge(struct udevice * dev,int sub_bus)347 void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
348 {
349 struct pci_region *pci_mem;
350 struct pci_region *pci_prefetch;
351 struct pci_region *pci_io;
352 u16 cmdstat, prefechable_64;
353 u8 io_32;
354 struct udevice *ctlr = pci_get_controller(dev);
355 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
356 int pcie_off;
357
358 pci_mem = ctlr_hose->pci_mem;
359 pci_prefetch = ctlr_hose->pci_prefetch;
360 pci_io = ctlr_hose->pci_io;
361
362 dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
363 dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
364 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
365 dm_pci_read_config8(dev, PCI_IO_BASE, &io_32);
366 io_32 &= PCI_IO_RANGE_TYPE_MASK;
367
368 /* Configure bus number registers */
369 dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
370 PCI_BUS(dm_pci_get_bdf(dev)) - dev_seq(ctlr));
371 dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - dev_seq(ctlr));
372 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
373
374 if (pci_mem) {
375 /* Round memory allocator to 1MB boundary */
376 pciauto_region_align(pci_mem, 0x100000);
377
378 /*
379 * Set up memory and I/O filter limits, assume 32-bit
380 * I/O space
381 */
382 dm_pci_write_config16(dev, PCI_MEMORY_BASE,
383 ((pci_mem->bus_lower & 0xfff00000) >> 16) &
384 PCI_MEMORY_RANGE_MASK);
385
386 cmdstat |= PCI_COMMAND_MEMORY;
387 }
388
389 if (pci_prefetch) {
390 /* Round memory allocator to 1MB boundary */
391 pciauto_region_align(pci_prefetch, 0x100000);
392
393 /*
394 * Set up memory and I/O filter limits, assume 32-bit
395 * I/O space
396 */
397 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
398 (((pci_prefetch->bus_lower & 0xfff00000) >> 16) &
399 PCI_PREF_RANGE_MASK) | prefechable_64);
400 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
401 #ifdef CONFIG_SYS_PCI_64BIT
402 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
403 pci_prefetch->bus_lower >> 32);
404 #else
405 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
406 #endif
407
408 cmdstat |= PCI_COMMAND_MEMORY;
409 } else {
410 /* We don't support prefetchable memory for now, so disable */
411 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0xfff0 |
412 prefechable_64);
413 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 |
414 prefechable_64);
415 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
416 dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
417 dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
418 }
419 }
420
421 if (pci_io) {
422 /* Round I/O allocator to 4KB boundary */
423 pciauto_region_align(pci_io, 0x1000);
424
425 dm_pci_write_config8(dev, PCI_IO_BASE,
426 (((pci_io->bus_lower & 0x0000f000) >> 8) &
427 PCI_IO_RANGE_MASK) | io_32);
428 if (io_32 == PCI_IO_RANGE_TYPE_32)
429 dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
430 (pci_io->bus_lower & 0xffff0000) >> 16);
431
432 cmdstat |= PCI_COMMAND_IO;
433 } else {
434 /* Disable I/O if unsupported */
435 dm_pci_write_config8(dev, PCI_IO_BASE, 0xf0 | io_32);
436 dm_pci_write_config8(dev, PCI_IO_LIMIT, 0x0 | io_32);
437 if (io_32 == PCI_IO_RANGE_TYPE_32) {
438 dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, 0x0);
439 dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 0x0);
440 }
441 }
442
443 /* For PCIe devices see if we need to retrain the link by hand */
444 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
445 if (pcie_off)
446 dm_pciauto_exp_fixup_link(dev, pcie_off);
447
448 /* Enable memory and I/O accesses, enable bus master */
449 dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
450 }
451
dm_pciauto_postscan_setup_bridge(struct udevice * dev,int sub_bus)452 void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
453 {
454 struct pci_region *pci_mem;
455 struct pci_region *pci_prefetch;
456 struct pci_region *pci_io;
457 struct udevice *ctlr = pci_get_controller(dev);
458 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
459
460 pci_mem = ctlr_hose->pci_mem;
461 pci_prefetch = ctlr_hose->pci_prefetch;
462 pci_io = ctlr_hose->pci_io;
463
464 /* Configure bus number registers */
465 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - dev_seq(ctlr));
466
467 if (pci_mem) {
468 /* Round memory allocator to 1MB boundary */
469 pciauto_region_align(pci_mem, 0x100000);
470
471 dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
472 ((pci_mem->bus_lower - 1) >> 16) &
473 PCI_MEMORY_RANGE_MASK);
474 }
475
476 if (pci_prefetch) {
477 u16 prefechable_64;
478
479 dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
480 &prefechable_64);
481 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
482
483 /* Round memory allocator to 1MB boundary */
484 pciauto_region_align(pci_prefetch, 0x100000);
485
486 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
487 (((pci_prefetch->bus_lower - 1) >> 16) &
488 PCI_PREF_RANGE_MASK) | prefechable_64);
489 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
490 #ifdef CONFIG_SYS_PCI_64BIT
491 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
492 (pci_prefetch->bus_lower - 1) >> 32);
493 #else
494 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
495 #endif
496 }
497
498 if (pci_io) {
499 u8 io_32;
500
501 dm_pci_read_config8(dev, PCI_IO_LIMIT,
502 &io_32);
503 io_32 &= PCI_IO_RANGE_TYPE_MASK;
504
505 /* Round I/O allocator to 4KB boundary */
506 pciauto_region_align(pci_io, 0x1000);
507
508 dm_pci_write_config8(dev, PCI_IO_LIMIT,
509 ((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) &
510 PCI_IO_RANGE_MASK) | io_32);
511 if (io_32 == PCI_IO_RANGE_TYPE_32)
512 dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
513 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
514 }
515 }
516
517 /*
518 * HJF: Changed this to return int. I think this is required
519 * to get the correct result when scanning bridges
520 */
dm_pciauto_config_device(struct udevice * dev)521 int dm_pciauto_config_device(struct udevice *dev)
522 {
523 struct pci_region *pci_mem;
524 struct pci_region *pci_prefetch;
525 struct pci_region *pci_io;
526 unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
527 unsigned short class;
528 struct udevice *ctlr = pci_get_controller(dev);
529 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
530 int ret;
531
532 pci_mem = ctlr_hose->pci_mem;
533 pci_prefetch = ctlr_hose->pci_prefetch;
534 pci_io = ctlr_hose->pci_io;
535
536 dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
537
538 switch (class) {
539 case PCI_CLASS_BRIDGE_PCI:
540 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
541 PCI_DEV(dm_pci_get_bdf(dev)));
542
543 dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
544
545 ret = dm_pci_hose_probe_bus(dev);
546 if (ret < 0)
547 return log_msg_ret("probe", ret);
548 sub_bus = ret;
549 break;
550
551 case PCI_CLASS_BRIDGE_CARDBUS:
552 /*
553 * just do a minimal setup of the bridge,
554 * let the OS take care of the rest
555 */
556 dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
557
558 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
559 PCI_DEV(dm_pci_get_bdf(dev)));
560
561 break;
562
563 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
564 case PCI_CLASS_BRIDGE_OTHER:
565 debug("PCI Autoconfig: Skipping bridge device %d\n",
566 PCI_DEV(dm_pci_get_bdf(dev)));
567 break;
568 #endif
569 #if defined(CONFIG_ARCH_MPC834X)
570 case PCI_CLASS_BRIDGE_OTHER:
571 /*
572 * The host/PCI bridge 1 seems broken in 8349 - it presents
573 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
574 * device claiming resources io/mem/irq.. we only allow for
575 * the PIMMR window to be allocated (BAR0 - 1MB size)
576 */
577 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
578 dm_pciauto_setup_device(dev, 0, hose->pci_mem,
579 hose->pci_prefetch, hose->pci_io);
580 break;
581 #endif
582
583 default:
584 dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
585 break;
586 }
587
588 return sub_bus;
589 }
590