1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013 Imagination Technologies
4 * Author: Paul Burton <paul.burton@mips.com>
5 */
6
7 #include <dm.h>
8 #include <init.h>
9 #include <msc01.h>
10 #include <pci.h>
11 #include <pci_msc01.h>
12 #include <asm/io.h>
13
14 #define PCI_ACCESS_READ 0
15 #define PCI_ACCESS_WRITE 1
16
17 struct msc01_pci_controller {
18 struct pci_controller hose;
19 void *base;
20 };
21
22 static inline struct msc01_pci_controller *
hose_to_msc01(struct pci_controller * hose)23 hose_to_msc01(struct pci_controller *hose)
24 {
25 return container_of(hose, struct msc01_pci_controller, hose);
26 }
27
msc01_config_access(struct msc01_pci_controller * msc01,unsigned char access_type,pci_dev_t bdf,int where,u32 * data)28 static int msc01_config_access(struct msc01_pci_controller *msc01,
29 unsigned char access_type, pci_dev_t bdf,
30 int where, u32 *data)
31 {
32 const u32 aborts = MSC01_PCI_INTSTAT_MA_MSK | MSC01_PCI_INTSTAT_TA_MSK;
33 void *intstat = msc01->base + MSC01_PCI_INTSTAT_OFS;
34 void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS;
35 unsigned int bus = PCI_BUS(bdf);
36 unsigned int dev = PCI_DEV(bdf);
37 unsigned int func = PCI_FUNC(bdf);
38
39 /* clear abort status */
40 __raw_writel(aborts, intstat);
41
42 /* setup address */
43 __raw_writel((PCI_CONF1_ADDRESS(bus, dev, func, where) & ~PCI_CONF1_ENABLE),
44 msc01->base + MSC01_PCI_CFGADDR_OFS);
45
46 /* perform access */
47 if (access_type == PCI_ACCESS_WRITE)
48 __raw_writel(*data, cfgdata);
49 else
50 *data = __raw_readl(cfgdata);
51
52 /* check for aborts */
53 if (__raw_readl(intstat) & aborts) {
54 /* clear abort status */
55 __raw_writel(aborts, intstat);
56 return -1;
57 }
58
59 return 0;
60 }
61
msc01_pci_read_config(const struct udevice * dev,pci_dev_t bdf,uint where,ulong * val,enum pci_size_t size)62 static int msc01_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
63 uint where, ulong *val, enum pci_size_t size)
64 {
65 struct msc01_pci_controller *msc01 = dev_get_priv(dev);
66 u32 data = 0;
67
68 if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, &data)) {
69 *val = pci_get_ff(size);
70 return 0;
71 }
72
73 *val = pci_conv_32_to_size(data, where, size);
74
75 return 0;
76 }
77
msc01_pci_write_config(struct udevice * dev,pci_dev_t bdf,uint where,ulong val,enum pci_size_t size)78 static int msc01_pci_write_config(struct udevice *dev, pci_dev_t bdf,
79 uint where, ulong val, enum pci_size_t size)
80 {
81 struct msc01_pci_controller *msc01 = dev_get_priv(dev);
82 u32 data = 0;
83
84 if (size == PCI_SIZE_32) {
85 data = val;
86 } else {
87 u32 old;
88
89 if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, &old))
90 return 0;
91
92 data = pci_conv_size_to_32(old, val, where, size);
93 }
94
95 msc01_config_access(msc01, PCI_ACCESS_WRITE, bdf, where, &data);
96
97 return 0;
98 }
99
msc01_pci_probe(struct udevice * dev)100 static int msc01_pci_probe(struct udevice *dev)
101 {
102 struct msc01_pci_controller *msc01 = dev_get_priv(dev);
103
104 msc01->base = dev_remap_addr(dev);
105 if (!msc01->base)
106 return -EINVAL;
107
108 return 0;
109 }
110
111 static const struct dm_pci_ops msc01_pci_ops = {
112 .read_config = msc01_pci_read_config,
113 .write_config = msc01_pci_write_config,
114 };
115
116 static const struct udevice_id msc01_pci_ids[] = {
117 { .compatible = "mips,pci-msc01" },
118 { }
119 };
120
121 U_BOOT_DRIVER(msc01_pci) = {
122 .name = "msc01_pci",
123 .id = UCLASS_PCI,
124 .of_match = msc01_pci_ids,
125 .ops = &msc01_pci_ops,
126 .probe = msc01_pci_probe,
127 .priv_auto = sizeof(struct msc01_pci_controller),
128 };
129