1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * SH7751 PCI Controller (PCIC) for U-Boot.
4 * (C) Dustin McIntire (dustin@sensoria.com)
5 * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <pci.h>
11 #include <asm/processor.h>
12 #include <asm/io.h>
13 #include <asm/pci.h>
14 #include <linux/bitops.h>
15 #include <linux/delay.h>
16
17 /* Register addresses and such */
18 #define SH7751_BCR1 (vu_long *)0xFF800000
19 #define SH7751_BCR2 (vu_short *)0xFF800004
20 #define SH7751_WCR1 (vu_long *)0xFF800008
21 #define SH7751_WCR2 (vu_long *)0xFF80000C
22 #define SH7751_WCR3 (vu_long *)0xFF800010
23 #define SH7751_MCR (vu_long *)0xFF800014
24 #define SH7751_BCR3 (vu_short *)0xFF800050
25 #define SH7751_PCICONF0 (vu_long *)0xFE200000
26 #define SH7751_PCICONF1 (vu_long *)0xFE200004
27 #define SH7751_PCICONF2 (vu_long *)0xFE200008
28 #define SH7751_PCICONF3 (vu_long *)0xFE20000C
29 #define SH7751_PCICONF4 (vu_long *)0xFE200010
30 #define SH7751_PCICONF5 (vu_long *)0xFE200014
31 #define SH7751_PCICONF6 (vu_long *)0xFE200018
32 #define SH7751_PCICR (vu_long *)0xFE200100
33 #define SH7751_PCILSR0 (vu_long *)0xFE200104
34 #define SH7751_PCILSR1 (vu_long *)0xFE200108
35 #define SH7751_PCILAR0 (vu_long *)0xFE20010C
36 #define SH7751_PCILAR1 (vu_long *)0xFE200110
37 #define SH7751_PCIMBR (vu_long *)0xFE2001C4
38 #define SH7751_PCIIOBR (vu_long *)0xFE2001C8
39 #define SH7751_PCIPINT (vu_long *)0xFE2001CC
40 #define SH7751_PCIPINTM (vu_long *)0xFE2001D0
41 #define SH7751_PCICLKR (vu_long *)0xFE2001D4
42 #define SH7751_PCIBCR1 (vu_long *)0xFE2001E0
43 #define SH7751_PCIBCR2 (vu_long *)0xFE2001E4
44 #define SH7751_PCIWCR1 (vu_long *)0xFE2001E8
45 #define SH7751_PCIWCR2 (vu_long *)0xFE2001EC
46 #define SH7751_PCIWCR3 (vu_long *)0xFE2001F0
47 #define SH7751_PCIMCR (vu_long *)0xFE2001F4
48 #define SH7751_PCIBCR3 (vu_long *)0xFE2001F8
49
50 #define BCR1_BREQEN 0x00080000
51 #define PCI_SH7751_ID 0x35051054
52 #define PCI_SH7751R_ID 0x350E1054
53 #define SH7751_PCICONF1_WCC 0x00000080
54 #define SH7751_PCICONF1_PER 0x00000040
55 #define SH7751_PCICONF1_BUM 0x00000004
56 #define SH7751_PCICONF1_MES 0x00000002
57 #define SH7751_PCICONF1_CMDS 0x000000C6
58 #define SH7751_PCI_HOST_BRIDGE 0x6
59 #define SH7751_PCICR_PREFIX 0xa5000000
60 #define SH7751_PCICR_PRST 0x00000002
61 #define SH7751_PCICR_CFIN 0x00000001
62 #define SH7751_PCIPINT_D3 0x00000002
63 #define SH7751_PCIPINT_D0 0x00000001
64 #define SH7751_PCICLKR_PREFIX 0xa5000000
65
66 #define SH7751_PCI_MEM_BASE 0xFD000000
67 #define SH7751_PCI_MEM_SIZE 0x01000000
68 #define SH7751_PCI_IO_BASE 0xFE240000
69 #define SH7751_PCI_IO_SIZE 0x00040000
70
71 #define SH7751_PCIPAR (vu_long *)0xFE2001C0
72 #define SH7751_PCIPDR (vu_long *)0xFE200220
73
74 #define p4_in(addr) (*addr)
75 #define p4_out(data, addr) (*addr) = (data)
76
sh7751_pci_read_config(const struct udevice * dev,pci_dev_t bdf,uint offset,ulong * value,enum pci_size_t size)77 static int sh7751_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
78 uint offset, ulong *value,
79 enum pci_size_t size)
80 {
81 u32 addr, reg;
82
83 addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
84 p4_out(addr, SH7751_PCIPAR);
85 reg = p4_in(SH7751_PCIPDR);
86 *value = pci_conv_32_to_size(reg, offset, size);
87
88 return 0;
89 }
90
sh7751_pci_write_config(struct udevice * dev,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)91 static int sh7751_pci_write_config(struct udevice *dev, pci_dev_t bdf,
92 uint offset, ulong value,
93 enum pci_size_t size)
94 {
95 u32 addr, reg, old;
96
97 addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
98 p4_out(addr, SH7751_PCIPAR);
99 old = p4_in(SH7751_PCIPDR);
100 reg = pci_conv_size_to_32(old, value, offset, size);
101 p4_out(reg, SH7751_PCIPDR);
102
103 return 0;
104 }
105
sh7751_pci_probe(struct udevice * dev)106 static int sh7751_pci_probe(struct udevice *dev)
107 {
108 /* Double-check that we're a 7751 or 7751R chip */
109 if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID
110 && p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) {
111 printf("PCI: Unknown PCI host bridge.\n");
112 return 1;
113 }
114 printf("PCI: SH7751 PCI host bridge found.\n");
115
116 /* Double-check some BSC config settings */
117 /* (Area 3 non-MPX 32-bit, PCI bus pins) */
118 if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
119 printf("SH7751_BCR1 value is wrong(0x%08X)\n",
120 (unsigned int)p4_in(SH7751_BCR1));
121 return 2;
122 }
123 if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
124 printf("SH7751_BCR2 value is wrong(0x%08X)\n",
125 (unsigned int)p4_in(SH7751_BCR2));
126 return 3;
127 }
128 if (p4_in(SH7751_BCR2) & 0x01) {
129 printf("SH7751_BCR2 value is wrong(0x%08X)\n",
130 (unsigned int)p4_in(SH7751_BCR2));
131 return 4;
132 }
133
134 /* Force BREQEN in BCR1 to allow PCIC access */
135 p4_out((p4_in(SH7751_BCR1) | BCR1_BREQEN), SH7751_BCR1);
136
137 /* Toggle PCI reset pin */
138 p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), SH7751_PCICR);
139 udelay(32);
140 p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR);
141
142 /* Set cmd bits: WCC, PER, BUM, MES */
143 /* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */
144 p4_out(0xfb900047, SH7751_PCICONF1); /* K.Kino */
145
146 /* Define this host as the host bridge */
147 p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2);
148
149 /* Force PCI clock(s) on */
150 p4_out(0, SH7751_PCICLKR);
151 p4_out(0x03, SH7751_PCICLKR);
152
153 /* Clear powerdown IRQs, also mask them (unused) */
154 p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), SH7751_PCIPINT);
155 p4_out(0, SH7751_PCIPINTM);
156
157 p4_out(0xab000001, SH7751_PCICONF4);
158
159 /* Set up target memory mappings (for external DMA access) */
160 /* Map both P0 and P2 range to Area 3 RAM for ease of use */
161 p4_out(CFG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
162 p4_out(CFG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
163 p4_out(CFG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
164
165 p4_out(0, SH7751_PCILSR1);
166 p4_out(0, SH7751_PCILAR1);
167 p4_out(0xd0000000, SH7751_PCICONF6);
168
169 /* Map memory window to same address on PCI bus */
170 p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);
171
172 /* Map IO window to same address on PCI bus */
173 p4_out(SH7751_PCI_IO_BASE, SH7751_PCIIOBR);
174
175 /* set BREQEN */
176 p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);
177
178 /* Copy BSC registers into PCI BSC */
179 p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1);
180 p4_out(inw(SH7751_BCR2), SH7751_PCIBCR2);
181 p4_out(inw(SH7751_BCR3), SH7751_PCIBCR3);
182 p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1);
183 p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2);
184 p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3);
185 p4_out(inl(SH7751_MCR), SH7751_PCIMCR);
186
187 /* Finally, set central function init complete */
188 p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR);
189
190 return 0;
191 }
192
193 static const struct dm_pci_ops sh7751_pci_ops = {
194 .read_config = sh7751_pci_read_config,
195 .write_config = sh7751_pci_write_config,
196 };
197
198 static const struct udevice_id sh7751_pci_ids[] = {
199 { .compatible = "renesas,pci-sh7751" },
200 { }
201 };
202
203 U_BOOT_DRIVER(sh7751_pci) = {
204 .name = "sh7751_pci",
205 .id = UCLASS_PCI,
206 .of_match = sh7751_pci_ids,
207 .ops = &sh7751_pci_ops,
208 .probe = sh7751_pci_probe,
209 };
210