1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek PCIe host controller driver.
4 *
5 * Copyright (c) 2017-2019 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 * Honghui Zhang <honghui.zhang@mediatek.com>
8 */
9
10 #include <common.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <generic-phy.h>
14 #include <log.h>
15 #include <malloc.h>
16 #include <pci.h>
17 #include <reset.h>
18 #include <asm/io.h>
19 #include <dm/devres.h>
20 #include <linux/bitops.h>
21 #include <linux/iopoll.h>
22 #include <linux/list.h>
23 #include "pci_internal.h"
24
25 /* PCIe shared registers */
26 #define PCIE_SYS_CFG 0x00
27 #define PCIE_INT_ENABLE 0x0c
28 #define PCIE_CFG_ADDR 0x20
29 #define PCIE_CFG_DATA 0x24
30
31 /* PCIe per port registers */
32 #define PCIE_BAR0_SETUP 0x10
33 #define PCIE_CLASS 0x34
34 #define PCIE_LINK_STATUS 0x50
35
36 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
37 #define PCIE_PORT_PERST(x) BIT(1 + (x))
38 #define PCIE_PORT_LINKUP BIT(0)
39 #define PCIE_BAR_MAP_MAX GENMASK(31, 16)
40
41 #define PCIE_BAR_ENABLE BIT(0)
42 #define PCIE_REVISION_ID BIT(0)
43 #define PCIE_CLASS_CODE (0x60400 << 8)
44
45 /* MediaTek specific configuration registers */
46 #define PCIE_FTS_NUM 0x70c
47 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
48 #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
49
50 #define PCIE_FC_CREDIT 0x73c
51 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
52 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
53
54 /* PCIe V2 share registers */
55 #define PCIE_SYS_CFG_V2 0x0
56 #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
57 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
58
59 /* PCIe V2 per-port registers */
60 #define PCIE_CONF_VEND_ID 0x100
61 #define PCIE_CONF_DEVICE_ID 0x102
62 #define PCIE_CONF_CLASS_ID 0x106
63
64 #define PCIE_AHB_TRANS_BASE0_L 0x438
65 #define PCIE_AHB_TRANS_BASE0_H 0x43c
66 #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
67 #define PCIE_AXI_WINDOW0 0x448
68 #define WIN_ENABLE BIT(7)
69
70 /*
71 * Define PCIe to AHB window size as 2^33 to support max 8GB address space
72 * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
73 * start from 0x40000000).
74 */
75 #define PCIE2AHB_SIZE 0x21
76
77 /* PCIe V2 configuration transaction header */
78 #define PCIE_CFG_HEADER0 0x460
79 #define PCIE_CFG_HEADER1 0x464
80 #define PCIE_CFG_HEADER2 0x468
81 #define PCIE_CFG_WDATA 0x470
82 #define PCIE_APP_TLP_REQ 0x488
83 #define PCIE_CFG_RDATA 0x48c
84 #define APP_CFG_REQ BIT(0)
85 #define APP_CPL_STATUS GENMASK(7, 5)
86
87 #define CFG_WRRD_TYPE_0 4
88 #define CFG_WR_FMT 2
89 #define CFG_RD_FMT 0
90
91 #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
92 #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
93 #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
94 #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
95 #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
96 #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
97 #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
98 #define CFG_HEADER_DW0(type, fmt) \
99 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
100 #define CFG_HEADER_DW1(where, size) \
101 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
102 #define CFG_HEADER_DW2(regn, fun, dev, bus) \
103 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
104 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
105
106 #define PCIE_RST_CTRL 0x510
107 #define PCIE_PHY_RSTB BIT(0)
108 #define PCIE_PIPE_SRSTB BIT(1)
109 #define PCIE_MAC_SRSTB BIT(2)
110 #define PCIE_CRSTB BIT(3)
111 #define PCIE_PERSTB BIT(8)
112 #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
113 #define PCIE_LINK_STATUS_V2 0x804
114 #define PCIE_PORT_LINKUP_V2 BIT(11)
115
116 #define PCI_VENDOR_ID_MEDIATEK 0x14c3
117
118 enum MTK_PCIE_GEN {PCIE_V1, PCIE_V2, PCIE_V3};
119
120 struct mtk_pcie_port {
121 void __iomem *base;
122 struct list_head list;
123 struct mtk_pcie *pcie;
124 struct reset_ctl reset;
125 struct clk sys_ck;
126 struct clk ahb_ck;
127 struct clk axi_ck;
128 struct clk aux_ck;
129 struct clk obff_ck;
130 struct clk pipe_ck;
131 struct phy phy;
132 u32 slot;
133 };
134
135 struct mtk_pcie {
136 void __iomem *base;
137 void *priv;
138 struct clk free_ck;
139 struct list_head ports;
140 };
141
mtk_pcie_config_address(const struct udevice * udev,pci_dev_t bdf,uint offset,void ** paddress)142 static int mtk_pcie_config_address(const struct udevice *udev, pci_dev_t bdf,
143 uint offset, void **paddress)
144 {
145 struct mtk_pcie *pcie = dev_get_priv(udev);
146 u32 val;
147
148 val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf),
149 PCI_FUNC(bdf), offset) & ~PCI_CONF1_ENABLE;
150 writel(val, pcie->base + PCIE_CFG_ADDR);
151 *paddress = pcie->base + PCIE_CFG_DATA + (offset & 3);
152
153 return 0;
154 }
155
mtk_pcie_read_config(const struct udevice * bus,pci_dev_t bdf,uint offset,ulong * valuep,enum pci_size_t size)156 static int mtk_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
157 uint offset, ulong *valuep,
158 enum pci_size_t size)
159 {
160 return pci_generic_mmap_read_config(bus, mtk_pcie_config_address,
161 bdf, offset, valuep, size);
162 }
163
mtk_pcie_write_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)164 static int mtk_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
165 uint offset, ulong value,
166 enum pci_size_t size)
167 {
168 return pci_generic_mmap_write_config(bus, mtk_pcie_config_address,
169 bdf, offset, value, size);
170 }
171
172 static const struct dm_pci_ops mtk_pcie_ops = {
173 .read_config = mtk_pcie_read_config,
174 .write_config = mtk_pcie_write_config,
175 };
176
mtk_pcie_check_cfg_cpld(struct mtk_pcie_port * port)177 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
178 {
179 u32 val;
180 int err;
181
182 err = readl_poll_timeout(port->base + PCIE_APP_TLP_REQ, val,
183 !(val & APP_CFG_REQ), 100 * 1000);
184 if (err)
185 return -1;
186
187 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
188 return -1;
189
190 return 0;
191 }
192
mtk_pcie_hw_rd_cfg(struct mtk_pcie_port * port,u32 bus,pci_dev_t devfn,int where,int size,ulong * val)193 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, pci_dev_t devfn,
194 int where, int size, ulong *val)
195 {
196 u32 tmp;
197
198 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
199 port->base + PCIE_CFG_HEADER0);
200 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
201 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_DEV(devfn), bus),
202 port->base + PCIE_CFG_HEADER2);
203
204 /* Trigger h/w to transmit Cfgrd TLP */
205 tmp = readl(port->base + PCIE_APP_TLP_REQ);
206 tmp |= APP_CFG_REQ;
207 writel(tmp, port->base + PCIE_APP_TLP_REQ);
208
209 /* Check completion status */
210 if (mtk_pcie_check_cfg_cpld(port))
211 return -1;
212
213 /* Read cpld payload of Cfgrd */
214 *val = readl(port->base + PCIE_CFG_RDATA);
215
216 if (size == 1)
217 *val = (*val >> (8 * (where & 3))) & 0xff;
218 else if (size == 2)
219 *val = (*val >> (8 * (where & 3))) & 0xffff;
220
221 return 0;
222 }
223
mtk_pcie_hw_wr_cfg(struct mtk_pcie_port * port,u32 bus,pci_dev_t devfn,int where,int size,u32 val)224 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, pci_dev_t devfn,
225 int where, int size, u32 val)
226 {
227 /* Write PCIe configuration transaction header for Cfgwr */
228 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
229 port->base + PCIE_CFG_HEADER0);
230 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
231 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_DEV(devfn), bus),
232 port->base + PCIE_CFG_HEADER2);
233
234 /* Write Cfgwr data */
235 val = val << 8 * (where & 3);
236 writel(val, port->base + PCIE_CFG_WDATA);
237
238 /* Trigger h/w to transmit Cfgwr TLP */
239 val = readl(port->base + PCIE_APP_TLP_REQ);
240 val |= APP_CFG_REQ;
241 writel(val, port->base + PCIE_APP_TLP_REQ);
242
243 /* Check completion status */
244 return mtk_pcie_check_cfg_cpld(port);
245 }
246
mtk_pcie_find_port(const struct udevice * bus,pci_dev_t bdf)247 static struct mtk_pcie_port *mtk_pcie_find_port(const struct udevice *bus,
248 pci_dev_t bdf)
249 {
250 struct mtk_pcie *pcie = dev_get_priv(bus);
251 struct mtk_pcie_port *port;
252 struct udevice *dev;
253 struct pci_child_plat *pplat = NULL;
254 int ret = 0;
255
256 if (PCI_BUS(bdf) != 0) {
257 ret = pci_get_bus(PCI_BUS(bdf), &dev);
258 if (ret) {
259 debug("No such device,ret = %d\n", ret);
260 return NULL;
261 }
262
263 while (dev_seq(dev->parent) != 0)
264 dev = dev->parent;
265
266 pplat = dev_get_parent_plat(dev);
267 }
268
269 list_for_each_entry(port, &pcie->ports, list) {
270 if ((PCI_BUS(bdf) == 0) && (PCI_DEV(bdf) == port->slot))
271 return port;
272
273 if (PCI_BUS(bdf) != 0 && PCI_DEV(bdf) == 0 &&
274 PCI_DEV(pplat->devfn) == port->slot)
275 return port;
276 }
277
278 return NULL;
279 }
280
mtk_pcie_config_read(const struct udevice * bus,pci_dev_t bdf,uint offset,ulong * valuep,enum pci_size_t size)281 static int mtk_pcie_config_read(const struct udevice *bus, pci_dev_t bdf,
282 uint offset, ulong *valuep,
283 enum pci_size_t size)
284 {
285 struct mtk_pcie_port *port;
286 int ret;
287
288 port = mtk_pcie_find_port(bus, bdf);
289 if (!port) {
290 *valuep = pci_get_ff(size);
291 return 0;
292 }
293
294 ret = mtk_pcie_hw_rd_cfg(port, PCI_BUS(bdf), bdf, offset, (1 << size), valuep);
295 if (ret)
296 *valuep = pci_get_ff(size);
297
298 return ret;
299 }
300
mtk_pcie_config_write(struct udevice * bus,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)301 static int mtk_pcie_config_write(struct udevice *bus, pci_dev_t bdf,
302 uint offset, ulong value,
303 enum pci_size_t size)
304 {
305 struct mtk_pcie_port *port;
306
307 port = mtk_pcie_find_port(bus, bdf);
308 if (!port)
309 return 0;
310
311 /* Do not modify RC bar 0/1. */
312 if (PCI_BUS(bdf) == 0 && (offset == 0x10 || offset == 0x14))
313 return 0;
314
315 return mtk_pcie_hw_wr_cfg(port, PCI_BUS(bdf), bdf, offset, (1 << size), value);
316 }
317
318 static const struct dm_pci_ops mtk_pcie_ops_v2 = {
319 .read_config = mtk_pcie_config_read,
320 .write_config = mtk_pcie_config_write,
321 };
322
mtk_pcie_port_free(struct mtk_pcie_port * port)323 static void mtk_pcie_port_free(struct mtk_pcie_port *port)
324 {
325 list_del(&port->list);
326 free(port);
327 }
328
mtk_pcie_startup_port(struct mtk_pcie_port * port)329 static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
330 {
331 struct mtk_pcie *pcie = port->pcie;
332 u32 val;
333 int err;
334
335 /* assert port PERST_N */
336 setbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
337 /* de-assert port PERST_N */
338 clrbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
339
340 /* 100ms timeout value should be enough for Gen1/2 training */
341 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
342 !!(val & PCIE_PORT_LINKUP), 100000);
343 if (err)
344 return -ETIMEDOUT;
345
346 /* disable interrupt */
347 clrbits_le32(pcie->base + PCIE_INT_ENABLE,
348 PCIE_PORT_INT_EN(port->slot));
349
350 /* map to all DDR region. We need to set it before cfg operation. */
351 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
352 port->base + PCIE_BAR0_SETUP);
353
354 /* configure class code and revision ID */
355 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
356
357 /* configure FC credit */
358 val = PCI_CONF1_EXT_ADDRESS(0, port->slot, 0, PCIE_FC_CREDIT) & ~PCI_CONF1_ENABLE;
359 writel(val, pcie->base + PCIE_CFG_ADDR);
360 clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FC_CREDIT_MASK,
361 PCIE_FC_CREDIT_VAL(0x806c));
362
363 /* configure RC FTS number to 250 when it leaves L0s */
364 val = PCI_CONF1_EXT_ADDRESS(0, port->slot, 0, PCIE_FTS_NUM) & ~PCI_CONF1_ENABLE;
365 writel(val, pcie->base + PCIE_CFG_ADDR);
366 clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FTS_NUM_MASK,
367 PCIE_FTS_NUM_L0(0x50));
368
369 return 0;
370 }
371
mtk_pcie_startup_port_v2(struct mtk_pcie_port * port)372 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
373 {
374 struct mtk_pcie *pcie = port->pcie;
375 struct udevice *dev = pcie->priv;
376 struct pci_region *pci_mem;
377 u32 val;
378 int err;
379
380 /* MT7622/MT7629 platforms need to enable LTSSM and ASPM from PCIe subsys */
381 if (pcie->base) {
382 val = readl(pcie->base + PCIE_SYS_CFG_V2);
383 val |= PCIE_CSR_LTSSM_EN(port->slot) |
384 PCIE_CSR_ASPM_L1_EN(port->slot);
385 writel(val, pcie->base + PCIE_SYS_CFG_V2);
386 }
387
388 /* Assert all reset signals */
389 writel(0, port->base + PCIE_RST_CTRL);
390
391 /*
392 * Enable PCIe link down reset, if link status changed from link up to
393 * link down, this will reset MAC control registers and configuration
394 * space.
395 */
396 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
397 udelay(500);
398
399 /* De-assert PHY, PE, PIPE, MAC and configuration reset */
400 val = readl(port->base + PCIE_RST_CTRL);
401 val |= PCIE_PHY_RSTB | PCIE_PIPE_SRSTB | PCIE_MAC_SRSTB | PCIE_CRSTB;
402 writel(val, port->base + PCIE_RST_CTRL);
403
404 mdelay(100);
405 val |= PCIE_PERSTB;
406 writel(val, port->base + PCIE_RST_CTRL);
407
408 /* Set up vendor ID and class code */
409 val = PCI_VENDOR_ID_MEDIATEK;
410 writew(val, port->base + PCIE_CONF_VEND_ID);
411
412 val = PCI_CLASS_BRIDGE_PCI;
413 writew(val, port->base + PCIE_CONF_CLASS_ID);
414
415 /* 100ms timeout value should be enough for Gen1/2 training */
416 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
417 !!(val & PCIE_PORT_LINKUP_V2),
418 100 * 1000);
419 if (err)
420 return -ETIMEDOUT;
421
422 pci_get_regions(dev, NULL, &pci_mem, NULL);
423
424 /* Set AHB to PCIe translation windows */
425 val = lower_32_bits(pci_mem->bus_start) |
426 AHB2PCIE_SIZE(fls(pci_mem->size) - 1);
427 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
428
429 val = upper_32_bits(pci_mem->bus_start);
430 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
431
432 /* Set PCIe to AXI translation memory space.*/
433 val = PCIE2AHB_SIZE | WIN_ENABLE;
434 writel(val, port->base + PCIE_AXI_WINDOW0);
435
436 return 0;
437 }
438
mtk_pcie_enable_port(struct mtk_pcie_port * port)439 static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
440 {
441 int err;
442
443 err = clk_enable(&port->sys_ck);
444 if (err)
445 goto err_sys_clk;
446
447 err = reset_assert(&port->reset);
448 if (err)
449 goto err_reset;
450
451 err = reset_deassert(&port->reset);
452 if (err)
453 goto err_reset;
454
455 err = generic_phy_init(&port->phy);
456 if (err)
457 goto err_phy_init;
458
459 err = generic_phy_power_on(&port->phy);
460 if (err)
461 goto err_phy_on;
462
463 if (!mtk_pcie_startup_port(port))
464 return;
465
466 pr_err("Port%d link down\n", port->slot);
467
468 generic_phy_power_off(&port->phy);
469 err_phy_on:
470 generic_phy_exit(&port->phy);
471 err_phy_init:
472 err_reset:
473 clk_disable(&port->sys_ck);
474 err_sys_clk:
475 mtk_pcie_port_free(port);
476 }
477
mtk_pcie_enable_port_v2(struct mtk_pcie_port * port)478 static void mtk_pcie_enable_port_v2(struct mtk_pcie_port *port)
479 {
480 int err = 0;
481
482 err = clk_enable(&port->sys_ck);
483 if (err) {
484 debug("clk_enable(sys_ck) failed: %d\n", err);
485 goto exit;
486 }
487
488 err = clk_enable(&port->ahb_ck);
489 if (err) {
490 debug("clk_enable(ahb_ck) failed: %d\n", err);
491 goto exit;
492 }
493
494 err = clk_enable(&port->aux_ck);
495 if (err) {
496 debug("clk_enable(aux_ck) failed: %d\n", err);
497 goto exit;
498 }
499
500 err = clk_enable(&port->axi_ck);
501 if (err) {
502 debug("clk_enable(axi_ck) failed: %d\n", err);
503 goto exit;
504 }
505
506 err = clk_enable(&port->obff_ck);
507 if (err) {
508 debug("clk_enable(obff_ck) failed: %d\n", err);
509 goto exit;
510 }
511
512 err = clk_enable(&port->pipe_ck);
513 if (err) {
514 debug("clk_enable(pipe_ck) failed: %d\n", err);
515 goto exit;
516 }
517
518 err = mtk_pcie_startup_port_v2(port);
519 if (!err)
520 return;
521
522 pr_err("Port%d link down\n", port->slot);
523 exit:
524 mtk_pcie_port_free(port);
525 }
526
mtk_pcie_parse_port(struct udevice * dev,u32 slot)527 static int mtk_pcie_parse_port(struct udevice *dev, u32 slot)
528 {
529 struct mtk_pcie *pcie = dev_get_priv(dev);
530 struct mtk_pcie_port *port;
531 char name[10];
532 int err;
533
534 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
535 if (!port)
536 return -ENOMEM;
537
538 snprintf(name, sizeof(name), "port%d", slot);
539 port->base = dev_remap_addr_name(dev, name);
540 if (!port->base)
541 return -ENOENT;
542
543 snprintf(name, sizeof(name), "sys_ck%d", slot);
544 err = clk_get_by_name(dev, name, &port->sys_ck);
545 if (err)
546 return err;
547
548 err = reset_get_by_index(dev, slot, &port->reset);
549 if (err)
550 return err;
551
552 err = generic_phy_get_by_index(dev, slot, &port->phy);
553 if (err)
554 return err;
555
556 port->slot = slot;
557 port->pcie = pcie;
558
559 INIT_LIST_HEAD(&port->list);
560 list_add_tail(&port->list, &pcie->ports);
561
562 return 0;
563 }
564
mtk_pcie_parse_port_v2(struct udevice * dev,u32 slot)565 static int mtk_pcie_parse_port_v2(struct udevice *dev, u32 slot)
566 {
567 struct mtk_pcie *pcie = dev_get_priv(dev);
568 struct mtk_pcie_port *port;
569 char name[10];
570 int err;
571
572 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
573 if (!port)
574 return -ENOMEM;
575
576 snprintf(name, sizeof(name), "port%d", slot);
577 port->base = dev_remap_addr_name(dev, name);
578 if (!port->base) {
579 debug("failed to map port%d base\n", slot);
580 return -ENOENT;
581 }
582
583 snprintf(name, sizeof(name), "sys_ck%d", slot);
584 err = clk_get_by_name(dev, name, &port->sys_ck);
585 if (err) {
586 debug("clk_get_by_name(sys_ck) failed: %d\n", err);
587 return err;
588 }
589
590 snprintf(name, sizeof(name), "ahb_ck%d", slot);
591 err = clk_get_by_name(dev, name, &port->ahb_ck);
592 if (err) {
593 debug("clk_get_by_name(ahb_ck) failed: %d\n", err);
594 return err;
595 }
596
597 snprintf(name, sizeof(name), "aux_ck%d", slot);
598 err = clk_get_by_name(dev, name, &port->aux_ck);
599 if (err) {
600 debug("clk_get_by_name(aux_ck) failed: %d\n", err);
601 return err;
602 }
603
604 snprintf(name, sizeof(name), "axi_ck%d", slot);
605 err = clk_get_by_name(dev, name, &port->axi_ck);
606 if (err) {
607 debug("clk_get_by_name(axi_ck) failed: %d\n", err);
608 return err;
609 }
610
611 snprintf(name, sizeof(name), "obff_ck%d", slot);
612 err = clk_get_by_name(dev, name, &port->obff_ck);
613 if (err) {
614 debug("clk_get_by_name(obff_ck) failed: %d\n", err);
615 return err;
616 }
617
618 snprintf(name, sizeof(name), "pipe_ck%d", slot);
619 err = clk_get_by_name(dev, name, &port->pipe_ck);
620 if (err) {
621 debug("clk_get_by_name(pipe_ck) failed: %d\n", err);
622 return err;
623 }
624
625 port->slot = slot;
626 port->pcie = pcie;
627
628 INIT_LIST_HEAD(&port->list);
629 list_add_tail(&port->list, &pcie->ports);
630
631 return 0;
632 }
633
mtk_pcie_probe(struct udevice * dev)634 static int mtk_pcie_probe(struct udevice *dev)
635 {
636 struct mtk_pcie *pcie = dev_get_priv(dev);
637 struct mtk_pcie_port *port, *tmp;
638 ofnode subnode;
639 int err;
640
641 INIT_LIST_HEAD(&pcie->ports);
642
643 pcie->base = dev_remap_addr_name(dev, "subsys");
644 if (!pcie->base)
645 return -ENOENT;
646
647 err = clk_get_by_name(dev, "free_ck", &pcie->free_ck);
648 if (err)
649 return err;
650
651 /* enable top level clock */
652 err = clk_enable(&pcie->free_ck);
653 if (err)
654 return err;
655
656 dev_for_each_subnode(subnode, dev) {
657 struct fdt_pci_addr addr;
658 u32 slot = 0;
659
660 if (!ofnode_is_enabled(subnode))
661 continue;
662
663 err = ofnode_read_pci_addr(subnode, 0, "reg", &addr);
664 if (err)
665 return err;
666
667 slot = PCI_DEV(addr.phys_hi);
668
669 err = mtk_pcie_parse_port(dev, slot);
670 if (err)
671 return err;
672 }
673
674 /* enable each port, and then check link status */
675 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
676 mtk_pcie_enable_port(port);
677
678 return 0;
679 }
680
mtk_pcie_probe_v2(struct udevice * dev)681 static int mtk_pcie_probe_v2(struct udevice *dev)
682 {
683 struct mtk_pcie *pcie = dev_get_priv(dev);
684 struct mtk_pcie_port *port, *tmp;
685 struct fdt_pci_addr addr;
686 ofnode subnode;
687 unsigned int slot;
688 int err;
689
690 INIT_LIST_HEAD(&pcie->ports);
691
692 pcie->base = dev_remap_addr_name(dev, "subsys");
693 if (!pcie->base)
694 return -ENOENT;
695
696 pcie->priv = dev;
697
698 dev_for_each_subnode(subnode, dev) {
699 if (!ofnode_is_enabled(subnode))
700 continue;
701
702 err = ofnode_read_pci_addr(subnode, 0, "reg", &addr);
703 if (err)
704 return err;
705
706 slot = PCI_DEV(addr.phys_hi);
707 err = mtk_pcie_parse_port_v2(dev, slot);
708 if (err)
709 return err;
710 }
711
712 /* enable each port, and then check link status */
713 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
714 mtk_pcie_enable_port_v2(port);
715
716 return 0;
717 }
718
719 static const struct udevice_id mtk_pcie_ids[] = {
720 { .compatible = "mediatek,mt7623-pcie", PCIE_V1},
721 { }
722 };
723
724 U_BOOT_DRIVER(pcie_mediatek_v1) = {
725 .name = "pcie_mediatek_v1",
726 .id = UCLASS_PCI,
727 .of_match = mtk_pcie_ids,
728 .ops = &mtk_pcie_ops,
729 .probe = mtk_pcie_probe,
730 .priv_auto = sizeof(struct mtk_pcie),
731 };
732
733 static const struct udevice_id mtk_pcie_ids_v2[] = {
734 { .compatible = "mediatek,mt7622-pcie", PCIE_V2},
735 { }
736 };
737
738 U_BOOT_DRIVER(pcie_mediatek_v2) = {
739 .name = "pcie_mediatek_v2",
740 .id = UCLASS_PCI,
741 .of_match = mtk_pcie_ids_v2,
742 .ops = &mtk_pcie_ops_v2,
743 .probe = mtk_pcie_probe_v2,
744 .priv_auto = sizeof(struct mtk_pcie),
745 };
746