1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015-2016 Marvell International Ltd.
4 */
5
6 #include <common.h>
7 #include <fdt_support.h>
8 #include <log.h>
9 #include <asm/global_data.h>
10 #include <asm/io.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13 #include <linux/delay.h>
14 #include <phy.h>
15
16 #include "comphy_a3700.h"
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 struct comphy_mux_data a3700_comphy_mux_data[] = {
21 /* Lane 0 */
22 {
23 4,
24 {
25 { COMPHY_TYPE_UNCONNECTED, 0x0 },
26 { COMPHY_TYPE_SGMII1, 0x0 },
27 { COMPHY_TYPE_USB3_HOST0, 0x1 },
28 { COMPHY_TYPE_USB3_DEVICE, 0x1 }
29 }
30 },
31 /* Lane 1 */
32 {
33 3,
34 {
35 { COMPHY_TYPE_UNCONNECTED, 0x0},
36 { COMPHY_TYPE_SGMII0, 0x0},
37 { COMPHY_TYPE_PEX0, 0x1}
38 }
39 },
40 /* Lane 2 */
41 {
42 4,
43 {
44 { COMPHY_TYPE_UNCONNECTED, 0x0},
45 { COMPHY_TYPE_SATA0, 0x0},
46 { COMPHY_TYPE_USB3_HOST0, 0x1},
47 { COMPHY_TYPE_USB3_DEVICE, 0x1}
48 }
49 },
50 };
51
52 struct sgmii_phy_init_data_fix {
53 u16 addr;
54 u16 value;
55 };
56
57 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
58 static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = {
59 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000},
60 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030},
61 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC},
62 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA},
63 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550},
64 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0},
65 {0x104, 0x0C10}
66 };
67
68 /* 40M1G25 mode init data */
69 static u16 sgmii_phy_init[512] = {
70 /* 0 1 2 3 4 5 6 7 */
71 /*-----------------------------------------------------------*/
72 /* 8 9 A B C D E F */
73 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */
74 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */
75 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */
76 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */
77 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */
78 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */
79 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
80 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */
81 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */
82 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */
83 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */
84 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */
85 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */
86 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */
87 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */
88 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */
89 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */
90 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */
91 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */
92 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */
93 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */
94 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */
95 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */
96 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */
97 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */
98 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */
99 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */
100 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */
101 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */
102 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */
103 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */
104 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */
105 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */
106 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */
107 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */
108 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */
109 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */
110 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */
111 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */
112 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */
113 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */
114 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */
115 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */
116 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */
117 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */
118 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */
119 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */
120 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */
121 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */
122 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */
123 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */
124 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */
125 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */
126 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */
127 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */
128 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */
129 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */
130 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */
131 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */
132 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */
133 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */
134 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */
135 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */
136 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
137 };
138
139 /*
140 * comphy_poll_reg
141 *
142 * return: 1 on success, 0 on timeout
143 */
comphy_poll_reg(void * addr,u32 val,u32 mask,u8 op_type)144 static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u8 op_type)
145 {
146 u32 rval = 0xDEAD, timeout;
147
148 for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) {
149 if (op_type == POLL_16B_REG)
150 rval = readw(addr); /* 16 bit */
151 else
152 rval = readl(addr) ; /* 32 bit */
153
154 if ((rval & mask) == val)
155 return 1;
156
157 udelay(10000);
158 }
159
160 debug("Time out waiting (%p = %#010x)\n", addr, rval);
161 return 0;
162 }
163
164 /*
165 * comphy_pcie_power_up
166 *
167 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
168 */
comphy_pcie_power_up(u32 speed,u32 invert)169 static int comphy_pcie_power_up(u32 speed, u32 invert)
170 {
171 int ret;
172
173 debug_enter();
174
175 /*
176 * 1. Enable max PLL.
177 */
178 reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0);
179
180 /*
181 * 2. Select 20 bit SERDES interface.
182 */
183 reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0);
184
185 /*
186 * 3. Force to use reg setting for PCIe mode
187 */
188 reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0);
189
190 /*
191 * 4. Change RX wait
192 */
193 reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF);
194
195 /*
196 * 5. Enable idle sync
197 */
198 reg_set16(phy_addr(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF);
199
200 /*
201 * 6. Enable the output of 100M/125M/500M clock
202 */
203 reg_set16(phy_addr(PCIE, MISC_REG0),
204 0xA00D | rb_clk500m_en | rb_txdclk_2x_sel | rb_clk100m_125m_en, 0xFFFF);
205
206 /*
207 * 7. Enable TX
208 */
209 reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF);
210
211 /*
212 * 8. Check crystal jumper setting and program the Power and PLL
213 * Control accordingly
214 */
215 if (get_ref_clk() == 40) {
216 /* 40 MHz */
217 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF);
218 } else {
219 /* 25 MHz */
220 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF);
221 }
222
223 /*
224 * 9. Override Speed_PLL value and use MAC PLL
225 */
226 reg_set16(phy_addr(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate,
227 0xFFFF);
228
229 /*
230 * 10. Check the Polarity invert bit
231 */
232 if (invert & COMPHY_POLARITY_TXD_INVERT)
233 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
234 else
235 reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_txd_inv);
236
237 if (invert & COMPHY_POLARITY_RXD_INVERT)
238 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
239 else
240 reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_rxd_inv);
241
242 /*
243 * 11. Release SW reset
244 */
245 reg_set16(phy_addr(PCIE, GLOB_PHY_CTRL0),
246 rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32,
247 bf_soft_rst | bf_mode_refdiv);
248
249 /* Wait for > 55 us to allow PCLK be enabled */
250 udelay(PLL_SET_DELAY_US);
251
252 /* Assert PCLK enabled */
253 ret = comphy_poll_reg(phy_addr(PCIE, LANE_STAT1), /* address */
254 rb_txdclk_pclk_en, /* value */
255 rb_txdclk_pclk_en, /* mask */
256 POLL_16B_REG); /* 16bit */
257 if (!ret)
258 printf("Failed to lock PCIe PLL\n");
259
260 debug_exit();
261
262 /* Return the status of the PLL */
263 return ret;
264 }
265
266 /*
267 * reg_set_indirect
268 *
269 * return: void
270 */
reg_set_indirect(u32 reg,u16 data,u16 mask)271 static void reg_set_indirect(u32 reg, u16 data, u16 mask)
272 {
273 reg_set(rh_vsreg_addr, reg, 0xFFFFFFFF);
274 reg_set(rh_vsreg_data, data, mask);
275 }
276
277 /*
278 * comphy_sata_power_up
279 *
280 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
281 */
comphy_sata_power_up(u32 invert)282 static int comphy_sata_power_up(u32 invert)
283 {
284 int ret;
285 u32 data = 0;
286
287 debug_enter();
288
289 /*
290 * 0. Check the Polarity invert bits
291 */
292 if (invert & COMPHY_POLARITY_TXD_INVERT)
293 data |= bs_txd_inv;
294
295 if (invert & COMPHY_POLARITY_RXD_INVERT)
296 data |= bs_rxd_inv;
297
298 reg_set_indirect(vphy_sync_pattern_reg, data, bs_txd_inv | bs_rxd_inv);
299
300 /*
301 * 1. Select 40-bit data width width
302 */
303 reg_set_indirect(vphy_loopback_reg0, 0x800, bs_phyintf_40bit);
304
305 /*
306 * 2. Select reference clock and PHY mode (SATA)
307 */
308 if (get_ref_clk() == 40) {
309 /* 40 MHz */
310 reg_set_indirect(vphy_power_reg0, 0x3, 0x00FF);
311 } else {
312 /* 20 MHz */
313 reg_set_indirect(vphy_power_reg0, 0x1, 0x00FF);
314 }
315
316 /*
317 * 3. Use maximum PLL rate (no power save)
318 */
319 reg_set_indirect(vphy_calctl_reg, bs_max_pll_rate, bs_max_pll_rate);
320
321 /*
322 * 4. Reset reserved bit (??)
323 */
324 reg_set_indirect(vphy_reserve_reg, 0, bs_phyctrl_frm_pin);
325
326 /*
327 * 5. Set vendor-specific configuration (??)
328 */
329 reg_set(rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF);
330 reg_set(rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll);
331
332 /* Wait for > 55 us to allow PLL be enabled */
333 udelay(PLL_SET_DELAY_US);
334
335 /* Assert SATA PLL enabled */
336 reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF);
337 ret = comphy_poll_reg(rh_vsreg_data, /* address */
338 bs_pll_ready_tx, /* value */
339 bs_pll_ready_tx, /* mask */
340 POLL_32B_REG); /* 32bit */
341 if (!ret)
342 printf("Failed to lock SATA PLL\n");
343
344 debug_exit();
345
346 return ret;
347 }
348
349 /*
350 * usb3_reg_set16
351 *
352 * return: void
353 */
usb3_reg_set16(u32 reg,u16 data,u16 mask,u32 lane)354 static void usb3_reg_set16(u32 reg, u16 data, u16 mask, u32 lane)
355 {
356 /*
357 * When Lane 2 PHY is for USB3, access the PHY registers
358 * through indirect Address and Data registers INDIR_ACC_PHY_ADDR
359 * (RD00E0178h [31:0]) and INDIR_ACC_PHY_DATA (RD00E017Ch [31:0])
360 * within the SATA Host Controller registers, Lane 2 base register
361 * offset is 0x200
362 */
363
364 if (lane == 2)
365 reg_set_indirect(USB3PHY_LANE2_REG_BASE_OFFSET + reg, data,
366 mask);
367 else
368 reg_set16(phy_addr(USB3, reg), data, mask);
369 }
370
371 /*
372 * comphy_usb3_power_up
373 *
374 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
375 */
comphy_usb3_power_up(u32 lane,u32 type,u32 speed,u32 invert)376 static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
377 {
378 int ret;
379
380 debug_enter();
381
382 /*
383 * 1. Power up OTG module
384 */
385 reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0);
386
387 /*
388 * 2. Set counter for 100us pulse in USB3 Host and Device
389 * restore default burst size limit (Reference Clock 31:24)
390 */
391 reg_set(USB3_CTRPUL_VAL_REG, 0x8 << 24, rb_usb3_ctr_100ns);
392
393
394 /* 0xd005c300 = 0x1001 */
395 /* set PRD_TXDEEMPH (3.5db de-emph) */
396 usb3_reg_set16(LANE_CFG0, 0x1, 0xFF, lane);
397
398 /*
399 * Set BIT0: enable transmitter in high impedance mode
400 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency
401 * Set BIT6: Tx detect Rx at HiZ mode
402 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db
403 * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR
404 * register
405 */
406 usb3_reg_set16(LANE_CFG1,
407 tx_det_rx_mode | gen2_tx_data_dly_deft
408 | tx_elec_idle_mode_en,
409 prd_txdeemph1_mask | tx_det_rx_mode
410 | gen2_tx_data_dly_mask | tx_elec_idle_mode_en, lane);
411
412 /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */
413 usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80, lane);
414
415 /*
416 * set Override Margining Controls From the MAC: Use margining signals
417 * from lane configuration
418 */
419 usb3_reg_set16(TEST_MODE_CTRL, rb_mode_margin_override, 0xFFFF, lane);
420
421 /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */
422 /* set Mode Clock Source = PCLK is generated from REFCLK */
423 usb3_reg_set16(GLOB_CLK_SRC_LO, 0x0, 0xFF, lane);
424
425 /* set G2 Spread Spectrum Clock Amplitude at 4K */
426 usb3_reg_set16(GEN2_SETTINGS_2, g2_tx_ssc_amp, 0xF000, lane);
427
428 /*
429 * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register
430 * Master Current Select
431 */
432 usb3_reg_set16(GEN2_SETTINGS_3, 0x0, 0xFFFF, lane);
433
434 /*
435 * 3. Check crystal jumper setting and program the Power and PLL
436 * Control accordingly
437 * 4. Change RX wait
438 */
439 if (get_ref_clk() == 40) {
440 /* 40 MHz */
441 usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF, lane);
442 usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane);
443 } else {
444 /* 25 MHz */
445 usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF, lane);
446 usb3_reg_set16(PWR_MGM_TIM1, 0x107, 0xFFFF, lane);
447 }
448
449 /*
450 * 5. Enable idle sync
451 */
452 usb3_reg_set16(UNIT_CTRL, 0x60 | rb_idle_sync_en, 0xFFFF, lane);
453
454 /*
455 * 6. Enable the output of 500M clock
456 */
457 usb3_reg_set16(MISC_REG0, 0xA00D | rb_clk500m_en, 0xFFFF, lane);
458
459 /*
460 * 7. Set 20-bit data width
461 */
462 usb3_reg_set16(DIG_LB_EN, 0x0400, 0xFFFF, lane);
463
464 /*
465 * 8. Override Speed_PLL value and use MAC PLL
466 */
467 usb3_reg_set16(KVCO_CAL_CTRL, 0x0040 | rb_use_max_pll_rate, 0xFFFF,
468 lane);
469
470 /*
471 * 9. Check the Polarity invert bit
472 */
473 if (invert & COMPHY_POLARITY_TXD_INVERT)
474 usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);
475 else
476 usb3_reg_set16(SYNC_PATTERN, 0, phy_txd_inv, lane);
477
478 if (invert & COMPHY_POLARITY_RXD_INVERT)
479 usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);
480 else
481 usb3_reg_set16(SYNC_PATTERN, 0, phy_rxd_inv, lane);
482
483 /*
484 * 10. Set max speed generation to USB3.0 5Gbps
485 */
486 usb3_reg_set16(SYNC_MASK_GEN, 0x0400, 0x0C00, lane);
487
488 /*
489 * 11. Set capacitor value for FFE gain peaking to 0xF
490 */
491 usb3_reg_set16(GEN3_SETTINGS_3, 0xF, 0xF, lane);
492
493 /*
494 * 12. Release SW reset
495 */
496 usb3_reg_set16(GLOB_PHY_CTRL0,
497 rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32
498 | 0x20, 0xFFFF, lane);
499
500 /* Wait for > 55 us to allow PCLK be enabled */
501 udelay(PLL_SET_DELAY_US);
502
503 /* Assert PCLK enabled */
504 if (lane == 2) {
505 reg_set(rh_vsreg_addr,
506 LANE_STAT1 + USB3PHY_LANE2_REG_BASE_OFFSET,
507 0xFFFFFFFF);
508 ret = comphy_poll_reg(rh_vsreg_data, /* address */
509 rb_txdclk_pclk_en, /* value */
510 rb_txdclk_pclk_en, /* mask */
511 POLL_32B_REG); /* 32bit */
512 } else {
513 ret = comphy_poll_reg(phy_addr(USB3, LANE_STAT1), /* address */
514 rb_txdclk_pclk_en, /* value */
515 rb_txdclk_pclk_en, /* mask */
516 POLL_16B_REG); /* 16bit */
517 }
518 if (!ret)
519 printf("Failed to lock USB3 PLL\n");
520
521 /*
522 * Set Soft ID for Host mode (Device mode works with Hard ID
523 * detection)
524 */
525 if (type == COMPHY_TYPE_USB3_HOST0) {
526 /*
527 * set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1)
528 * clear BIT1: set SOFT_ID = Host
529 * set BIT4: set INT_MODE = ID. Interrupt Mode: enable
530 * interrupt by ID instead of using both interrupts
531 * of HOST and Device ORed simultaneously
532 * INT_MODE=ID in order to avoid unexpected
533 * behaviour or both interrupts together
534 */
535 reg_set(USB32_CTRL_BASE,
536 usb32_ctrl_id_mode | usb32_ctrl_int_mode,
537 usb32_ctrl_id_mode | usb32_ctrl_soft_id |
538 usb32_ctrl_int_mode);
539 }
540
541 debug_exit();
542
543 return ret;
544 }
545
546 /*
547 * comphy_usb2_power_up
548 *
549 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
550 */
comphy_usb2_power_up(u8 usb32)551 static int comphy_usb2_power_up(u8 usb32)
552 {
553 int ret;
554
555 debug_enter();
556
557 if (usb32 != 0 && usb32 != 1) {
558 printf("invalid usb32 value: (%d), should be either 0 or 1\n",
559 usb32);
560 debug_exit();
561 return 0;
562 }
563
564 /*
565 * 0. Setup PLL. 40MHz clock uses defaults.
566 * See "PLL Settings for Typical REFCLK" table
567 */
568 if (get_ref_clk() == 25) {
569 reg_set(USB2_PHY_BASE(usb32), 5 | (96 << 16),
570 0x3F | (0xFF << 16) | (0x3 << 28));
571 }
572
573 /*
574 * 1. PHY pull up and disable USB2 suspend
575 */
576 reg_set(USB2_PHY_CTRL_ADDR(usb32),
577 RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU(usb32), 0);
578
579 if (usb32 != 0) {
580 /*
581 * 2. Power up OTG module
582 */
583 reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0);
584
585 /*
586 * 3. Configure PHY charger detection
587 */
588 reg_set(USB2_PHY_CHRGR_DET_ADDR, 0,
589 rb_cdp_en | rb_dcp_en | rb_pd_en | rb_cdp_dm_auto |
590 rb_enswitch_dp | rb_enswitch_dm | rb_pu_chrg_dtc);
591 }
592
593 /* Assert PLL calibration done */
594 ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32),
595 rb_usb2phy_pllcal_done, /* value */
596 rb_usb2phy_pllcal_done, /* mask */
597 POLL_32B_REG); /* 32bit */
598 if (!ret) {
599 printf("Failed to end USB2 PLL calibration\n");
600 goto out;
601 }
602
603 /* Assert impedance calibration done */
604 ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32),
605 rb_usb2phy_impcal_done, /* value */
606 rb_usb2phy_impcal_done, /* mask */
607 POLL_32B_REG); /* 32bit */
608 if (!ret) {
609 printf("Failed to end USB2 impedance calibration\n");
610 goto out;
611 }
612
613 /* Assert squetch calibration done */
614 ret = comphy_poll_reg(USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32),
615 rb_usb2phy_sqcal_done, /* value */
616 rb_usb2phy_sqcal_done, /* mask */
617 POLL_32B_REG); /* 32bit */
618 if (!ret) {
619 printf("Failed to end USB2 unknown calibration\n");
620 goto out;
621 }
622
623 /* Assert PLL is ready */
624 ret = comphy_poll_reg(USB2_PHY_PLL_CTRL0_ADDR(usb32),
625 rb_usb2phy_pll_ready, /* value */
626 rb_usb2phy_pll_ready, /* mask */
627 POLL_32B_REG); /* 32bit */
628
629 if (!ret) {
630 printf("Failed to lock USB2 PLL\n");
631 goto out;
632 }
633
634 out:
635 debug_exit();
636
637 return ret;
638 }
639
640 /*
641 * comphy_emmc_power_up
642 *
643 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
644 */
comphy_emmc_power_up(void)645 static int comphy_emmc_power_up(void)
646 {
647 debug_enter();
648
649 /*
650 * 1. Bus power ON, Bus voltage 1.8V
651 */
652 reg_set(SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00);
653
654 /*
655 * 2. Set FIFO parameters
656 */
657 reg_set(SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF);
658
659 /*
660 * 3. Set Capabilities 1_2
661 */
662 reg_set(SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF);
663
664 /*
665 * 4. Set Endian
666 */
667 reg_set(SDIO_ENDIAN_ADDR, 0x00c00000, 0);
668
669 /*
670 * 4. Init PHY
671 */
672 reg_set(SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000);
673 reg_set(SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000, 0xF0000000);
674
675 /*
676 * 5. DLL reset
677 */
678 reg_set(SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0);
679 reg_set(SDIO_DLL_RST_ADDR, 0x00010000, 0);
680
681 debug_exit();
682
683 return 1;
684 }
685
686 /*
687 * comphy_sgmii_power_up
688 *
689 * return:
690 */
comphy_sgmii_phy_init(u32 lane,u32 speed)691 static void comphy_sgmii_phy_init(u32 lane, u32 speed)
692 {
693 const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix);
694 int addr, fix_idx;
695 u16 val;
696
697 fix_idx = 0;
698 for (addr = 0; addr < 512; addr++) {
699 /*
700 * All PHY register values are defined in full for 3.125Gbps
701 * SERDES speed. The values required for 1.25 Gbps are almost
702 * the same and only few registers should be "fixed" in
703 * comparison to 3.125 Gbps values. These register values are
704 * stored in "sgmii_phy_init_fix" array.
705 */
706 if (speed != COMPHY_SPEED_1_25G &&
707 sgmii_phy_init_fix[fix_idx].addr == addr) {
708 /* Use new value */
709 val = sgmii_phy_init_fix[fix_idx].value;
710 if (fix_idx < fix_arr_sz)
711 fix_idx++;
712 } else {
713 val = sgmii_phy_init[addr];
714 }
715
716 reg_set16(sgmiiphy_addr(lane, addr), val, 0xFFFF);
717 }
718 }
719
720 /*
721 * comphy_sgmii_power_up
722 *
723 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
724 */
comphy_sgmii_power_up(u32 lane,u32 speed,u32 invert)725 static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
726 {
727 int ret;
728 u32 saved_selector;
729
730 debug_enter();
731
732 /*
733 * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0
734 */
735 saved_selector = readl(COMPHY_SEL_ADDR);
736 reg_set(COMPHY_SEL_ADDR, 0, 0xFFFFFFFF);
737
738 /*
739 * 2. Reset PHY by setting PHY input port PIN_RESET=1.
740 * 3. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep
741 * PHY TXP/TXN output to idle state during PHY initialization
742 * 4. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.
743 */
744 reg_set(COMPHY_PHY_CFG1_ADDR(lane),
745 rb_pin_reset_comphy | rb_pin_tx_idle | rb_pin_pu_iveref,
746 rb_pin_reset_core | rb_pin_pu_pll |
747 rb_pin_pu_rx | rb_pin_pu_tx);
748
749 /*
750 * 5. Release reset to the PHY by setting PIN_RESET=0.
751 */
752 reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0, rb_pin_reset_comphy);
753
754 /*
755 * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide
756 * COMPHY bit rate
757 */
758 if (speed == COMPHY_SPEED_3_125G) { /* 3.125 GHz */
759 reg_set(COMPHY_PHY_CFG1_ADDR(lane),
760 (0x8 << rf_gen_rx_sel_shift) |
761 (0x8 << rf_gen_tx_sel_shift),
762 rf_gen_rx_select | rf_gen_tx_select);
763
764 } else if (speed == COMPHY_SPEED_1_25G) { /* 1.25 GHz */
765 reg_set(COMPHY_PHY_CFG1_ADDR(lane),
766 (0x6 << rf_gen_rx_sel_shift) |
767 (0x6 << rf_gen_tx_sel_shift),
768 rf_gen_rx_select | rf_gen_tx_select);
769 } else {
770 printf("Unsupported COMPHY speed!\n");
771 return 0;
772 }
773
774 /*
775 * 8. Wait 1mS for bandgap and reference clocks to stabilize;
776 * then start SW programming.
777 */
778 mdelay(10);
779
780 /* 9. Program COMPHY register PHY_MODE */
781 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),
782 PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask);
783
784 /*
785 * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK
786 * source
787 */
788 reg_set16(sgmiiphy_addr(lane, MISC_REG0), 0, rb_ref_clk_sel);
789
790 /*
791 * 11. Set correct reference clock frequency in COMPHY register
792 * REF_FREF_SEL.
793 */
794 if (get_ref_clk() == 40) {
795 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),
796 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
797 } else {
798 /* 25MHz */
799 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),
800 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
801 }
802
803 /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */
804 /*
805 * This step is mentioned in the flow received from verification team.
806 * However the PHY_GEN_MAX value is only meaningful for other
807 * interfaces (not SGMII). For instance, it selects SATA speed
808 * 1.5/3/6 Gbps or PCIe speed 2.5/5 Gbps
809 */
810
811 /*
812 * 13. Program COMPHY register SEL_BITS to set correct parallel data
813 * bus width
814 */
815 /* 10bit */
816 reg_set16(sgmiiphy_addr(lane, DIG_LB_EN), 0, rf_data_width_mask);
817
818 /*
819 * 14. As long as DFE function needs to be enabled in any mode,
820 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F
821 * for real chip during COMPHY power on.
822 */
823 /*
824 * The step 14 exists (and empty) in the original initialization flow
825 * obtained from the verification team. According to the functional
826 * specification DFE_UPDATE_EN already has the default value 0x3F
827 */
828
829 /*
830 * 15. Program COMPHY GEN registers.
831 * These registers should be programmed based on the lab testing
832 * result to achieve optimal performance. Please contact the CEA
833 * group to get the related GEN table during real chip bring-up.
834 * We only requred to run though the entire registers programming
835 * flow defined by "comphy_sgmii_phy_init" when the REF clock is
836 * 40 MHz. For REF clock 25 MHz the default values stored in PHY
837 * registers are OK.
838 */
839 debug("Running C-DPI phy init %s mode\n",
840 speed == COMPHY_SPEED_3_125G ? "2G5" : "1G");
841 if (get_ref_clk() == 40)
842 comphy_sgmii_phy_init(lane, speed);
843
844 /*
845 * 16. [Simulation Only] should not be used for real chip.
846 * By pass power up calibration by programming EXT_FORCE_CAL_DONE
847 * (R02h[9]) to 1 to shorten COMPHY simulation time.
848 */
849 /*
850 * 17. [Simulation Only: should not be used for real chip]
851 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX
852 * training simulation time.
853 */
854
855 /*
856 * 18. Check the PHY Polarity invert bit
857 */
858 if (invert & COMPHY_POLARITY_TXD_INVERT)
859 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);
860 else
861 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), 0, phy_txd_inv);
862
863 if (invert & COMPHY_POLARITY_RXD_INVERT)
864 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);
865 else
866 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), 0, phy_rxd_inv);
867
868 /*
869 * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1
870 * to start PHY power up sequence. All the PHY register
871 * programming should be done before PIN_PU_PLL=1. There should be
872 * no register programming for normal PHY operation from this point.
873 */
874 reg_set(COMPHY_PHY_CFG1_ADDR(lane),
875 rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx,
876 rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx);
877
878 /*
879 * 20. Wait for PHY power up sequence to finish by checking output ports
880 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1.
881 */
882 ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */
883 rb_pll_ready_tx | rb_pll_ready_rx, /* value */
884 rb_pll_ready_tx | rb_pll_ready_rx, /* mask */
885 POLL_32B_REG); /* 32bit */
886 if (!ret) {
887 printf("Failed to lock PLL for SGMII PHY %d\n", lane);
888 goto out;
889 }
890
891 /*
892 * 21. Set COMPHY input port PIN_TX_IDLE=0
893 */
894 reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0x0, rb_pin_tx_idle);
895
896 /*
897 * 22. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1.
898 * to start RX initialization. PIN_RX_INIT_DONE will be cleared to
899 * 0 by the PHY. After RX initialization is done, PIN_RX_INIT_DONE
900 * will be set to 1 by COMPHY. Set PIN_RX_INIT=0 after
901 * PIN_RX_INIT_DONE= 1.
902 * Please refer to RX initialization part for details.
903 */
904 reg_set(COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init, 0x0);
905
906 ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */
907 rb_rx_init_done, /* value */
908 rb_rx_init_done, /* mask */
909 POLL_32B_REG); /* 32bit */
910 if (!ret) {
911 printf("Failed to init RX of SGMII PHY %d\n", lane);
912 goto out;
913 }
914
915 /*
916 * Restore saved selector.
917 */
918 reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF);
919
920 out:
921 debug_exit();
922
923 return ret;
924 }
925
comphy_dedicated_phys_init(void)926 void comphy_dedicated_phys_init(void)
927 {
928 int node, usb32, ret = 1;
929 const void *blob = gd->fdt_blob;
930
931 debug_enter();
932
933 for (usb32 = 0; usb32 <= 1; usb32++) {
934 /*
935 * There are 2 UTMI PHYs in this SOC.
936 * One is independendent and one is paired with USB3 port (OTG)
937 */
938 if (usb32 == 0) {
939 node = fdt_node_offset_by_compatible(
940 blob, -1, "marvell,armada-3700-ehci");
941 } else {
942 node = fdt_node_offset_by_compatible(
943 blob, -1, "marvell,armada3700-xhci");
944 }
945
946 if (node > 0) {
947 if (fdtdec_get_is_enabled(blob, node)) {
948 ret = comphy_usb2_power_up(usb32);
949 if (!ret)
950 printf("Failed to initialize UTMI PHY\n");
951 else
952 debug("UTMI PHY init succeed\n");
953 } else {
954 debug("USB%d node is disabled\n",
955 usb32 == 0 ? 2 : 3);
956 }
957 } else {
958 debug("No USB%d node in DT\n", usb32 == 0 ? 2 : 3);
959 }
960 }
961
962 node = fdt_node_offset_by_compatible(blob, -1,
963 "marvell,armada-8k-sdhci");
964 if (node <= 0) {
965 node = fdt_node_offset_by_compatible(
966 blob, -1, "marvell,armada-3700-sdhci");
967 }
968
969 if (node > 0) {
970 if (fdtdec_get_is_enabled(blob, node)) {
971 ret = comphy_emmc_power_up();
972 if (!ret)
973 printf("Failed to initialize SDIO/eMMC PHY\n");
974 else
975 debug("SDIO/eMMC PHY init succeed\n");
976 } else {
977 debug("SDIO/eMMC node is disabled\n");
978 }
979 } else {
980 debug("No SDIO/eMMC node in DT\n");
981 }
982
983 debug_exit();
984 }
985
find_available_node_by_compatible(int offset,const char * compatible)986 static int find_available_node_by_compatible(int offset, const char *compatible)
987 {
988 fdt_for_each_node_by_compatible(offset, gd->fdt_blob, offset,
989 compatible)
990 if (fdtdec_get_is_enabled(gd->fdt_blob, offset))
991 return offset;
992
993 return -1;
994 }
995
comphy_a3700_find_lane(const int nodes[3],int node,int port,int * lane,int * invert)996 static bool comphy_a3700_find_lane(const int nodes[3], int node,
997 int port, int *lane, int *invert)
998 {
999 int res, i, j;
1000
1001 for (i = 0; ; i++) {
1002 struct fdtdec_phandle_args args;
1003
1004 res = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "phys",
1005 "#phy-cells", 0, i, &args);
1006 if (res)
1007 return false;
1008
1009 for (j = 0; j < 3; j++) {
1010 if (nodes[j] >= 0 && args.node == nodes[j] &&
1011 (args.args_count >= 1 ? args.args[0] : 0) == port) {
1012 *lane = j;
1013 *invert = args.args_count >= 2 ? args.args[1]
1014 : 0;
1015 return true;
1016 }
1017 }
1018 }
1019
1020 return false;
1021 }
1022
comphy_a3700_fill_cfg(struct chip_serdes_phy_config * cfg,const int nodes[3],const char * compatible,int type)1023 static void comphy_a3700_fill_cfg(struct chip_serdes_phy_config *cfg,
1024 const int nodes[3], const char *compatible,
1025 int type)
1026 {
1027 int node, lane, port, speed, invert;
1028
1029 port = (type == COMPHY_TYPE_SGMII1) ? 1 : 0;
1030
1031 node = -1;
1032 while (1) {
1033 node = find_available_node_by_compatible(node, compatible);
1034 if (node < 0)
1035 return;
1036
1037 if (comphy_a3700_find_lane(nodes, node, port, &lane, &invert))
1038 break;
1039 }
1040
1041 if (cfg->comphy_map_data[lane].type != COMPHY_TYPE_UNCONNECTED) {
1042 printf("Error: More PHYs defined for lane %d, skipping\n",
1043 lane);
1044 return;
1045 }
1046
1047 if (type == COMPHY_TYPE_SGMII0 || type == COMPHY_TYPE_SGMII1) {
1048 const char *phy_mode;
1049
1050 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
1051 if (phy_mode &&
1052 !strcmp(phy_mode,
1053 phy_string_for_interface(PHY_INTERFACE_MODE_2500BASEX)))
1054 speed = COMPHY_SPEED_3_125G;
1055 else
1056 speed = COMPHY_SPEED_1_25G;
1057 } else if (type == COMPHY_TYPE_SATA0) {
1058 speed = COMPHY_SPEED_6G;
1059 } else {
1060 speed = COMPHY_SPEED_5G;
1061 }
1062
1063 cfg->comphy_map_data[lane].type = type;
1064 cfg->comphy_map_data[lane].speed = speed;
1065 cfg->comphy_map_data[lane].invert = invert;
1066 }
1067
1068 static const fdt32_t comphy_a3700_mux_lane_order[3] = {
1069 __constant_cpu_to_be32(1),
1070 __constant_cpu_to_be32(0),
1071 __constant_cpu_to_be32(2),
1072 };
1073
comphy_a3700_init_serdes_map(int node,struct chip_serdes_phy_config * cfg)1074 int comphy_a3700_init_serdes_map(int node, struct chip_serdes_phy_config *cfg)
1075 {
1076 int comphy_nodes[3];
1077 int child, i;
1078
1079 for (i = 0; i < ARRAY_SIZE(comphy_nodes); i++)
1080 comphy_nodes[i] = -FDT_ERR_NOTFOUND;
1081
1082 fdt_for_each_subnode(child, gd->fdt_blob, node) {
1083 if (!fdtdec_get_is_enabled(gd->fdt_blob, child))
1084 continue;
1085
1086 i = fdtdec_get_int(gd->fdt_blob, child, "reg", -1);
1087 if (i < 0 || i >= ARRAY_SIZE(comphy_nodes))
1088 continue;
1089
1090 comphy_nodes[i] = child;
1091 }
1092
1093 for (i = 0; i < ARRAY_SIZE(comphy_nodes); i++) {
1094 cfg->comphy_map_data[i].type = COMPHY_TYPE_UNCONNECTED;
1095 cfg->comphy_map_data[i].speed = COMPHY_SPEED_INVALID;
1096 }
1097
1098 comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada3700-u3d",
1099 COMPHY_TYPE_USB3_DEVICE);
1100 comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada3700-xhci",
1101 COMPHY_TYPE_USB3_HOST0);
1102 comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada-3700-pcie",
1103 COMPHY_TYPE_PEX0);
1104 comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada-3700-ahci",
1105 COMPHY_TYPE_SATA0);
1106 comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada-3700-neta",
1107 COMPHY_TYPE_SGMII0);
1108 comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada-3700-neta",
1109 COMPHY_TYPE_SGMII1);
1110
1111 cfg->comphy_lanes_count = 3;
1112 cfg->comphy_mux_bitcount = 4;
1113 cfg->comphy_mux_lane_order = comphy_a3700_mux_lane_order;
1114
1115 return 0;
1116 }
1117
comphy_a3700_init(struct chip_serdes_phy_config * chip_cfg,struct comphy_map * serdes_map)1118 int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg,
1119 struct comphy_map *serdes_map)
1120 {
1121 struct comphy_map *comphy_map;
1122 u32 comphy_max_count = chip_cfg->comphy_lanes_count;
1123 u32 lane, ret = 0;
1124
1125 debug_enter();
1126
1127 /* Initialize PHY mux */
1128 chip_cfg->mux_data = a3700_comphy_mux_data;
1129 comphy_mux_init(chip_cfg, serdes_map, COMPHY_SEL_ADDR);
1130
1131 for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count;
1132 lane++, comphy_map++) {
1133 debug("Initialize serdes number %d\n", lane);
1134 debug("Serdes type = 0x%x invert=%d\n",
1135 comphy_map->type, comphy_map->invert);
1136
1137 switch (comphy_map->type) {
1138 case COMPHY_TYPE_UNCONNECTED:
1139 continue;
1140 break;
1141
1142 case COMPHY_TYPE_PEX0:
1143 ret = comphy_pcie_power_up(comphy_map->speed,
1144 comphy_map->invert);
1145 break;
1146
1147 case COMPHY_TYPE_USB3_HOST0:
1148 case COMPHY_TYPE_USB3_DEVICE:
1149 ret = comphy_usb3_power_up(lane,
1150 comphy_map->type,
1151 comphy_map->speed,
1152 comphy_map->invert);
1153 break;
1154
1155 case COMPHY_TYPE_SGMII0:
1156 case COMPHY_TYPE_SGMII1:
1157 ret = comphy_sgmii_power_up(lane, comphy_map->speed,
1158 comphy_map->invert);
1159 break;
1160
1161 case COMPHY_TYPE_SATA0:
1162 ret = comphy_sata_power_up(comphy_map->invert);
1163 break;
1164
1165 default:
1166 debug("Unknown SerDes type, skip initialize SerDes %d\n",
1167 lane);
1168 ret = 1;
1169 break;
1170 }
1171 if (!ret)
1172 printf("PLL is not locked - Failed to initialize lane %d\n",
1173 lane);
1174 }
1175
1176 debug_exit();
1177 return ret;
1178 }
1179