1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
6 #define LOG_CATEGORY UCLASS_PHY
7
8 #include <common.h>
9 #include <clk.h>
10 #include <clk-uclass.h>
11 #include <div64.h>
12 #include <dm.h>
13 #include <fdtdec.h>
14 #include <generic-phy.h>
15 #include <log.h>
16 #include <reset.h>
17 #include <syscon.h>
18 #include <usb.h>
19 #include <asm/io.h>
20 #include <dm/device_compat.h>
21 #include <dm/lists.h>
22 #include <dm/of_access.h>
23 #include <linux/bitfield.h>
24 #include <linux/bitops.h>
25 #include <linux/delay.h>
26 #include <power/regulator.h>
27
28 /* USBPHYC registers */
29 #define STM32_USBPHYC_PLL 0x0
30 #define STM32_USBPHYC_MISC 0x8
31 #define STM32_USBPHYC_TUNE(X) (0x10C + ((X) * 0x100))
32
33 /* STM32_USBPHYC_PLL bit fields */
34 #define PLLNDIV GENMASK(6, 0)
35 #define PLLNDIV_SHIFT 0
36 #define PLLFRACIN GENMASK(25, 10)
37 #define PLLFRACIN_SHIFT 10
38 #define PLLEN BIT(26)
39 #define PLLSTRB BIT(27)
40 #define PLLSTRBYP BIT(28)
41 #define PLLFRACCTL BIT(29)
42 #define PLLDITHEN0 BIT(30)
43 #define PLLDITHEN1 BIT(31)
44
45 /* STM32_USBPHYC_MISC bit fields */
46 #define SWITHOST BIT(0)
47
48 /* STM32_USBPHYC_TUNE bit fields */
49 #define INCURREN BIT(0)
50 #define INCURRINT BIT(1)
51 #define LFSCAPEN BIT(2)
52 #define HSDRVSLEW BIT(3)
53 #define HSDRVDCCUR BIT(4)
54 #define HSDRVDCLEV BIT(5)
55 #define HSDRVCURINCR BIT(6)
56 #define FSDRVRFADJ BIT(7)
57 #define HSDRVRFRED BIT(8)
58 #define HSDRVCHKITRM GENMASK(12, 9)
59 #define HSDRVCHKZTRM GENMASK(14, 13)
60 #define OTPCOMP GENMASK(19, 15)
61 #define SQLCHCTL GENMASK(21, 20)
62 #define HDRXGNEQEN BIT(22)
63 #define HSRXOFF GENMASK(24, 23)
64 #define HSFALLPREEM BIT(25)
65 #define SHTCCTCTLPROT BIT(26)
66 #define STAGSEL BIT(27)
67
68 #define MAX_PHYS 2
69
70 /* max 100 us for PLL lock and 100 us for PHY init */
71 #define PLL_INIT_TIME_US 200
72 #define PLL_PWR_DOWN_TIME_US 5
73 #define PLL_FVCO 2880 /* in MHz */
74 #define PLL_INFF_MIN_RATE 19200000 /* in Hz */
75 #define PLL_INFF_MAX_RATE 38400000 /* in Hz */
76
77 /* USBPHYC_CLK48 */
78 #define USBPHYC_CLK48_FREQ 48000000 /* in Hz */
79
80 enum boosting_vals {
81 BOOST_1000_UA = 1000,
82 BOOST_2000_UA = 2000,
83 };
84
85 enum dc_level_vals {
86 DC_MINUS_5_TO_7_MV,
87 DC_PLUS_5_TO_7_MV,
88 DC_PLUS_10_TO_14_MV,
89 DC_MAX,
90 };
91
92 enum current_trim {
93 CUR_NOMINAL,
94 CUR_PLUS_1_56_PCT,
95 CUR_PLUS_3_12_PCT,
96 CUR_PLUS_4_68_PCT,
97 CUR_PLUS_6_24_PCT,
98 CUR_PLUS_7_8_PCT,
99 CUR_PLUS_9_36_PCT,
100 CUR_PLUS_10_92_PCT,
101 CUR_PLUS_12_48_PCT,
102 CUR_PLUS_14_04_PCT,
103 CUR_PLUS_15_6_PCT,
104 CUR_PLUS_17_16_PCT,
105 CUR_PLUS_19_01_PCT,
106 CUR_PLUS_20_58_PCT,
107 CUR_PLUS_22_16_PCT,
108 CUR_PLUS_23_73_PCT,
109 CUR_MAX,
110 };
111
112 enum impedance_trim {
113 IMP_NOMINAL,
114 IMP_MINUS_2_OHMS,
115 IMP_MINUS_4_OMHS,
116 IMP_MINUS_6_OHMS,
117 IMP_MAX,
118 };
119
120 enum squelch_level {
121 SQLCH_NOMINAL,
122 SQLCH_PLUS_7_MV,
123 SQLCH_MINUS_5_MV,
124 SQLCH_PLUS_14_MV,
125 SQLCH_MAX,
126 };
127
128 enum rx_offset {
129 NO_RX_OFFSET,
130 RX_OFFSET_PLUS_5_MV,
131 RX_OFFSET_PLUS_10_MV,
132 RX_OFFSET_MINUS_5_MV,
133 RX_OFFSET_MAX,
134 };
135
136 struct pll_params {
137 u8 ndiv;
138 u16 frac;
139 };
140
141 struct stm32_usbphyc {
142 fdt_addr_t base;
143 struct clk clk;
144 struct udevice *vdda1v1;
145 struct udevice *vdda1v8;
146 struct stm32_usbphyc_phy {
147 struct udevice *vdd;
148 struct udevice *vbus;
149 bool init;
150 bool powered;
151 } phys[MAX_PHYS];
152 int n_pll_cons;
153 };
154
stm32_usbphyc_get_pll_params(u32 clk_rate,struct pll_params * pll_params)155 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
156 struct pll_params *pll_params)
157 {
158 unsigned long long fvco, ndiv, frac;
159
160 /*
161 * | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
162 * | FVCO = 2880MHz
163 * | NDIV = integer part of input bits to set the LDF
164 * | FRACT = fractional part of input bits to set the LDF
165 * => PLLNDIV = integer part of (FVCO / (INFF*2))
166 * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
167 * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
168 */
169 fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
170
171 ndiv = fvco;
172 do_div(ndiv, (clk_rate * 2));
173 pll_params->ndiv = (u8)ndiv;
174
175 frac = fvco * (1 << 16);
176 do_div(frac, (clk_rate * 2));
177 frac = frac - (ndiv * (1 << 16));
178 pll_params->frac = (u16)frac;
179 }
180
stm32_usbphyc_pll_init(struct stm32_usbphyc * usbphyc)181 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
182 {
183 struct pll_params pll_params;
184 u32 clk_rate = clk_get_rate(&usbphyc->clk);
185 u32 usbphyc_pll;
186
187 if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
188 log_debug("input clk freq (%dHz) out of range\n",
189 clk_rate);
190 return -EINVAL;
191 }
192
193 stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
194
195 usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
196 usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
197
198 if (pll_params.frac) {
199 usbphyc_pll |= PLLFRACCTL;
200 usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
201 & PLLFRACIN);
202 }
203
204 writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
205
206 log_debug("input clk freq=%dHz, ndiv=%d, frac=%d\n",
207 clk_rate, pll_params.ndiv, pll_params.frac);
208
209 return 0;
210 }
211
stm32_usbphyc_is_powered(struct stm32_usbphyc * usbphyc)212 static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
213 {
214 int i;
215
216 for (i = 0; i < MAX_PHYS; i++) {
217 if (usbphyc->phys[i].powered)
218 return true;
219 }
220
221 return false;
222 }
223
stm32_usbphyc_pll_enable(struct stm32_usbphyc * usbphyc)224 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
225 {
226 bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
227 true : false;
228 int ret;
229
230 /* Check if one consumer has already configured the pll */
231 if (pllen && usbphyc->n_pll_cons) {
232 usbphyc->n_pll_cons++;
233 return 0;
234 }
235
236 if (usbphyc->vdda1v1) {
237 ret = regulator_set_enable(usbphyc->vdda1v1, true);
238 if (ret)
239 return ret;
240 }
241
242 if (usbphyc->vdda1v8) {
243 ret = regulator_set_enable(usbphyc->vdda1v8, true);
244 if (ret)
245 return ret;
246 }
247
248 if (pllen) {
249 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
250 udelay(PLL_PWR_DOWN_TIME_US);
251 }
252
253 ret = stm32_usbphyc_pll_init(usbphyc);
254 if (ret)
255 return ret;
256
257 setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
258
259 /* We must wait PLL_INIT_TIME_US before using PHY */
260 udelay(PLL_INIT_TIME_US);
261
262 if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
263 return -EIO;
264
265 usbphyc->n_pll_cons++;
266
267 return 0;
268 }
269
stm32_usbphyc_pll_disable(struct stm32_usbphyc * usbphyc)270 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
271 {
272 int ret;
273
274 usbphyc->n_pll_cons--;
275
276 /* Check if other consumer requires pllen */
277 if (usbphyc->n_pll_cons)
278 return 0;
279
280 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
281
282 /*
283 * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
284 * bit is still clear
285 */
286 udelay(PLL_PWR_DOWN_TIME_US);
287
288 if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
289 return -EIO;
290
291 if (usbphyc->vdda1v1) {
292 ret = regulator_set_enable(usbphyc->vdda1v1, false);
293 if (ret)
294 return ret;
295 }
296
297 if (usbphyc->vdda1v8) {
298 ret = regulator_set_enable(usbphyc->vdda1v8, false);
299 if (ret)
300 return ret;
301 }
302
303 return 0;
304 }
305
stm32_usbphyc_phy_init(struct phy * phy)306 static int stm32_usbphyc_phy_init(struct phy *phy)
307 {
308 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
309 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
310 int ret;
311
312 dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
313 if (usbphyc_phy->init)
314 return 0;
315
316 ret = stm32_usbphyc_pll_enable(usbphyc);
317 if (ret)
318 return log_ret(ret);
319
320 usbphyc_phy->init = true;
321
322 return 0;
323 }
324
stm32_usbphyc_phy_exit(struct phy * phy)325 static int stm32_usbphyc_phy_exit(struct phy *phy)
326 {
327 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
328 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
329 int ret;
330
331 dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
332 if (!usbphyc_phy->init)
333 return 0;
334
335 ret = stm32_usbphyc_pll_disable(usbphyc);
336
337 usbphyc_phy->init = false;
338
339 return log_ret(ret);
340 }
341
stm32_usbphyc_phy_power_on(struct phy * phy)342 static int stm32_usbphyc_phy_power_on(struct phy *phy)
343 {
344 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
345 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
346 int ret;
347
348 dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
349 if (usbphyc_phy->vdd) {
350 ret = regulator_set_enable(usbphyc_phy->vdd, true);
351 if (ret)
352 return ret;
353 }
354 if (usbphyc_phy->vbus) {
355 ret = regulator_set_enable(usbphyc_phy->vbus, true);
356 if (ret)
357 return ret;
358 }
359
360 usbphyc_phy->powered = true;
361
362 return 0;
363 }
364
stm32_usbphyc_phy_power_off(struct phy * phy)365 static int stm32_usbphyc_phy_power_off(struct phy *phy)
366 {
367 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
368 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
369 int ret;
370
371 dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
372 usbphyc_phy->powered = false;
373
374 if (stm32_usbphyc_is_powered(usbphyc))
375 return 0;
376
377 if (usbphyc_phy->vbus) {
378 ret = regulator_set_enable_if_allowed(usbphyc_phy->vbus, false);
379 if (ret)
380 return ret;
381 }
382 if (usbphyc_phy->vdd) {
383 ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false);
384 if (ret)
385 return ret;
386 }
387
388 return 0;
389 }
390
stm32_usbphyc_get_regulator(ofnode node,char * supply_name,struct udevice ** regulator)391 static int stm32_usbphyc_get_regulator(ofnode node,
392 char *supply_name,
393 struct udevice **regulator)
394 {
395 struct ofnode_phandle_args regulator_phandle;
396 int ret;
397
398 ret = ofnode_parse_phandle_with_args(node, supply_name,
399 NULL, 0, 0,
400 ®ulator_phandle);
401 if (ret)
402 return ret;
403
404 ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
405 regulator_phandle.node,
406 regulator);
407 if (ret)
408 return ret;
409
410 return 0;
411 }
412
stm32_usbphyc_of_xlate(struct phy * phy,struct ofnode_phandle_args * args)413 static int stm32_usbphyc_of_xlate(struct phy *phy,
414 struct ofnode_phandle_args *args)
415 {
416 if (args->args_count < 1)
417 return -ENODEV;
418
419 if (args->args[0] >= MAX_PHYS)
420 return -ENODEV;
421
422 phy->id = args->args[0];
423
424 if ((phy->id == 0 && args->args_count != 1) ||
425 (phy->id == 1 && args->args_count != 2)) {
426 dev_err(phy->dev, "invalid number of cells for phy port%ld\n",
427 phy->id);
428 return -EINVAL;
429 }
430
431 return 0;
432 }
433
stm32_usbphyc_tuning(struct udevice * dev,ofnode node,u32 index)434 static void stm32_usbphyc_tuning(struct udevice *dev, ofnode node, u32 index)
435 {
436 struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
437 u32 reg = STM32_USBPHYC_TUNE(index);
438 u32 otpcomp, val, tune = 0;
439 int ret;
440
441 /* Backup OTP compensation code */
442 otpcomp = FIELD_GET(OTPCOMP, readl(usbphyc->base + reg));
443
444 ret = ofnode_read_u32(node, "st,current-boost-microamp", &val);
445 if (!ret && (val == BOOST_1000_UA || val == BOOST_2000_UA)) {
446 val = (val == BOOST_2000_UA) ? 1 : 0;
447 tune |= INCURREN | FIELD_PREP(INCURRINT, val);
448 } else if (ret != -EINVAL) {
449 dev_warn(dev, "phy%d: invalid st,current-boost-microamp value\n", index);
450 }
451
452 if (!ofnode_read_bool(node, "st,no-lsfs-fb-cap"))
453 tune |= LFSCAPEN;
454
455 if (ofnode_read_bool(node, "st,decrease-hs-slew-rate"))
456 tune |= HSDRVSLEW;
457
458 ret = ofnode_read_u32(node, "st,tune-hs-dc-level", &val);
459 if (!ret && val < DC_MAX) {
460 if (val == DC_MINUS_5_TO_7_MV) {
461 tune |= HSDRVDCCUR;
462 } else {
463 val = (val == DC_PLUS_10_TO_14_MV) ? 1 : 0;
464 tune |= HSDRVCURINCR | FIELD_PREP(HSDRVDCLEV, val);
465 }
466 } else if (ret != -EINVAL) {
467 dev_warn(dev, "phy%d: invalid st,tune-hs-dc-level value\n", index);
468 }
469
470 if (ofnode_read_bool(node, "st,enable-fs-rftime-tuning"))
471 tune |= FSDRVRFADJ;
472
473 if (ofnode_read_bool(node, "st,enable-hs-rftime-reduction"))
474 tune |= HSDRVRFRED;
475
476 ret = ofnode_read_u32(node, "st,trim-hs-current", &val);
477 if (!ret && val < CUR_MAX)
478 tune |= FIELD_PREP(HSDRVCHKITRM, val);
479 else if (ret != -EINVAL)
480 dev_warn(dev, "phy%d: invalid st,trim-hs-current value\n", index);
481
482 ret = ofnode_read_u32(node, "st,trim-hs-impedance", &val);
483 if (!ret && val < IMP_MAX)
484 tune |= FIELD_PREP(HSDRVCHKZTRM, val);
485 else if (ret != -EINVAL)
486 dev_warn(dev, "phy%d: invalid trim-hs-impedance value\n", index);
487
488 ret = ofnode_read_u32(node, "st,tune-squelch-level", &val);
489 if (!ret && val < SQLCH_MAX)
490 tune |= FIELD_PREP(SQLCHCTL, val);
491 else if (ret != -EINVAL)
492 dev_warn(dev, "phy%d: invalid st,tune-squelch-level value\n", index);
493
494 if (ofnode_read_bool(node, "st,enable-hs-rx-gain-eq"))
495 tune |= HDRXGNEQEN;
496
497 ret = ofnode_read_u32(node, "st,tune-hs-rx-offset", &val);
498 if (!ret && val < RX_OFFSET_MAX)
499 tune |= FIELD_PREP(HSRXOFF, val);
500 else if (ret != -EINVAL)
501 dev_warn(dev, "phy%d: invalid st,tune-hs-rx-offset value\n", index);
502
503 if (ofnode_read_bool(node, "st,no-hs-ftime-ctrl"))
504 tune |= HSFALLPREEM;
505
506 if (!ofnode_read_bool(node, "st,no-lsfs-sc"))
507 tune |= SHTCCTCTLPROT;
508
509 if (ofnode_read_bool(node, "st,enable-hs-tx-staggering"))
510 tune |= STAGSEL;
511
512 /* Restore OTP compensation code */
513 tune |= FIELD_PREP(OTPCOMP, otpcomp);
514
515 writel(tune, usbphyc->base + reg);
516 }
517
518 static const struct phy_ops stm32_usbphyc_phy_ops = {
519 .init = stm32_usbphyc_phy_init,
520 .exit = stm32_usbphyc_phy_exit,
521 .power_on = stm32_usbphyc_phy_power_on,
522 .power_off = stm32_usbphyc_phy_power_off,
523 .of_xlate = stm32_usbphyc_of_xlate,
524 };
525
stm32_usbphyc_bind(struct udevice * dev)526 static int stm32_usbphyc_bind(struct udevice *dev)
527 {
528 int ret;
529
530 ret = device_bind_driver_to_node(dev, "stm32-usbphyc-clk", "ck_usbo_48m",
531 dev_ofnode(dev), NULL);
532
533 return log_ret(ret);
534 }
535
stm32_usbphyc_probe(struct udevice * dev)536 static int stm32_usbphyc_probe(struct udevice *dev)
537 {
538 struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
539 struct reset_ctl reset;
540 ofnode node, connector;
541 int ret;
542
543 usbphyc->base = dev_read_addr(dev);
544 if (usbphyc->base == FDT_ADDR_T_NONE)
545 return -EINVAL;
546
547 /* Enable clock */
548 ret = clk_get_by_index(dev, 0, &usbphyc->clk);
549 if (ret)
550 return ret;
551
552 ret = clk_enable(&usbphyc->clk);
553 if (ret)
554 return ret;
555
556 /* Reset */
557 ret = reset_get_by_index(dev, 0, &reset);
558 if (!ret) {
559 reset_assert(&reset);
560 udelay(2);
561 reset_deassert(&reset);
562 }
563
564 /* get usbphyc regulator */
565 ret = device_get_supply_regulator(dev, "vdda1v1-supply",
566 &usbphyc->vdda1v1);
567 if (ret) {
568 dev_err(dev, "Can't get vdda1v1-supply regulator\n");
569 return ret;
570 }
571
572 ret = device_get_supply_regulator(dev, "vdda1v8-supply",
573 &usbphyc->vdda1v8);
574 if (ret) {
575 dev_err(dev, "Can't get vdda1v8-supply regulator\n");
576 return ret;
577 }
578
579 /* parse all PHY subnodes to populate regulator associated to each PHY port */
580 dev_for_each_subnode(node, dev) {
581 fdt_addr_t phy_id;
582 struct stm32_usbphyc_phy *usbphyc_phy;
583
584 phy_id = ofnode_read_u32_default(node, "reg", FDT_ADDR_T_NONE);
585 if (phy_id >= MAX_PHYS) {
586 dev_err(dev, "invalid reg value %llx for %s\n",
587 (fdt64_t)phy_id, ofnode_get_name(node));
588 return -ENOENT;
589 }
590
591 /* Configure phy tuning */
592 stm32_usbphyc_tuning(dev, node, phy_id);
593
594 usbphyc_phy = usbphyc->phys + phy_id;
595 usbphyc_phy->init = false;
596 usbphyc_phy->powered = false;
597 ret = stm32_usbphyc_get_regulator(node, "phy-supply",
598 &usbphyc_phy->vdd);
599 if (ret) {
600 dev_err(dev, "Can't get phy-supply regulator\n");
601 return ret;
602 }
603
604 usbphyc_phy->vbus = NULL;
605 connector = ofnode_find_subnode(node, "connector");
606 if (ofnode_valid(connector)) {
607 ret = stm32_usbphyc_get_regulator(connector, "vbus-supply",
608 &usbphyc_phy->vbus);
609 }
610 }
611
612 /* Check if second port has to be used for host controller */
613 if (dev_read_bool(dev, "st,port2-switch-to-host"))
614 setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
615
616 return 0;
617 }
618
619 static const struct udevice_id stm32_usbphyc_of_match[] = {
620 { .compatible = "st,stm32mp1-usbphyc", },
621 { },
622 };
623
624 U_BOOT_DRIVER(stm32_usb_phyc) = {
625 .name = "stm32-usbphyc",
626 .id = UCLASS_PHY,
627 .of_match = stm32_usbphyc_of_match,
628 .ops = &stm32_usbphyc_phy_ops,
629 .bind = stm32_usbphyc_bind,
630 .probe = stm32_usbphyc_probe,
631 .priv_auto = sizeof(struct stm32_usbphyc),
632 };
633
634 struct stm32_usbphyc_clk {
635 bool enable;
636 };
637
stm32_usbphyc_clk48_get_rate(struct clk * clk)638 static ulong stm32_usbphyc_clk48_get_rate(struct clk *clk)
639 {
640 return USBPHYC_CLK48_FREQ;
641 }
642
stm32_usbphyc_clk48_enable(struct clk * clk)643 static int stm32_usbphyc_clk48_enable(struct clk *clk)
644 {
645 struct stm32_usbphyc_clk *usbphyc_clk = dev_get_priv(clk->dev);
646 struct stm32_usbphyc *usbphyc;
647 int ret;
648
649 if (usbphyc_clk->enable)
650 return 0;
651
652 usbphyc = dev_get_priv(clk->dev->parent);
653
654 /* ck_usbo_48m is generated by usbphyc PLL */
655 ret = stm32_usbphyc_pll_enable(usbphyc);
656 if (ret)
657 return ret;
658
659 usbphyc_clk->enable = true;
660
661 return 0;
662 }
663
stm32_usbphyc_clk48_disable(struct clk * clk)664 static int stm32_usbphyc_clk48_disable(struct clk *clk)
665 {
666 struct stm32_usbphyc_clk *usbphyc_clk = dev_get_priv(clk->dev);
667 struct stm32_usbphyc *usbphyc;
668 int ret;
669
670 if (!usbphyc_clk->enable)
671 return 0;
672
673 usbphyc = dev_get_priv(clk->dev->parent);
674
675 ret = stm32_usbphyc_pll_disable(usbphyc);
676 if (ret)
677 return ret;
678
679 usbphyc_clk->enable = false;
680
681 return 0;
682 }
683
684 const struct clk_ops usbphyc_clk48_ops = {
685 .get_rate = stm32_usbphyc_clk48_get_rate,
686 .enable = stm32_usbphyc_clk48_enable,
687 .disable = stm32_usbphyc_clk48_disable,
688 };
689
690 U_BOOT_DRIVER(stm32_usb_phyc_clk) = {
691 .name = "stm32-usbphyc-clk",
692 .id = UCLASS_CLK,
693 .ops = &usbphyc_clk48_ops,
694 .priv_auto = sizeof(struct stm32_usbphyc_clk),
695 };
696