1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017-2020 STMicroelectronics - All Rights Reserved
4 */
5
6 #define LOG_CATEGORY UCLASS_PINCTRL
7
8 #include <common.h>
9 #include <dm.h>
10 #include <hwspinlock.h>
11 #include <log.h>
12 #include <malloc.h>
13 #include <asm/gpio.h>
14 #include <asm/io.h>
15 #include <dm/device_compat.h>
16 #include <dm/lists.h>
17 #include <dm/pinctrl.h>
18 #include <linux/bitops.h>
19 #include <linux/err.h>
20 #include <linux/libfdt.h>
21
22 #include "../gpio/stm32_gpio_priv.h"
23
24 #define MAX_PINS_ONE_IP 70
25 #define MODE_BITS_MASK 3
26 #define OSPEED_MASK 3
27 #define PUPD_MASK 3
28 #define OTYPE_MSK 1
29 #define AFR_MASK 0xF
30
31 struct stm32_pinctrl_priv {
32 struct hwspinlock hws;
33 int pinctrl_ngpios;
34 struct list_head gpio_dev;
35 };
36
37 struct stm32_gpio_bank {
38 struct udevice *gpio_dev;
39 struct list_head list;
40 };
41
42 #ifndef CONFIG_SPL_BUILD
43
44 static char pin_name[PINNAME_SIZE];
45 static const char * const pinmux_mode[GPIOF_COUNT] = {
46 [GPIOF_INPUT] = "gpio input",
47 [GPIOF_OUTPUT] = "gpio output",
48 [GPIOF_UNUSED] = "analog",
49 [GPIOF_UNKNOWN] = "unknown",
50 [GPIOF_FUNC] = "alt function",
51 };
52
53 static const char * const pinmux_bias[] = {
54 [STM32_GPIO_PUPD_NO] = "",
55 [STM32_GPIO_PUPD_UP] = "pull-up",
56 [STM32_GPIO_PUPD_DOWN] = "pull-down",
57 };
58
59 static const char * const pinmux_otype[] = {
60 [STM32_GPIO_OTYPE_PP] = "push-pull",
61 [STM32_GPIO_OTYPE_OD] = "open-drain",
62 };
63
64 static const char * const pinmux_speed[] = {
65 [STM32_GPIO_SPEED_2M] = "Low speed",
66 [STM32_GPIO_SPEED_25M] = "Medium speed",
67 [STM32_GPIO_SPEED_50M] = "High speed",
68 [STM32_GPIO_SPEED_100M] = "Very-high speed",
69 };
70
stm32_pinctrl_get_af(struct udevice * dev,unsigned int offset)71 static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
72 {
73 struct stm32_gpio_priv *priv = dev_get_priv(dev);
74 struct stm32_gpio_regs *regs = priv->regs;
75 u32 af;
76 u32 alt_shift = (offset % 8) * 4;
77 u32 alt_index = offset / 8;
78
79 af = (readl(®s->afr[alt_index]) &
80 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
81
82 return af;
83 }
84
stm32_populate_gpio_dev_list(struct udevice * dev)85 static int stm32_populate_gpio_dev_list(struct udevice *dev)
86 {
87 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
88 struct udevice *gpio_dev;
89 struct udevice *child;
90 struct stm32_gpio_bank *gpio_bank;
91 int ret;
92
93 /*
94 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
95 * a list with all gpio device reference which belongs to the
96 * current pin-controller. This list is used to find pin_name and
97 * pin muxing
98 */
99 list_for_each_entry(child, &dev->child_head, sibling_node) {
100 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
101 &gpio_dev);
102 if (ret < 0)
103 continue;
104
105 gpio_bank = malloc(sizeof(*gpio_bank));
106 if (!gpio_bank) {
107 dev_err(dev, "Not enough memory\n");
108 return -ENOMEM;
109 }
110
111 gpio_bank->gpio_dev = gpio_dev;
112 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
113 }
114
115 return 0;
116 }
117
stm32_pinctrl_get_pins_count(struct udevice * dev)118 static int stm32_pinctrl_get_pins_count(struct udevice *dev)
119 {
120 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
121 struct gpio_dev_priv *uc_priv;
122 struct stm32_gpio_bank *gpio_bank;
123
124 /*
125 * if get_pins_count has already been executed once on this
126 * pin-controller, no need to run it again
127 */
128 if (priv->pinctrl_ngpios)
129 return priv->pinctrl_ngpios;
130
131 if (list_empty(&priv->gpio_dev))
132 stm32_populate_gpio_dev_list(dev);
133 /*
134 * walk through all banks to retrieve the pin-controller
135 * pins number
136 */
137 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
138 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
139
140 priv->pinctrl_ngpios += uc_priv->gpio_count;
141 }
142
143 return priv->pinctrl_ngpios;
144 }
145
stm32_pinctrl_get_gpio_dev(struct udevice * dev,unsigned int selector,unsigned int * idx)146 static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
147 unsigned int selector,
148 unsigned int *idx)
149 {
150 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
151 struct stm32_gpio_bank *gpio_bank;
152 struct gpio_dev_priv *uc_priv;
153 int pin_count = 0;
154
155 if (list_empty(&priv->gpio_dev))
156 stm32_populate_gpio_dev_list(dev);
157
158 /* look up for the bank which owns the requested pin */
159 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
160 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
161
162 if (selector < (pin_count + uc_priv->gpio_count)) {
163 /*
164 * we found the bank, convert pin selector to
165 * gpio bank index
166 */
167 *idx = selector - pin_count;
168
169 return gpio_bank->gpio_dev;
170 }
171 pin_count += uc_priv->gpio_count;
172 }
173
174 return NULL;
175 }
176
stm32_pinctrl_get_pin_name(struct udevice * dev,unsigned int selector)177 static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
178 unsigned int selector)
179 {
180 struct gpio_dev_priv *uc_priv;
181 struct udevice *gpio_dev;
182 unsigned int gpio_idx;
183
184 /* look up for the bank which owns the requested pin */
185 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
186 if (!gpio_dev) {
187 snprintf(pin_name, PINNAME_SIZE, "Error");
188 } else {
189 uc_priv = dev_get_uclass_priv(gpio_dev);
190
191 snprintf(pin_name, PINNAME_SIZE, "%s%d",
192 uc_priv->bank_name,
193 gpio_idx);
194 }
195
196 return pin_name;
197 }
198
stm32_pinctrl_get_pin_muxing(struct udevice * dev,unsigned int selector,char * buf,int size)199 static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
200 unsigned int selector,
201 char *buf,
202 int size)
203 {
204 struct udevice *gpio_dev;
205 struct stm32_gpio_priv *priv;
206 const char *label;
207 int mode;
208 int af_num;
209 unsigned int gpio_idx;
210 u32 pupd, otype;
211 u8 speed;
212
213 /* look up for the bank which owns the requested pin */
214 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
215
216 if (!gpio_dev)
217 return -ENODEV;
218
219 mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
220 dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
221 selector, gpio_idx, mode);
222 priv = dev_get_priv(gpio_dev);
223 pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK;
224 otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
225 speed = (readl(&priv->regs->ospeedr) >> gpio_idx * 2) & OSPEED_MASK;
226
227 switch (mode) {
228 case GPIOF_UNKNOWN:
229 case GPIOF_UNUSED:
230 snprintf(buf, size, "%s", pinmux_mode[mode]);
231 break;
232 case GPIOF_FUNC:
233 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
234 snprintf(buf, size, "%s %d %s %s %s", pinmux_mode[mode], af_num,
235 pinmux_otype[otype], pinmux_bias[pupd],
236 pinmux_speed[speed]);
237 break;
238 case GPIOF_OUTPUT:
239 snprintf(buf, size, "%s %s %s %s %s",
240 pinmux_mode[mode], pinmux_otype[otype],
241 pinmux_bias[pupd], label ? label : "",
242 pinmux_speed[speed]);
243 break;
244 case GPIOF_INPUT:
245 snprintf(buf, size, "%s %s %s", pinmux_mode[mode],
246 pinmux_bias[pupd], label ? label : "");
247 break;
248 }
249
250 return 0;
251 }
252
253 #endif
254
stm32_pinctrl_probe(struct udevice * dev)255 static int stm32_pinctrl_probe(struct udevice *dev)
256 {
257 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
258 int ret;
259
260 INIT_LIST_HEAD(&priv->gpio_dev);
261
262 /* hwspinlock property is optional, just log the error */
263 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
264 if (ret)
265 dev_dbg(dev, "hwspinlock_get_by_index may have failed (%d)\n",
266 ret);
267
268 return 0;
269 }
270
stm32_gpio_config(ofnode node,struct gpio_desc * desc,const struct stm32_gpio_ctl * ctl)271 static int stm32_gpio_config(ofnode node,
272 struct gpio_desc *desc,
273 const struct stm32_gpio_ctl *ctl)
274 {
275 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
276 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(desc->dev);
277 struct stm32_gpio_regs *regs = priv->regs;
278 struct stm32_pinctrl_priv *ctrl_priv;
279 int ret;
280 u32 index;
281
282 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
283 ctl->pupd > 2 || ctl->speed > 3)
284 return -EINVAL;
285
286 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
287 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
288 if (ret == -ETIME) {
289 dev_err(desc->dev, "HWSpinlock timeout\n");
290 return ret;
291 }
292
293 index = (desc->offset & 0x07) * 4;
294 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
295 ctl->af << index);
296
297 index = desc->offset * 2;
298 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
299 ctl->mode << index);
300 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
301 ctl->speed << index);
302 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
303
304 index = desc->offset;
305 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
306
307 uc_priv->name[desc->offset] = strdup(ofnode_get_name(node));
308
309 hwspinlock_unlock(&ctrl_priv->hws);
310
311 return 0;
312 }
313
prep_gpio_dsc(struct stm32_gpio_dsc * gpio_dsc,u32 port_pin)314 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
315 {
316 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
317 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
318 log_debug("GPIO:port= %d, pin= %d\n", gpio_dsc->port, gpio_dsc->pin);
319
320 return 0;
321 }
322
prep_gpio_ctl(struct stm32_gpio_ctl * gpio_ctl,u32 gpio_fn,ofnode node)323 static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn,
324 ofnode node)
325 {
326 gpio_fn &= 0x00FF;
327 gpio_ctl->af = 0;
328
329 switch (gpio_fn) {
330 case 0:
331 gpio_ctl->mode = STM32_GPIO_MODE_IN;
332 break;
333 case 1 ... 16:
334 gpio_ctl->mode = STM32_GPIO_MODE_AF;
335 gpio_ctl->af = gpio_fn - 1;
336 break;
337 case 17:
338 gpio_ctl->mode = STM32_GPIO_MODE_AN;
339 break;
340 default:
341 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
342 break;
343 }
344
345 gpio_ctl->speed = ofnode_read_u32_default(node, "slew-rate", 0);
346
347 if (ofnode_read_bool(node, "drive-open-drain"))
348 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
349 else
350 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
351
352 if (ofnode_read_bool(node, "bias-pull-up"))
353 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
354 else if (ofnode_read_bool(node, "bias-pull-down"))
355 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
356 else
357 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
358
359 log_debug("gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
360 gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
361 gpio_ctl->pupd);
362
363 return 0;
364 }
365
stm32_pinctrl_config(ofnode node)366 static int stm32_pinctrl_config(ofnode node)
367 {
368 u32 pin_mux[MAX_PINS_ONE_IP];
369 int rv, len;
370 ofnode subnode;
371
372 /*
373 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
374 * usart1) of pin controller phandle "pinctrl-0"
375 * */
376 ofnode_for_each_subnode(subnode, node) {
377 struct stm32_gpio_dsc gpio_dsc;
378 struct stm32_gpio_ctl gpio_ctl;
379 int i;
380
381 rv = ofnode_read_size(subnode, "pinmux");
382 if (rv < 0)
383 return rv;
384 len = rv / sizeof(pin_mux[0]);
385 log_debug("No of pinmux entries= %d\n", len);
386 if (len > MAX_PINS_ONE_IP)
387 return -EINVAL;
388 rv = ofnode_read_u32_array(subnode, "pinmux", pin_mux, len);
389 if (rv < 0)
390 return rv;
391 for (i = 0; i < len; i++) {
392 struct gpio_desc desc;
393
394 log_debug("pinmux = %x\n", *(pin_mux + i));
395 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
396 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), subnode);
397 rv = uclass_get_device_by_seq(UCLASS_GPIO,
398 gpio_dsc.port,
399 &desc.dev);
400 if (rv)
401 return rv;
402 desc.offset = gpio_dsc.pin;
403 rv = stm32_gpio_config(node, &desc, &gpio_ctl);
404 log_debug("rv = %d\n\n", rv);
405 if (rv)
406 return rv;
407 }
408 }
409
410 return 0;
411 }
412
stm32_pinctrl_bind(struct udevice * dev)413 static int stm32_pinctrl_bind(struct udevice *dev)
414 {
415 ofnode node;
416 const char *name;
417 int ret;
418
419 dev_for_each_subnode(node, dev) {
420 dev_dbg(dev, "bind %s\n", ofnode_get_name(node));
421
422 if (!ofnode_is_enabled(node))
423 continue;
424
425 ofnode_get_property(node, "gpio-controller", &ret);
426 if (ret < 0)
427 continue;
428 /* Get the name of each gpio node */
429 name = ofnode_get_name(node);
430 if (!name)
431 return -EINVAL;
432
433 /* Bind each gpio node */
434 ret = device_bind_driver_to_node(dev, "gpio_stm32",
435 name, node, NULL);
436 if (ret)
437 return ret;
438
439 dev_dbg(dev, "bind %s\n", name);
440 }
441
442 return 0;
443 }
444
445 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
stm32_pinctrl_set_state(struct udevice * dev,struct udevice * config)446 static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
447 {
448 return stm32_pinctrl_config(dev_ofnode(config));
449 }
450 #else /* PINCTRL_FULL */
stm32_pinctrl_set_state_simple(struct udevice * dev,struct udevice * periph)451 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
452 struct udevice *periph)
453 {
454 const fdt32_t *list;
455 uint32_t phandle;
456 ofnode config_node;
457 int size, i, ret;
458
459 list = ofnode_get_property(dev_ofnode(periph), "pinctrl-0", &size);
460 if (!list)
461 return -EINVAL;
462
463 dev_dbg(dev, "periph->name = %s\n", periph->name);
464
465 size /= sizeof(*list);
466 for (i = 0; i < size; i++) {
467 phandle = fdt32_to_cpu(*list++);
468
469 config_node = ofnode_get_by_phandle(phandle);
470 if (!ofnode_valid(config_node)) {
471 dev_err(periph,
472 "prop pinctrl-0 index %d invalid phandle\n", i);
473 return -EINVAL;
474 }
475
476 ret = stm32_pinctrl_config(config_node);
477 if (ret)
478 return ret;
479 }
480
481 return 0;
482 }
483 #endif /* PINCTRL_FULL */
484
485 static struct pinctrl_ops stm32_pinctrl_ops = {
486 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
487 .set_state = stm32_pinctrl_set_state,
488 #else /* PINCTRL_FULL */
489 .set_state_simple = stm32_pinctrl_set_state_simple,
490 #endif /* PINCTRL_FULL */
491 #ifndef CONFIG_SPL_BUILD
492 .get_pin_name = stm32_pinctrl_get_pin_name,
493 .get_pins_count = stm32_pinctrl_get_pins_count,
494 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
495 #endif
496 };
497
498 static const struct udevice_id stm32_pinctrl_ids[] = {
499 { .compatible = "st,stm32f429-pinctrl" },
500 { .compatible = "st,stm32f469-pinctrl" },
501 { .compatible = "st,stm32f746-pinctrl" },
502 { .compatible = "st,stm32f769-pinctrl" },
503 { .compatible = "st,stm32h743-pinctrl" },
504 { .compatible = "st,stm32mp157-pinctrl" },
505 { .compatible = "st,stm32mp157-z-pinctrl" },
506 { .compatible = "st,stm32mp135-pinctrl" },
507 { }
508 };
509
510 U_BOOT_DRIVER(pinctrl_stm32) = {
511 .name = "pinctrl_stm32",
512 .id = UCLASS_PINCTRL,
513 .of_match = stm32_pinctrl_ids,
514 .ops = &stm32_pinctrl_ops,
515 .bind = stm32_pinctrl_bind,
516 .probe = stm32_pinctrl_probe,
517 .priv_auto = sizeof(struct stm32_pinctrl_priv),
518 };
519