1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Texas Instruments' K3 DDRSS driver
4 *
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8 #include <common.h>
9 #include <config.h>
10 #include <clk.h>
11 #include <div64.h>
12 #include <dm.h>
13 #include <dm/device_compat.h>
14 #include <fdt_support.h>
15 #include <ram.h>
16 #include <hang.h>
17 #include <log.h>
18 #include <asm/io.h>
19 #include <power-domain.h>
20 #include <wait_bit.h>
21 #include <power/regulator.h>
22
23 #include "lpddr4_obj_if.h"
24 #include "lpddr4_if.h"
25 #include "lpddr4_structs_if.h"
26 #include "lpddr4_ctl_regs.h"
27
28 #define SRAM_MAX 512
29
30 #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80
31 #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0
32
33 #define DDRSS_V2A_CTL_REG 0x0020
34 #define DDRSS_ECC_CTRL_REG 0x0120
35
36 #define DDRSS_ECC_CTRL_REG_ECC_EN BIT(0)
37 #define DDRSS_ECC_CTRL_REG_RMW_EN BIT(1)
38 #define DDRSS_ECC_CTRL_REG_ECC_CK BIT(2)
39 #define DDRSS_ECC_CTRL_REG_WR_ALLOC BIT(4)
40
41 #define DDRSS_ECC_R0_STR_ADDR_REG 0x0130
42 #define DDRSS_ECC_R0_END_ADDR_REG 0x0134
43 #define DDRSS_ECC_R1_STR_ADDR_REG 0x0138
44 #define DDRSS_ECC_R1_END_ADDR_REG 0x013c
45 #define DDRSS_ECC_R2_STR_ADDR_REG 0x0140
46 #define DDRSS_ECC_R2_END_ADDR_REG 0x0144
47 #define DDRSS_ECC_1B_ERR_CNT_REG 0x0150
48
49 #define SINGLE_DDR_SUBSYSTEM 0x1
50 #define MULTI_DDR_SUBSYSTEM 0x2
51
52 #define MULTI_DDR_CFG0 0x00114100
53 #define MULTI_DDR_CFG1 0x00114104
54 #define DDR_CFG_LOAD 0x00114110
55
56 enum intrlv_gran {
57 GRAN_128B,
58 GRAN_512B,
59 GRAN_2KB,
60 GRAN_4KB,
61 GRAN_16KB,
62 GRAN_32KB,
63 GRAN_512KB,
64 GRAN_1GB,
65 GRAN_1_5GB,
66 GRAN_2GB,
67 GRAN_3GB,
68 GRAN_4GB,
69 GRAN_6GB,
70 GRAN_8GB,
71 GRAN_16GB
72 };
73
74 enum intrlv_size {
75 SIZE_0,
76 SIZE_128MB,
77 SIZE_256MB,
78 SIZE_512MB,
79 SIZE_1GB,
80 SIZE_2GB,
81 SIZE_3GB,
82 SIZE_4GB,
83 SIZE_6GB,
84 SIZE_8GB,
85 SIZE_12GB,
86 SIZE_16GB,
87 SIZE_32GB
88 };
89
90 struct k3_ddrss_data {
91 u32 flags;
92 };
93
94 enum ecc_enable {
95 DISABLE_ALL = 0,
96 ENABLE_0,
97 ENABLE_1,
98 ENABLE_ALL
99 };
100
101 enum emif_config {
102 INTERLEAVE_ALL = 0,
103 SEPR0,
104 SEPR1
105 };
106
107 enum emif_active {
108 EMIF_0 = 1,
109 EMIF_1,
110 EMIF_ALL
111 };
112
113 struct k3_msmc {
114 enum intrlv_gran gran;
115 enum intrlv_size size;
116 enum ecc_enable enable;
117 enum emif_config config;
118 enum emif_active active;
119 };
120
121 #define K3_DDRSS_MAX_ECC_REGIONS 3
122
123 struct k3_ddrss_ecc_region {
124 u32 start;
125 u32 range;
126 };
127
128 struct k3_ddrss_desc {
129 struct udevice *dev;
130 void __iomem *ddrss_ss_cfg;
131 void __iomem *ddrss_ctrl_mmr;
132 void __iomem *ddrss_ctl_cfg;
133 struct power_domain ddrcfg_pwrdmn;
134 struct power_domain ddrdata_pwrdmn;
135 struct clk ddr_clk;
136 struct clk osc_clk;
137 u32 ddr_freq0;
138 u32 ddr_freq1;
139 u32 ddr_freq2;
140 u32 ddr_fhs_cnt;
141 struct udevice *vtt_supply;
142 u32 instance;
143 lpddr4_obj *driverdt;
144 lpddr4_config config;
145 lpddr4_privatedata pd;
146 struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REGIONS];
147 u64 ecc_reserved_space;
148 bool ti_ecc_enabled;
149 };
150
151 struct reginitdata {
152 u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT];
153 u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT];
154 u32 pi_regs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
155 u16 pi_regs_offs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
156 u32 phy_regs[LPDDR4_INTR_PHY_REG_COUNT];
157 u16 phy_regs_offs[LPDDR4_INTR_PHY_REG_COUNT];
158 };
159
160 #define TH_MACRO_EXP(fld, str) (fld##str)
161
162 #define TH_FLD_MASK(fld) TH_MACRO_EXP(fld, _MASK)
163 #define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT)
164 #define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH)
165 #define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR)
166 #define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET)
167
168 #define str(s) #s
169 #define xstr(s) str(s)
170
171 #define CTL_SHIFT 11
172 #define PHY_SHIFT 11
173 #define PI_SHIFT 10
174
175 #define DENALI_CTL_0_DRAM_CLASS_DDR4 0xA
176 #define DENALI_CTL_0_DRAM_CLASS_LPDDR4 0xB
177
178 #define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
179 char *i, *pstr = xstr(REG); offset = 0;\
180 for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
181 offset = offset * 10 + (*i - '0'); } \
182 } while (0)
183
k3_lpddr4_read_ddr_type(const lpddr4_privatedata * pd)184 static u32 k3_lpddr4_read_ddr_type(const lpddr4_privatedata *pd)
185 {
186 u32 status = 0U;
187 u32 offset = 0U;
188 u32 regval = 0U;
189 u32 dram_class = 0U;
190 struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
191
192 TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset);
193 status = ddrss->driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val);
194 if (status > 0U) {
195 printf("%s: Failed to read DRAM_CLASS\n", __func__);
196 hang();
197 }
198
199 dram_class = ((regval & TH_FLD_MASK(LPDDR4__DRAM_CLASS__FLD)) >>
200 TH_FLD_SHIFT(LPDDR4__DRAM_CLASS__FLD));
201 return dram_class;
202 }
203
k3_lpddr4_freq_update(struct k3_ddrss_desc * ddrss)204 static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss)
205 {
206 unsigned int req_type, counter;
207
208 for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
209 if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
210 CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10, 0x80,
211 true, 10000, false)) {
212 printf("Timeout during frequency handshake\n");
213 hang();
214 }
215
216 req_type = readl(ddrss->ddrss_ctrl_mmr +
217 CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10) & 0x03;
218
219 debug("%s: received freq change req: req type = %d, req no. = %d, instance = %d\n",
220 __func__, req_type, counter, ddrss->instance);
221
222 if (req_type == 1)
223 clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
224 else if (req_type == 2)
225 clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2);
226 else if (req_type == 0)
227 clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq0);
228 else
229 printf("%s: Invalid freq request type\n", __func__);
230
231 writel(0x1, ddrss->ddrss_ctrl_mmr +
232 CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance * 0x10);
233 if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
234 CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10, 0x80,
235 false, 10, false)) {
236 printf("Timeout during frequency handshake\n");
237 hang();
238 }
239 writel(0x0, ddrss->ddrss_ctrl_mmr +
240 CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance * 0x10);
241 }
242 }
243
k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata * pd)244 static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
245 {
246 u32 dram_class;
247 struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
248
249 debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
250
251 dram_class = k3_lpddr4_read_ddr_type(pd);
252
253 switch (dram_class) {
254 case DENALI_CTL_0_DRAM_CLASS_DDR4:
255 break;
256 case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
257 k3_lpddr4_freq_update(ddrss);
258 break;
259 default:
260 printf("Unrecognized dram_class cannot update frequency!\n");
261 }
262 }
263
k3_ddrss_init_freq(struct k3_ddrss_desc * ddrss)264 static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss)
265 {
266 u32 dram_class;
267 int ret;
268 lpddr4_privatedata *pd = &ddrss->pd;
269
270 dram_class = k3_lpddr4_read_ddr_type(pd);
271
272 switch (dram_class) {
273 case DENALI_CTL_0_DRAM_CLASS_DDR4:
274 /* Set to ddr_freq1 from DT for DDR4 */
275 ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
276 break;
277 case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
278 ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq0);
279 break;
280 default:
281 ret = -EINVAL;
282 printf("Unrecognized dram_class cannot init frequency!\n");
283 }
284
285 if (ret < 0)
286 dev_err(ddrss->dev, "ddr clk init failed: %d\n", ret);
287 else
288 ret = 0;
289
290 return ret;
291 }
292
k3_lpddr4_info_handler(const lpddr4_privatedata * pd,lpddr4_infotype infotype)293 static void k3_lpddr4_info_handler(const lpddr4_privatedata *pd,
294 lpddr4_infotype infotype)
295 {
296 if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE)
297 k3_lpddr4_ack_freq_upd_req(pd);
298 }
299
k3_ddrss_power_on(struct k3_ddrss_desc * ddrss)300 static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss)
301 {
302 int ret;
303
304 debug("%s(ddrss=%p)\n", __func__, ddrss);
305
306 ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
307 if (ret) {
308 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
309 return ret;
310 }
311
312 ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
313 if (ret) {
314 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
315 return ret;
316 }
317
318 ret = device_get_supply_regulator(ddrss->dev, "vtt-supply",
319 &ddrss->vtt_supply);
320 if (ret) {
321 dev_dbg(ddrss->dev, "vtt-supply not found.\n");
322 } else {
323 ret = regulator_set_value(ddrss->vtt_supply, 3300000);
324 if (ret)
325 return ret;
326 dev_dbg(ddrss->dev, "VTT regulator enabled, volt = %d\n",
327 regulator_get_value(ddrss->vtt_supply));
328 }
329
330 return 0;
331 }
332
k3_ddrss_ofdata_to_priv(struct udevice * dev)333 static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
334 {
335 struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
336 struct k3_ddrss_data *ddrss_data = (struct k3_ddrss_data *)dev_get_driver_data(dev);
337 phys_addr_t reg;
338 int ret;
339
340 debug("%s(dev=%p)\n", __func__, dev);
341
342 reg = dev_read_addr_name(dev, "cfg");
343 if (reg == FDT_ADDR_T_NONE) {
344 dev_err(dev, "No reg property for DDRSS wrapper logic\n");
345 return -EINVAL;
346 }
347 ddrss->ddrss_ctl_cfg = (void *)reg;
348
349 reg = dev_read_addr_name(dev, "ctrl_mmr_lp4");
350 if (reg == FDT_ADDR_T_NONE) {
351 dev_err(dev, "No reg property for CTRL MMR\n");
352 return -EINVAL;
353 }
354 ddrss->ddrss_ctrl_mmr = (void *)reg;
355
356 reg = dev_read_addr_name(dev, "ss_cfg");
357 if (reg == FDT_ADDR_T_NONE) {
358 dev_dbg(dev, "No reg property for SS Config region, but this is optional so continuing.\n");
359 ddrss->ddrss_ss_cfg = NULL;
360 } else {
361 ddrss->ddrss_ss_cfg = (void *)reg;
362 }
363
364 ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
365 if (ret) {
366 dev_err(dev, "power_domain_get() failed: %d\n", ret);
367 return ret;
368 }
369
370 ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
371 if (ret) {
372 dev_err(dev, "power_domain_get() failed: %d\n", ret);
373 return ret;
374 }
375
376 ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk);
377 if (ret)
378 dev_err(dev, "clk get failed%d\n", ret);
379
380 ret = clk_get_by_index(dev, 1, &ddrss->osc_clk);
381 if (ret)
382 dev_err(dev, "clk get failed for osc clk %d\n", ret);
383
384 /* Reading instance number for multi ddr subystems */
385 if (ddrss_data->flags & MULTI_DDR_SUBSYSTEM) {
386 ret = dev_read_u32(dev, "instance", &ddrss->instance);
387 if (ret) {
388 dev_err(dev, "missing instance property");
389 return -EINVAL;
390 }
391 } else {
392 ddrss->instance = 0;
393 }
394
395 ret = dev_read_u32(dev, "ti,ddr-freq0", &ddrss->ddr_freq0);
396 if (ret) {
397 ddrss->ddr_freq0 = clk_get_rate(&ddrss->osc_clk);
398 dev_dbg(dev,
399 "ddr freq0 not populated, using bypass frequency.\n");
400 }
401
402 ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
403 if (ret)
404 dev_err(dev, "ddr freq1 not populated %d\n", ret);
405
406 ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2);
407 if (ret)
408 dev_err(dev, "ddr freq2 not populated %d\n", ret);
409
410 ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt);
411 if (ret)
412 dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
413
414 ddrss->ti_ecc_enabled = dev_read_bool(dev, "ti,ecc-enable");
415
416 return ret;
417 }
418
k3_lpddr4_probe(struct k3_ddrss_desc * ddrss)419 void k3_lpddr4_probe(struct k3_ddrss_desc *ddrss)
420 {
421 u32 status = 0U;
422 u16 configsize = 0U;
423 lpddr4_config *config = &ddrss->config;
424
425 status = ddrss->driverdt->probe(config, &configsize);
426
427 if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
428 || (configsize > SRAM_MAX)) {
429 printf("%s: FAIL\n", __func__);
430 hang();
431 } else {
432 debug("%s: PASS\n", __func__);
433 }
434 }
435
k3_lpddr4_init(struct k3_ddrss_desc * ddrss)436 void k3_lpddr4_init(struct k3_ddrss_desc *ddrss)
437 {
438 u32 status = 0U;
439 lpddr4_config *config = &ddrss->config;
440 lpddr4_obj *driverdt = ddrss->driverdt;
441 lpddr4_privatedata *pd = &ddrss->pd;
442
443 if ((sizeof(*pd) != sizeof(lpddr4_privatedata)) || (sizeof(*pd) > SRAM_MAX)) {
444 printf("%s: FAIL\n", __func__);
445 hang();
446 }
447
448 config->ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ctl_cfg;
449 config->infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler;
450
451 status = driverdt->init(pd, config);
452
453 /* linking ddr instance to lpddr4 */
454 pd->ddr_instance = (void *)ddrss;
455
456 if ((status > 0U) ||
457 (pd->ctlbase != (struct lpddr4_ctlregs_s *)config->ctlbase) ||
458 (pd->ctlinterrupthandler != config->ctlinterrupthandler) ||
459 (pd->phyindepinterrupthandler != config->phyindepinterrupthandler)) {
460 printf("%s: FAIL\n", __func__);
461 hang();
462 } else {
463 debug("%s: PASS\n", __func__);
464 }
465 }
466
populate_data_array_from_dt(struct k3_ddrss_desc * ddrss,struct reginitdata * reginit_data)467 void populate_data_array_from_dt(struct k3_ddrss_desc *ddrss,
468 struct reginitdata *reginit_data)
469 {
470 int ret, i;
471
472 ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
473 (u32 *)reginit_data->ctl_regs,
474 LPDDR4_INTR_CTL_REG_COUNT);
475 if (ret)
476 printf("Error reading ctrl data %d\n", ret);
477
478 for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++)
479 reginit_data->ctl_regs_offs[i] = i;
480
481 ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
482 (u32 *)reginit_data->pi_regs,
483 LPDDR4_INTR_PHY_INDEP_REG_COUNT);
484 if (ret)
485 printf("Error reading PI data\n");
486
487 for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
488 reginit_data->pi_regs_offs[i] = i;
489
490 ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
491 (u32 *)reginit_data->phy_regs,
492 LPDDR4_INTR_PHY_REG_COUNT);
493 if (ret)
494 printf("Error reading PHY data %d\n", ret);
495
496 for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++)
497 reginit_data->phy_regs_offs[i] = i;
498 }
499
k3_lpddr4_hardware_reg_init(struct k3_ddrss_desc * ddrss)500 void k3_lpddr4_hardware_reg_init(struct k3_ddrss_desc *ddrss)
501 {
502 u32 status = 0U;
503 struct reginitdata reginitdata;
504 lpddr4_obj *driverdt = ddrss->driverdt;
505 lpddr4_privatedata *pd = &ddrss->pd;
506
507 populate_data_array_from_dt(ddrss, ®initdata);
508
509 status = driverdt->writectlconfig(pd, reginitdata.ctl_regs,
510 reginitdata.ctl_regs_offs,
511 LPDDR4_INTR_CTL_REG_COUNT);
512 if (!status)
513 status = driverdt->writephyindepconfig(pd, reginitdata.pi_regs,
514 reginitdata.pi_regs_offs,
515 LPDDR4_INTR_PHY_INDEP_REG_COUNT);
516 if (!status)
517 status = driverdt->writephyconfig(pd, reginitdata.phy_regs,
518 reginitdata.phy_regs_offs,
519 LPDDR4_INTR_PHY_REG_COUNT);
520 if (status) {
521 printf("%s: FAIL\n", __func__);
522 hang();
523 }
524 }
525
k3_lpddr4_start(struct k3_ddrss_desc * ddrss)526 void k3_lpddr4_start(struct k3_ddrss_desc *ddrss)
527 {
528 u32 status = 0U;
529 u32 regval = 0U;
530 u32 offset = 0U;
531 lpddr4_obj *driverdt = ddrss->driverdt;
532 lpddr4_privatedata *pd = &ddrss->pd;
533
534 TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
535
536 status = driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val);
537 if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
538 printf("%s: Pre start FAIL\n", __func__);
539 hang();
540 }
541
542 status = driverdt->start(pd);
543 if (status > 0U) {
544 printf("%s: FAIL\n", __func__);
545 hang();
546 }
547
548 status = driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val);
549 if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
550 printf("%s: Post start FAIL\n", __func__);
551 hang();
552 } else {
553 debug("%s: Post start PASS\n", __func__);
554 }
555 }
556
k3_ddrss_set_ecc_range_r0(u32 base,u32 start_address,u32 size)557 static void k3_ddrss_set_ecc_range_r0(u32 base, u32 start_address, u32 size)
558 {
559 writel((start_address) >> 16, base + DDRSS_ECC_R0_STR_ADDR_REG);
560 writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG);
561 }
562
k3_ddrss_preload_ecc_mem_region(u32 * addr,u32 size,u32 word)563 static void k3_ddrss_preload_ecc_mem_region(u32 *addr, u32 size, u32 word)
564 {
565 int i;
566
567 printf("ECC is enabled, priming DDR which will take several seconds.\n");
568
569 for (i = 0; i < (size / 4); i++)
570 addr[i] = word;
571 }
572
k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc * ddrss)573 static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss)
574 {
575 fdtdec_setup_mem_size_base_lowest();
576
577 ddrss->ecc_reserved_space = gd->ram_size;
578 do_div(ddrss->ecc_reserved_space, 9);
579
580 /* Round to clean number */
581 ddrss->ecc_reserved_space = 1ull << (fls(ddrss->ecc_reserved_space));
582 }
583
k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc * ddrss)584 static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss)
585 {
586 u32 ecc_region_start = ddrss->ecc_regions[0].start;
587 u32 ecc_range = ddrss->ecc_regions[0].range;
588 u32 base = (u32)ddrss->ddrss_ss_cfg;
589 u32 val;
590
591 /* Only Program region 0 which covers full ddr space */
592 k3_ddrss_set_ecc_range_r0(base, ecc_region_start - gd->ram_base, ecc_range);
593
594 /* Enable ECC, RMW, WR_ALLOC */
595 writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN |
596 DDRSS_ECC_CTRL_REG_WR_ALLOC, base + DDRSS_ECC_CTRL_REG);
597
598 /* Preload ECC Mem region with 0's */
599 k3_ddrss_preload_ecc_mem_region((u32 *)ecc_region_start, ecc_range,
600 0x00000000);
601
602 /* Clear Error Count Register */
603 writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG);
604
605 /* Enable ECC Check */
606 val = readl(base + DDRSS_ECC_CTRL_REG);
607 val |= DDRSS_ECC_CTRL_REG_ECC_CK;
608 writel(val, base + DDRSS_ECC_CTRL_REG);
609 }
610
k3_ddrss_probe(struct udevice * dev)611 static int k3_ddrss_probe(struct udevice *dev)
612 {
613 int ret;
614 struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
615
616 debug("%s(dev=%p)\n", __func__, dev);
617
618 ret = k3_ddrss_ofdata_to_priv(dev);
619 if (ret)
620 return ret;
621
622 ddrss->dev = dev;
623 ret = k3_ddrss_power_on(ddrss);
624 if (ret)
625 return ret;
626
627 #ifdef CONFIG_K3_AM64_DDRSS
628 /* AM64x supports only up to 2 GB SDRAM */
629 writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG);
630 writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
631 #endif
632
633 ddrss->driverdt = lpddr4_getinstance();
634
635 k3_lpddr4_probe(ddrss);
636 k3_lpddr4_init(ddrss);
637 k3_lpddr4_hardware_reg_init(ddrss);
638
639 ret = k3_ddrss_init_freq(ddrss);
640 if (ret)
641 return ret;
642
643 k3_lpddr4_start(ddrss);
644
645 if (ddrss->ti_ecc_enabled) {
646 if (!ddrss->ddrss_ss_cfg) {
647 printf("%s: ss_cfg is required if ecc is enabled but not provided.",
648 __func__);
649 return -EINVAL;
650 }
651
652 k3_ddrss_lpddr4_ecc_calc_reserved_mem(ddrss);
653
654 /* Always configure one region that covers full DDR space */
655 ddrss->ecc_regions[0].start = gd->ram_base;
656 ddrss->ecc_regions[0].range = gd->ram_size - ddrss->ecc_reserved_space;
657 k3_ddrss_lpddr4_ecc_init(ddrss);
658 }
659
660 return ret;
661 }
662
k3_ddrss_ddr_fdt_fixup(struct udevice * dev,void * blob,struct bd_info * bd)663 int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd)
664 {
665 struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
666 u64 start[CONFIG_NR_DRAM_BANKS];
667 u64 size[CONFIG_NR_DRAM_BANKS];
668 int bank;
669
670 if (ddrss->ecc_reserved_space == 0)
671 return 0;
672
673 for (bank = CONFIG_NR_DRAM_BANKS - 1; bank >= 0; bank--) {
674 if (ddrss->ecc_reserved_space > bd->bi_dram[bank].size) {
675 ddrss->ecc_reserved_space -= bd->bi_dram[bank].size;
676 bd->bi_dram[bank].size = 0;
677 } else {
678 bd->bi_dram[bank].size -= ddrss->ecc_reserved_space;
679 break;
680 }
681 }
682
683 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
684 start[bank] = bd->bi_dram[bank].start;
685 size[bank] = bd->bi_dram[bank].size;
686 }
687
688 return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
689 }
690
k3_ddrss_get_info(struct udevice * dev,struct ram_info * info)691 static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info)
692 {
693 return 0;
694 }
695
696 static struct ram_ops k3_ddrss_ops = {
697 .get_info = k3_ddrss_get_info,
698 };
699
700 static const struct k3_ddrss_data k3_data = {
701 .flags = SINGLE_DDR_SUBSYSTEM,
702 };
703
704 static const struct k3_ddrss_data j721s2_data = {
705 .flags = MULTI_DDR_SUBSYSTEM,
706 };
707
708 static const struct udevice_id k3_ddrss_ids[] = {
709 {.compatible = "ti,am62a-ddrss", .data = (ulong)&k3_data, },
710 {.compatible = "ti,am64-ddrss", .data = (ulong)&k3_data, },
711 {.compatible = "ti,j721e-ddrss", .data = (ulong)&k3_data, },
712 {.compatible = "ti,j721s2-ddrss", .data = (ulong)&j721s2_data, },
713 {}
714 };
715
716 U_BOOT_DRIVER(k3_ddrss) = {
717 .name = "k3_ddrss",
718 .id = UCLASS_RAM,
719 .of_match = k3_ddrss_ids,
720 .ops = &k3_ddrss_ops,
721 .probe = k3_ddrss_probe,
722 .priv_auto = sizeof(struct k3_ddrss_desc),
723 };
724
k3_msmc_set_config(struct k3_msmc * msmc)725 static int k3_msmc_set_config(struct k3_msmc *msmc)
726 {
727 u32 ddr_cfg0 = 0;
728 u32 ddr_cfg1 = 0;
729
730 ddr_cfg0 |= msmc->gran << 24;
731 ddr_cfg0 |= msmc->size << 16;
732 /* heartbeat_per, bit[4:0] setting to 3 is advisable */
733 ddr_cfg0 |= 3;
734
735 /* Program MULTI_DDR_CFG0 */
736 writel(ddr_cfg0, MULTI_DDR_CFG0);
737
738 ddr_cfg1 |= msmc->enable << 16;
739 ddr_cfg1 |= msmc->config << 8;
740 ddr_cfg1 |= msmc->active;
741
742 /* Program MULTI_DDR_CFG1 */
743 writel(ddr_cfg1, MULTI_DDR_CFG1);
744
745 /* Program DDR_CFG_LOAD */
746 writel(0x60000000, DDR_CFG_LOAD);
747
748 return 0;
749 }
750
k3_msmc_probe(struct udevice * dev)751 static int k3_msmc_probe(struct udevice *dev)
752 {
753 struct k3_msmc *msmc = dev_get_priv(dev);
754 int ret = 0;
755
756 /* Read the granular size from DT */
757 ret = dev_read_u32(dev, "intrlv-gran", &msmc->gran);
758 if (ret) {
759 dev_err(dev, "missing intrlv-gran property");
760 return -EINVAL;
761 }
762
763 /* Read the interleave region from DT */
764 ret = dev_read_u32(dev, "intrlv-size", &msmc->size);
765 if (ret) {
766 dev_err(dev, "missing intrlv-size property");
767 return -EINVAL;
768 }
769
770 /* Read ECC enable config */
771 ret = dev_read_u32(dev, "ecc-enable", &msmc->enable);
772 if (ret) {
773 dev_err(dev, "missing ecc-enable property");
774 return -EINVAL;
775 }
776
777 /* Read EMIF configuration */
778 ret = dev_read_u32(dev, "emif-config", &msmc->config);
779 if (ret) {
780 dev_err(dev, "missing emif-config property");
781 return -EINVAL;
782 }
783
784 /* Read EMIF active */
785 ret = dev_read_u32(dev, "emif-active", &msmc->active);
786 if (ret) {
787 dev_err(dev, "missing emif-active property");
788 return -EINVAL;
789 }
790
791 ret = k3_msmc_set_config(msmc);
792 if (ret) {
793 dev_err(dev, "error setting msmc config");
794 return -EINVAL;
795 }
796
797 return 0;
798 }
799
800 static const struct udevice_id k3_msmc_ids[] = {
801 { .compatible = "ti,j721s2-msmc"},
802 {}
803 };
804
805 U_BOOT_DRIVER(k3_msmc) = {
806 .name = "k3_msmc",
807 .of_match = k3_msmc_ids,
808 .id = UCLASS_MISC,
809 .probe = k3_msmc_probe,
810 .priv_auto = sizeof(struct k3_msmc),
811 .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
812 };
813