1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*
3 * Cadence DDR Driver
4 *
5 * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
6 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
7 */
8
9 #ifndef LPDDR4_SANITY_H
10 #define LPDDR4_SANITY_H
11
12 #include <errno.h>
13 #include <linux/types.h>
14 #include "lpddr4_if.h"
15
16 static inline u32 lpddr4_configsf(const lpddr4_config *obj);
17 static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj);
18
19 static inline u32 lpddr4_sanityfunction1(const lpddr4_config *config, const u16 *configsize);
20 static inline u32 lpddr4_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_config *cfg);
21 static inline u32 lpddr4_sanityfunction3(const lpddr4_privatedata *pd);
22 static inline u32 lpddr4_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_regblock cpp, const u32 *regvalue);
23 static inline u32 lpddr4_sanityfunction5(const lpddr4_privatedata *pd, const lpddr4_regblock cpp);
24 static inline u32 lpddr4_sanityfunction6(const lpddr4_privatedata *pd, const u64 *mmrvalue, const u8 *mmrstatus);
25 static inline u32 lpddr4_sanityfunction7(const lpddr4_privatedata *pd, const u8 *mrwstatus);
26 static inline u32 lpddr4_sanityfunction14(const lpddr4_privatedata *pd, const u64 *mask);
27 static inline u32 lpddr4_sanityfunction15(const lpddr4_privatedata *pd, const u64 *mask);
28 static inline u32 lpddr4_sanityfunction16(const lpddr4_privatedata *pd, const u32 *mask);
29 static inline u32 lpddr4_sanityfunction18(const lpddr4_privatedata *pd, const lpddr4_debuginfo *debuginfo);
30 static inline u32 lpddr4_sanityfunction19(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
31 static inline u32 lpddr4_sanityfunction21(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
32 static inline u32 lpddr4_sanityfunction22(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
33 static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
34 static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
35 static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off);
36 static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
37 static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref_val, const u32 *tras_max_val);
38 static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
39
40 #define lpddr4_probesf lpddr4_sanityfunction1
41 #define lpddr4_initsf lpddr4_sanityfunction2
42 #define lpddr4_startsf lpddr4_sanityfunction3
43 #define lpddr4_readregsf lpddr4_sanityfunction4
44 #define lpddr4_writeregsf lpddr4_sanityfunction5
45 #define lpddr4_getmmrregistersf lpddr4_sanityfunction6
46 #define lpddr4_setmmrregistersf lpddr4_sanityfunction7
47 #define lpddr4_writectlconfigsf lpddr4_sanityfunction3
48 #define lpddr4_writephyconfigsf lpddr4_sanityfunction3
49 #define lpddr4_writephyindepconfigsf lpddr4_sanityfunction3
50 #define lpddr4_readctlconfigsf lpddr4_sanityfunction3
51 #define lpddr4_readphyconfigsf lpddr4_sanityfunction3
52 #define lpddr4_readphyindepconfigsf lpddr4_sanityfunction3
53 #define lpddr4_getctlinterruptmasksf lpddr4_sanityfunction14
54 #define lpddr4_setctlinterruptmasksf lpddr4_sanityfunction15
55 #define lpddr4_getphyindepinterruptmsf lpddr4_sanityfunction16
56 #define lpddr4_setphyindepinterruptmsf lpddr4_sanityfunction16
57 #define lpddr4_getdebuginitinfosf lpddr4_sanityfunction18
58 #define lpddr4_getlpiwakeuptimesf lpddr4_sanityfunction19
59 #define lpddr4_setlpiwakeuptimesf lpddr4_sanityfunction19
60 #define lpddr4_geteccenablesf lpddr4_sanityfunction21
61 #define lpddr4_seteccenablesf lpddr4_sanityfunction22
62 #define lpddr4_getreducmodesf lpddr4_sanityfunction23
63 #define lpddr4_setreducmodesf lpddr4_sanityfunction24
64 #define lpddr4_getdbireadmodesf lpddr4_sanityfunction25
65 #define lpddr4_getdbiwritemodesf lpddr4_sanityfunction25
66 #define lpddr4_setdbimodesf lpddr4_sanityfunction27
67 #define lpddr4_getrefreshratesf lpddr4_sanityfunction28
68 #define lpddr4_setrefreshratesf lpddr4_sanityfunction29
69 #define lpddr4_refreshperchipselectsf lpddr4_sanityfunction3
70 #define lpddr4_deferredregverifysf lpddr4_sanityfunction5
71
lpddr4_configsf(const lpddr4_config * obj)72 static inline u32 lpddr4_configsf(const lpddr4_config *obj)
73 {
74 u32 ret = 0;
75
76 if (obj == NULL)
77 ret = EINVAL;
78
79 return ret;
80 }
81
lpddr4_privatedatasf(const lpddr4_privatedata * obj)82 static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj)
83 {
84 u32 ret = 0;
85
86 if (obj == NULL)
87 ret = EINVAL;
88
89 return ret;
90 }
91
lpddr4_sanityfunction1(const lpddr4_config * config,const u16 * configsize)92 static inline u32 lpddr4_sanityfunction1(const lpddr4_config *config, const u16 *configsize)
93 {
94 u32 ret = 0;
95
96 if (configsize == NULL) {
97 ret = EINVAL;
98 } else if (lpddr4_configsf(config) == EINVAL) {
99 ret = EINVAL;
100 } else {
101 }
102
103 return ret;
104 }
105
lpddr4_sanityfunction2(const lpddr4_privatedata * pd,const lpddr4_config * cfg)106 static inline u32 lpddr4_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_config *cfg)
107 {
108 u32 ret = 0;
109
110 if (lpddr4_privatedatasf(pd) == EINVAL) {
111 ret = EINVAL;
112 } else if (lpddr4_configsf(cfg) == EINVAL) {
113 ret = EINVAL;
114 } else {
115 }
116
117 return ret;
118 }
119
lpddr4_sanityfunction3(const lpddr4_privatedata * pd)120 static inline u32 lpddr4_sanityfunction3(const lpddr4_privatedata *pd)
121 {
122 u32 ret = 0;
123
124 if (lpddr4_privatedatasf(pd) == EINVAL)
125 ret = EINVAL;
126
127 return ret;
128 }
129
lpddr4_sanityfunction4(const lpddr4_privatedata * pd,const lpddr4_regblock cpp,const u32 * regvalue)130 static inline u32 lpddr4_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_regblock cpp, const u32 *regvalue)
131 {
132 u32 ret = 0;
133
134 if (regvalue == NULL) {
135 ret = EINVAL;
136 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
137 ret = EINVAL;
138 } else if (
139 (cpp != LPDDR4_CTL_REGS) &&
140 (cpp != LPDDR4_PHY_REGS) &&
141 (cpp != LPDDR4_PHY_INDEP_REGS)
142 ) {
143 ret = EINVAL;
144 } else {
145 }
146
147 return ret;
148 }
149
lpddr4_sanityfunction5(const lpddr4_privatedata * pd,const lpddr4_regblock cpp)150 static inline u32 lpddr4_sanityfunction5(const lpddr4_privatedata *pd, const lpddr4_regblock cpp)
151 {
152 u32 ret = 0;
153
154 if (lpddr4_privatedatasf(pd) == EINVAL) {
155 ret = EINVAL;
156 } else if (
157 (cpp != LPDDR4_CTL_REGS) &&
158 (cpp != LPDDR4_PHY_REGS) &&
159 (cpp != LPDDR4_PHY_INDEP_REGS)
160 ) {
161 ret = EINVAL;
162 } else {
163 }
164
165 return ret;
166 }
167
lpddr4_sanityfunction6(const lpddr4_privatedata * pd,const u64 * mmrvalue,const u8 * mmrstatus)168 static inline u32 lpddr4_sanityfunction6(const lpddr4_privatedata *pd, const u64 *mmrvalue, const u8 *mmrstatus)
169 {
170 u32 ret = 0;
171
172 if (mmrvalue == NULL) {
173 ret = EINVAL;
174 } else if (mmrstatus == NULL) {
175 ret = EINVAL;
176 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
177 ret = EINVAL;
178 } else {
179 }
180
181 return ret;
182 }
183
lpddr4_sanityfunction7(const lpddr4_privatedata * pd,const u8 * mrwstatus)184 static inline u32 lpddr4_sanityfunction7(const lpddr4_privatedata *pd, const u8 *mrwstatus)
185 {
186 u32 ret = 0;
187
188 if (mrwstatus == NULL) {
189 ret = EINVAL;
190 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
191 ret = EINVAL;
192 } else {
193 }
194
195 return ret;
196 }
197
lpddr4_sanityfunction14(const lpddr4_privatedata * pd,const u64 * mask)198 static inline u32 lpddr4_sanityfunction14(const lpddr4_privatedata *pd, const u64 *mask)
199 {
200 u32 ret = 0;
201
202 if (mask == NULL) {
203 ret = EINVAL;
204 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
205 ret = EINVAL;
206 } else {
207 }
208
209 return ret;
210 }
211
lpddr4_sanityfunction15(const lpddr4_privatedata * pd,const u64 * mask)212 static inline u32 lpddr4_sanityfunction15(const lpddr4_privatedata *pd, const u64 *mask)
213 {
214 u32 ret = 0;
215
216 if (mask == NULL) {
217 ret = EINVAL;
218 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
219 ret = EINVAL;
220 } else {
221 }
222
223 return ret;
224 }
225
lpddr4_sanityfunction16(const lpddr4_privatedata * pd,const u32 * mask)226 static inline u32 lpddr4_sanityfunction16(const lpddr4_privatedata *pd, const u32 *mask)
227 {
228 u32 ret = 0;
229
230 if (mask == NULL) {
231 ret = EINVAL;
232 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
233 ret = EINVAL;
234 } else {
235 }
236
237 return ret;
238 }
239
lpddr4_sanityfunction18(const lpddr4_privatedata * pd,const lpddr4_debuginfo * debuginfo)240 static inline u32 lpddr4_sanityfunction18(const lpddr4_privatedata *pd, const lpddr4_debuginfo *debuginfo)
241 {
242 u32 ret = 0;
243
244 if (debuginfo == NULL) {
245 ret = EINVAL;
246 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
247 ret = EINVAL;
248 } else {
249 }
250
251 return ret;
252 }
253
lpddr4_sanityfunction19(const lpddr4_privatedata * pd,const lpddr4_lpiwakeupparam * lpiwakeupparam,const lpddr4_ctlfspnum * fspnum,const u32 * cycles)254 static inline u32 lpddr4_sanityfunction19(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles)
255 {
256 u32 ret = 0;
257
258 if (lpiwakeupparam == NULL) {
259 ret = EINVAL;
260 } else if (fspnum == NULL) {
261 ret = EINVAL;
262 } else if (cycles == NULL) {
263 ret = EINVAL;
264 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
265 ret = EINVAL;
266 } else if (
267 (*lpiwakeupparam != LPDDR4_LPI_PD_WAKEUP_FN) &&
268 (*lpiwakeupparam != LPDDR4_LPI_SR_SHORT_WAKEUP_FN) &&
269 (*lpiwakeupparam != LPDDR4_LPI_SR_LONG_WAKEUP_FN) &&
270 (*lpiwakeupparam != LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) &&
271 (*lpiwakeupparam != LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) &&
272 (*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) &&
273 (*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN)
274 ) {
275 ret = EINVAL;
276 } else if (
277 (*fspnum != LPDDR4_FSP_0) &&
278 (*fspnum != LPDDR4_FSP_1) &&
279 (*fspnum != LPDDR4_FSP_2)
280 ) {
281 ret = EINVAL;
282 } else {
283 }
284
285 return ret;
286 }
287
lpddr4_sanityfunction21(const lpddr4_privatedata * pd,const lpddr4_eccenable * eccparam)288 static inline u32 lpddr4_sanityfunction21(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
289 {
290 u32 ret = 0;
291
292 if (eccparam == NULL) {
293 ret = EINVAL;
294 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
295 ret = EINVAL;
296 } else {
297 }
298
299 return ret;
300 }
301
lpddr4_sanityfunction22(const lpddr4_privatedata * pd,const lpddr4_eccenable * eccparam)302 static inline u32 lpddr4_sanityfunction22(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
303 {
304 u32 ret = 0;
305
306 if (eccparam == NULL) {
307 ret = EINVAL;
308 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
309 ret = EINVAL;
310 } else if (
311 (*eccparam != LPDDR4_ECC_DISABLED) &&
312 (*eccparam != LPDDR4_ECC_ENABLED) &&
313 (*eccparam != LPDDR4_ECC_ERR_DETECT) &&
314 (*eccparam != LPDDR4_ECC_ERR_DETECT_CORRECT)
315 ) {
316 ret = EINVAL;
317 } else {
318 }
319
320 return ret;
321 }
322
lpddr4_sanityfunction23(const lpddr4_privatedata * pd,const lpddr4_reducmode * mode)323 static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
324 {
325 u32 ret = 0;
326
327 if (mode == NULL) {
328 ret = EINVAL;
329 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
330 ret = EINVAL;
331 } else {
332 }
333
334 return ret;
335 }
336
lpddr4_sanityfunction24(const lpddr4_privatedata * pd,const lpddr4_reducmode * mode)337 static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
338 {
339 u32 ret = 0;
340
341 if (mode == NULL) {
342 ret = EINVAL;
343 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
344 ret = EINVAL;
345 } else if (
346 (*mode != LPDDR4_REDUC_ON) &&
347 (*mode != LPDDR4_REDUC_OFF)
348 ) {
349 ret = EINVAL;
350 } else {
351 }
352
353 return ret;
354 }
355
lpddr4_sanityfunction25(const lpddr4_privatedata * pd,const bool * on_off)356 static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off)
357 {
358 u32 ret = 0;
359
360 if (on_off == NULL) {
361 ret = EINVAL;
362 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
363 ret = EINVAL;
364 } else {
365 }
366
367 return ret;
368 }
369
lpddr4_sanityfunction27(const lpddr4_privatedata * pd,const lpddr4_dbimode * mode)370 static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode)
371 {
372 u32 ret = 0;
373
374 if (mode == NULL) {
375 ret = EINVAL;
376 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
377 ret = EINVAL;
378 } else if (
379 (*mode != LPDDR4_DBI_RD_ON) &&
380 (*mode != LPDDR4_DBI_RD_OFF) &&
381 (*mode != LPDDR4_DBI_WR_ON) &&
382 (*mode != LPDDR4_DBI_WR_OFF)
383 ) {
384 ret = EINVAL;
385 } else {
386 }
387
388 return ret;
389 }
390
lpddr4_sanityfunction28(const lpddr4_privatedata * pd,const lpddr4_ctlfspnum * fspnum,const u32 * tref_val,const u32 * tras_max_val)391 static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref_val, const u32 *tras_max_val)
392 {
393 u32 ret = 0;
394
395 if (fspnum == NULL) {
396 ret = EINVAL;
397 } else if (tref_val == NULL) {
398 ret = EINVAL;
399 } else if (tras_max_val == NULL) {
400 ret = EINVAL;
401 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
402 ret = EINVAL;
403 } else if (
404 (*fspnum != LPDDR4_FSP_0) &&
405 (*fspnum != LPDDR4_FSP_1) &&
406 (*fspnum != LPDDR4_FSP_2)
407 ) {
408 ret = EINVAL;
409 } else {
410 }
411
412 return ret;
413 }
414
lpddr4_sanityfunction29(const lpddr4_privatedata * pd,const lpddr4_ctlfspnum * fspnum,const u32 * tref,const u32 * tras_max)415 static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
416 {
417 u32 ret = 0;
418
419 if (fspnum == NULL) {
420 ret = EINVAL;
421 } else if (tref == NULL) {
422 ret = EINVAL;
423 } else if (tras_max == NULL) {
424 ret = EINVAL;
425 } else if (lpddr4_privatedatasf(pd) == EINVAL) {
426 ret = EINVAL;
427 } else if (
428 (*fspnum != LPDDR4_FSP_0) &&
429 (*fspnum != LPDDR4_FSP_1) &&
430 (*fspnum != LPDDR4_FSP_2)
431 ) {
432 ret = EINVAL;
433 } else {
434 }
435
436 return ret;
437 }
438
439 #endif /* LPDDR4_SANITY_H */
440