1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * RZ/N1 DDR Controller initialisation
4 *
5 * The DDR Controller register values for a specific DDR device, mode and
6 * frequency are generated using a Cadence tool.
7 *
8 * Copyright (C) 2015 Renesas Electronics Europe Ltd
9 */
10 #include <common.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <dm/device_compat.h>
14 #include <ram.h>
15 #include <regmap.h>
16 #include <syscon.h>
17 #include <asm/io.h>
18 #include <linux/delay.h>
19 #include <wait_bit.h>
20 #include <renesas/ddr_ctrl.h>
21
22 void clk_rzn1_reset_state(struct clk *clk, int on);
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 struct cadence_ddr_info {
27 struct udevice *dev;
28 void __iomem *ddrc;
29 void __iomem *phy;
30 struct clk clk_ddrc;
31 struct clk hclk_ddrc;
32 struct regmap *syscon;
33 bool enable_ecc;
34 bool enable_8bit;
35 u32 ddr_size;
36
37 /* These two used only during .probe */
38 u32 *reg0;
39 u32 *reg350;
40 };
41
cadence_readl(void __iomem * addr,unsigned int offset)42 static inline u32 cadence_readl(void __iomem *addr, unsigned int offset)
43 {
44 return readl(addr + offset);
45 }
46
cadence_writel(void __iomem * addr,unsigned int offset,u32 data)47 static inline void cadence_writel(void __iomem *addr, unsigned int offset,
48 u32 data)
49 {
50 debug("%s: addr = 0x%p, value = 0x%08x\n", __func__, addr + offset, data);
51 writel(data, addr + offset);
52 }
53
54 #define ddrc_readl(off) cadence_readl(priv->ddrc, off)
55 #define ddrc_writel(val, off) cadence_writel(priv->ddrc, off, val)
56
57 #define phy_readl(off) cadence_readl(priv->phy, off)
58 #define phy_writel(val, off) cadence_writel(priv->phy, off, val)
59
60 #define RZN1_DDR3_SINGLE_BANK 3
61 #define RZN1_DDR3_DUAL_BANK 32
62
63 #define FUNCCTRL 0x00
64 #define FUNCCTRL_MASKSDLOFS (0x18 << 16)
65 #define FUNCCTRL_DVDDQ_1_5V BIT(8)
66 #define FUNCCTRL_RESET_N BIT(0)
67 #define DLLCTRL 0x04
68 #define DLLCTRL_ASDLLOCK BIT(26)
69 #define DLLCTRL_MFSL_500MHz (2 << 1)
70 #define DLLCTRL_MDLLSTBY BIT(0)
71 #define ZQCALCTRL 0x08
72 #define ZQCALCTRL_ZQCALEND BIT(30)
73 #define ZQCALCTRL_ZQCALRSTB BIT(0)
74 #define ZQODTCTRL 0x0c
75 #define RDCTRL 0x10
76 #define RDTMG 0x14
77 #define FIFOINIT 0x18
78 #define FIFOINIT_RDPTINITEXE BIT(8)
79 #define FIFOINIT_WRPTINITEXE BIT(0)
80 #define OUTCTRL 0x1c
81 #define OUTCTRL_ADCMDOE BIT(0)
82 #define WLCTRL1 0x40
83 #define WLCTRL1_WLSTR BIT(24)
84 #define DQCALOFS1 0xe8
85
86 /* DDR PHY setup */
ddr_phy_init(struct cadence_ddr_info * priv,int ddr_type)87 static void ddr_phy_init(struct cadence_ddr_info *priv, int ddr_type)
88 {
89 u32 val;
90
91 /* Disable DDR Controller clock and FlexWAY connection */
92 clk_disable(&priv->hclk_ddrc);
93 clk_disable(&priv->clk_ddrc);
94
95 clk_rzn1_reset_state(&priv->hclk_ddrc, 0);
96 clk_rzn1_reset_state(&priv->clk_ddrc, 0);
97
98 /* Enable DDR Controller clock and FlexWAY connection */
99 clk_enable(&priv->clk_ddrc);
100 clk_enable(&priv->hclk_ddrc);
101
102 /* DDR PHY Soft reset assert */
103 ddrc_writel(FUNCCTRL_MASKSDLOFS | FUNCCTRL_DVDDQ_1_5V, FUNCCTRL);
104
105 clk_rzn1_reset_state(&priv->hclk_ddrc, 1);
106 clk_rzn1_reset_state(&priv->clk_ddrc, 1);
107
108 /* DDR PHY setup */
109 phy_writel(DLLCTRL_MFSL_500MHz | DLLCTRL_MDLLSTBY, DLLCTRL);
110 phy_writel(0x00000182, ZQCALCTRL);
111 if (ddr_type == RZN1_DDR3_DUAL_BANK)
112 phy_writel(0xAB330031, ZQODTCTRL);
113 else if (ddr_type == RZN1_DDR3_SINGLE_BANK)
114 phy_writel(0xAB320051, ZQODTCTRL);
115 else /* DDR2 */
116 phy_writel(0xAB330071, ZQODTCTRL);
117 phy_writel(0xB545B544, RDCTRL);
118 phy_writel(0x000000B0, RDTMG);
119 phy_writel(0x020A0806, OUTCTRL);
120 if (ddr_type == RZN1_DDR3_DUAL_BANK)
121 phy_writel(0x80005556, WLCTRL1);
122 else
123 phy_writel(0x80005C5D, WLCTRL1);
124 phy_writel(0x00000101, FIFOINIT);
125 phy_writel(0x00004545, DQCALOFS1);
126
127 /* Step 9 MDLL reset release */
128 val = phy_readl(DLLCTRL);
129 val &= ~DLLCTRL_MDLLSTBY;
130 phy_writel(val, DLLCTRL);
131
132 /* Step 12 Soft reset release */
133 val = phy_readl(FUNCCTRL);
134 val |= FUNCCTRL_RESET_N;
135 phy_writel(val, FUNCCTRL);
136
137 /* Step 13 FIFO pointer initialize */
138 phy_writel(FIFOINIT_RDPTINITEXE | FIFOINIT_WRPTINITEXE, FIFOINIT);
139
140 /* Step 14 Execute ZQ Calibration */
141 val = phy_readl(ZQCALCTRL);
142 val |= ZQCALCTRL_ZQCALRSTB;
143 phy_writel(val, ZQCALCTRL);
144
145 /* Step 15 Wait for 200us or more, or wait for DFIINITCOMPLETE to be "1" */
146 wait_for_bit_le32(priv->phy + DLLCTRL, DLLCTRL_ASDLLOCK, true, 1, false);
147 wait_for_bit_le32(priv->phy + ZQCALCTRL, ZQCALCTRL_ZQCALEND, true, 1, false);
148
149 /* Step 16 Enable Address and Command output */
150 val = phy_readl(OUTCTRL);
151 val |= OUTCTRL_ADCMDOE;
152 phy_writel(val, OUTCTRL);
153
154 /* Step 17 Wait for 200us or more(from MRESETB=0) */
155 udelay(200);
156 }
157
ddr_phy_enable_wl(struct cadence_ddr_info * priv)158 static void ddr_phy_enable_wl(struct cadence_ddr_info *priv)
159 {
160 u32 val;
161
162 /* Step 26 (Set Write Leveling) */
163 val = phy_readl(WLCTRL1);
164 val |= WLCTRL1_WLSTR;
165 phy_writel(val, WLCTRL1);
166 }
167
168 #define RZN1_V_DDR_BASE 0x80000000 /* RZ/N1D only */
169
rzn1_ddr3_single_bank(void * ddr_ctrl_base)170 static void rzn1_ddr3_single_bank(void *ddr_ctrl_base)
171 {
172 /* CS0 */
173 cdns_ddr_set_mr1(ddr_ctrl_base, 0,
174 MR1_ODT_IMPEDANCE_60_OHMS,
175 MR1_DRIVE_STRENGTH_40_OHMS);
176 cdns_ddr_set_mr2(ddr_ctrl_base, 0,
177 MR2_DYNAMIC_ODT_OFF,
178 MR2_SELF_REFRESH_TEMP_EXT);
179
180 /* ODT_WR_MAP_CS0 = 1, ODT_RD_MAP_CS0 = 0 */
181 cdns_ddr_set_odt_map(ddr_ctrl_base, 0, 0x0100);
182 }
183
rzn1_dram_init(struct cadence_ddr_info * priv)184 static int rzn1_dram_init(struct cadence_ddr_info *priv)
185 {
186 u32 version;
187 u32 ddr_start_addr = 0;
188
189 ddr_phy_init(priv, RZN1_DDR3_SINGLE_BANK);
190
191 /*
192 * Override DDR PHY Interface (DFI) related settings
193 * DFI is the internal interface between the DDR controller and the DDR PHY.
194 * These settings are specific to the board and can't be known by the settings
195 * provided for each DDR model within the generated include.
196 */
197 priv->reg350[351 - 350] = 0x001e0000;
198 priv->reg350[352 - 350] = 0x1e680000;
199 priv->reg350[353 - 350] = 0x02000020;
200 priv->reg350[354 - 350] = 0x02000200;
201 priv->reg350[355 - 350] = 0x00000c30;
202 priv->reg350[356 - 350] = 0x00009808;
203 priv->reg350[357 - 350] = 0x020a0706;
204 priv->reg350[372 - 350] = 0x01000000;
205
206 /*
207 * On ES1.0 devices, the DDR start address that the DDR Controller sees
208 * is the physical address of the DDR. However, later devices changed it
209 * to be 0 in order to fix an issue with DDR out-of-range detection.
210 */
211 #define RZN1_SYSCTRL_REG_VERSION 412
212 regmap_read(priv->syscon, RZN1_SYSCTRL_REG_VERSION, &version);
213 if (version == 0x10)
214 ddr_start_addr = RZN1_V_DDR_BASE;
215
216 if (priv->enable_ecc)
217 priv->ddr_size = priv->ddr_size / 2;
218
219 /* DDR Controller is always in ASYNC mode */
220 cdns_ddr_ctrl_init(priv->ddrc, 1,
221 priv->reg0, priv->reg350,
222 ddr_start_addr, priv->ddr_size,
223 priv->enable_ecc, priv->enable_8bit);
224
225 rzn1_ddr3_single_bank(priv->ddrc);
226 cdns_ddr_set_diff_cs_delays(priv->ddrc, 2, 7, 2, 2);
227 cdns_ddr_set_same_cs_delays(priv->ddrc, 0, 7, 0, 0);
228 cdns_ddr_set_odt_times(priv->ddrc, 5, 6, 6, 0, 4);
229 cdns_ddr_ctrl_start(priv->ddrc);
230
231 ddr_phy_enable_wl(priv);
232
233 if (priv->enable_ecc) {
234 /*
235 * Any read before a write will trigger an ECC un-correctable error,
236 * causing a data abort. However, this is also true for any read with a
237 * size less than the AXI bus width. So, the only sensible solution is
238 * to write to all of DDR now and take the hit...
239 */
240 memset((void *)RZN1_V_DDR_BASE, 0xff, priv->ddr_size);
241 }
242
243 return 0;
244 }
245
cadence_ddr_get_info(struct udevice * udev,struct ram_info * info)246 static int cadence_ddr_get_info(struct udevice *udev, struct ram_info *info)
247 {
248 info->base = 0;
249 info->size = gd->ram_size;
250
251 return 0;
252 }
253
254 static struct ram_ops cadence_ddr_ops = {
255 .get_info = cadence_ddr_get_info,
256 };
257
cadence_ddr_test(long * base,long maxsize)258 static int cadence_ddr_test(long *base, long maxsize)
259 {
260 volatile long *addr = base;
261 long cnt;
262
263 maxsize /= sizeof(long);
264
265 for (cnt = 1; cnt <= maxsize; cnt <<= 1) {
266 addr[cnt - 1] = ~cnt;
267 }
268
269 for (cnt = 1; cnt <= maxsize; cnt <<= 1) {
270 if (addr[cnt - 1] != ~cnt) {
271 return 0;
272 }
273 }
274
275 return 1;
276 }
277
cadence_ddr_probe(struct udevice * dev)278 static int cadence_ddr_probe(struct udevice *dev)
279 {
280 struct cadence_ddr_info *priv = dev_get_priv(dev);
281 ofnode subnode;
282 int ret;
283
284 priv->dev = dev;
285
286 priv->ddrc = dev_remap_addr_name(dev, "ddrc");
287 if (!priv->ddrc) {
288 dev_err(dev, "No reg property for Cadence DDR CTRL\n");
289 return -EINVAL;
290 }
291
292 priv->phy = dev_remap_addr_name(dev, "phy");
293 if (!priv->phy) {
294 dev_err(dev, "No reg property for Cadence DDR PHY\n");
295 return -EINVAL;
296 }
297
298 ret = clk_get_by_name(dev, "clk_ddrc", &priv->clk_ddrc);
299 if (ret) {
300 dev_err(dev, "No clock for Cadence DDR\n");
301 return ret;
302 }
303
304 ret = clk_get_by_name(dev, "hclk_ddrc", &priv->hclk_ddrc);
305 if (ret) {
306 dev_err(dev, "No HCLK for Cadence DDR\n");
307 return ret;
308 }
309
310 priv->syscon = syscon_regmap_lookup_by_phandle(dev, "syscon");
311 if (IS_ERR(priv->syscon)) {
312 dev_err(dev, "No syscon node found\n");
313 return PTR_ERR(priv->syscon);
314 }
315
316 priv->enable_ecc = dev_read_bool(dev, "enable-ecc");
317 priv->enable_8bit = dev_read_bool(dev, "enable-8bit");
318
319 priv->reg0 = malloc(88 * sizeof(u32));
320 priv->reg350 = malloc(25 * sizeof(u32));
321 if (!priv->reg0 || !priv->reg350)
322 panic("malloc failure\n");
323
324 /* There may be multiple DDR configurations to try */
325 dev_for_each_subnode(subnode, dev) {
326 ret = ofnode_read_u32(subnode, "size", &priv->ddr_size);
327 if (ret) {
328 dev_err(dev, "No size for Cadence DDR\n");
329 continue;
330 }
331
332 ret = ofnode_read_u32_array(subnode, "cadence,ctl-000", priv->reg0, 88);
333 if (ret) {
334 dev_err(dev, "No cadence,ctl-000\n");
335 continue;
336 }
337
338 ret = ofnode_read_u32_array(subnode, "cadence,ctl-350", priv->reg350, 25);
339 if (ret) {
340 dev_err(dev, "No cadence,ctl-350\n");
341 continue;
342 }
343
344 if (rzn1_dram_init(priv))
345 continue;
346
347 if (cadence_ddr_test((long *)RZN1_V_DDR_BASE, priv->ddr_size)) {
348 gd->ram_base = RZN1_V_DDR_BASE;
349 gd->ram_size = priv->ddr_size;
350 break;
351 }
352 }
353
354 if (!priv->ddr_size)
355 panic("No valid DDR to start");
356
357 free(priv->reg350);
358 free(priv->reg0);
359
360 return 0;
361 }
362
363 static const struct udevice_id cadence_ddr_ids[] = {
364 { .compatible = "cadence,ddr-ctrl" },
365 { }
366 };
367
368 U_BOOT_DRIVER(cadence_ddr) = {
369 .name = "cadence_ddr",
370 .id = UCLASS_RAM,
371 .of_match = cadence_ddr_ids,
372 .ops = &cadence_ddr_ops,
373 .probe = cadence_ddr_probe,
374 .priv_auto = sizeof(struct cadence_ddr_info),
375 .flags = DM_FLAG_PRE_RELOC,
376 };
377