1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
4  * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
5  */
6 
7 #ifndef __STARFIVE_DDR_H__
8 #define __STARFIVE_DDR_H__
9 
10 #define SEC_CTRL_ADDR		0x1000
11 #define PHY_BASE_ADDR		0x800
12 #define PHY_AC_BASE_ADDR	0x1000
13 
14 #define DDR_BUS_MASK		GENMASK(29, 24)
15 #define DDR_AXI_MASK		BIT(31)
16 #define DDR_BUS_OFFSET		0xAC
17 #define DDR_AXI_OFFSET		0xB0
18 
19 #define DDR_BUS_OSC_DIV2	0
20 #define DDR_BUS_PLL1_DIV2	1
21 #define DDR_BUS_PLL1_DIV4	2
22 #define DDR_BUS_PLL1_DIV8	3
23 #define DDR_AXI_DISABLE		0
24 #define DDR_AXI_ENABLE		1
25 
26 #define OFFSET_SEL		BIT(31)
27 #define REG2G			BIT(30)
28 #define REG4G			BIT(29)
29 #define REG8G			BIT(28)
30 #define F_ADDSET		BIT(2)
31 #define F_SET			BIT(1)
32 #define F_CLRSET		BIT(0)
33 #define REGALL			(REG2G | REG4G | REG8G)
34 #define REGSETALL		(F_SET | REGALL)
35 #define REGCLRSETALL		(F_CLRSET | REGALL)
36 #define REGADDSETALL		(F_ADDSET | REGALL)
37 
38 struct ddr_reg_cfg {
39 	u32 offset;
40 	u32 mask;
41 	u32 val;
42 	u32 flag;
43 };
44 
45 enum ddr_size_t {
46 	DDR_SIZE_2G,
47 	DDR_SIZE_4G,
48 	DDR_SIZE_8G,
49 	DDR_SIZE_16G,
50 };
51 
52 void ddr_phy_train(u32 *phyreg);
53 void ddr_phy_util(u32 *phyreg);
54 void ddr_phy_start(u32 *phyreg, enum ddr_size_t size);
55 void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size);
56 
57 #define DDR_REG_TRIGGER(addr, mask, value) \
58 	out_le32((addr), (in_le32(addr) & (mask)) | (value))
59 
60 #define DDR_REG_SET(type, val) \
61 	clrsetbits_le32(JH7110_SYS_CRG + DDR_##type##_OFFSET, \
62 		DDR_##type##_MASK, \
63 		((val) << __ffs(DDR_##type##_MASK)) & DDR_##type##_MASK)
64 
65 #endif /*__STARFIVE_DDR_H__*/
66