1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
5 */
6
7 #define LOG_CATEGORY UCLASS_RESET
8
9 #include <common.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <log.h>
13 #include <malloc.h>
14 #include <reset-uclass.h>
15 #include <stm32_rcc.h>
16 #include <asm/io.h>
17 #include <dm/device_compat.h>
18 #include <linux/bitops.h>
19
20 /* offset of register without set/clear management */
21 #define RCC_MP_GCR_OFFSET 0x10C
22
23 /* reset clear offset for STM32MP RCC */
24 #define RCC_CL 0x4
25
26 struct stm32_reset_priv {
27 fdt_addr_t base;
28 };
29
stm32_reset_assert(struct reset_ctl * reset_ctl)30 static int stm32_reset_assert(struct reset_ctl *reset_ctl)
31 {
32 struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
33 int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
34 int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);
35
36 dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
37 reset_ctl->id, bank, offset);
38
39 if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
40 if (bank != RCC_MP_GCR_OFFSET)
41 /* reset assert is done in rcc set register */
42 writel(BIT(offset), priv->base + bank);
43 else
44 clrbits_le32(priv->base + bank, BIT(offset));
45 else
46 setbits_le32(priv->base + bank, BIT(offset));
47
48 return 0;
49 }
50
stm32_reset_deassert(struct reset_ctl * reset_ctl)51 static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
52 {
53 struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
54 int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
55 int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);
56
57 dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
58 reset_ctl->id, bank, offset);
59
60 if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
61 if (bank != RCC_MP_GCR_OFFSET)
62 /* reset deassert is done in rcc clr register */
63 writel(BIT(offset), priv->base + bank + RCC_CL);
64 else
65 setbits_le32(priv->base + bank, BIT(offset));
66 else
67 clrbits_le32(priv->base + bank, BIT(offset));
68
69 return 0;
70 }
71
72 static const struct reset_ops stm32_reset_ops = {
73 .rst_assert = stm32_reset_assert,
74 .rst_deassert = stm32_reset_deassert,
75 };
76
stm32_reset_probe(struct udevice * dev)77 static int stm32_reset_probe(struct udevice *dev)
78 {
79 struct stm32_reset_priv *priv = dev_get_priv(dev);
80
81 priv->base = dev_read_addr(dev);
82 if (priv->base == FDT_ADDR_T_NONE) {
83 /* for MFD, get address of parent */
84 priv->base = dev_read_addr(dev->parent);
85 if (priv->base == FDT_ADDR_T_NONE)
86 return -EINVAL;
87 }
88
89 return 0;
90 }
91
92 U_BOOT_DRIVER(stm32_rcc_reset) = {
93 .name = "stm32_rcc_reset",
94 .id = UCLASS_RESET,
95 .probe = stm32_reset_probe,
96 .priv_auto = sizeof(struct stm32_reset_priv),
97 .ops = &stm32_reset_ops,
98 };
99