1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2011 DENX Software Engineering GmbH
4  * Heiko Schocher <hs@denx.de>
5  * Copyright (C) 2021 Dario Binacchi <dariobin@libero.it>
6  */
7 #include <common.h>
8 #include <command.h>
9 #include <dm.h>
10 #include <clk.h>
11 #include <log.h>
12 #include <rtc.h>
13 #include <asm/io.h>
14 #include <dm/device_compat.h>
15 #include <linux/delay.h>
16 
17 /* RTC registers */
18 #define OMAP_RTC_SECONDS_REG		0x00
19 #define OMAP_RTC_MINUTES_REG		0x04
20 #define OMAP_RTC_HOURS_REG		0x08
21 #define OMAP_RTC_DAYS_REG		0x0C
22 #define OMAP_RTC_MONTHS_REG		0x10
23 #define OMAP_RTC_YEARS_REG		0x14
24 #define OMAP_RTC_WEEKS_REG		0x18
25 
26 #define OMAP_RTC_CTRL_REG		0x40
27 #define OMAP_RTC_STATUS_REG		0x44
28 #define OMAP_RTC_INTERRUPTS_REG		0x48
29 
30 #define OMAP_RTC_OSC_REG		0x54
31 
32 #define OMAP_RTC_SCRATCH0_REG		0x60
33 #define OMAP_RTC_SCRATCH1_REG		0x64
34 #define OMAP_RTC_SCRATCH2_REG		0x68
35 
36 #define OMAP_RTC_KICK0_REG		0x6c
37 #define OMAP_RTC_KICK1_REG		0x70
38 
39 #define OMAP_RTC_PMIC_REG		0x98
40 
41 /* OMAP_RTC_CTRL_REG bit fields: */
42 #define OMAP_RTC_CTRL_SPLIT		BIT(7)
43 #define OMAP_RTC_CTRL_DISABLE		BIT(6)
44 #define OMAP_RTC_CTRL_SET_32_COUNTER	BIT(5)
45 #define OMAP_RTC_CTRL_TEST		BIT(4)
46 #define OMAP_RTC_CTRL_MODE_12_24	BIT(3)
47 #define OMAP_RTC_CTRL_AUTO_COMP		BIT(2)
48 #define OMAP_RTC_CTRL_ROUND_30S		BIT(1)
49 #define OMAP_RTC_CTRL_STOP		BIT(0)
50 
51 /* OMAP_RTC_STATUS_REG bit fields */
52 #define OMAP_RTC_STATUS_POWER_UP	BIT(7)
53 #define OMAP_RTC_STATUS_ALARM2		BIT(7)
54 #define OMAP_RTC_STATUS_ALARM		BIT(6)
55 #define OMAP_RTC_STATUS_1D_EVENT	BIT(5)
56 #define OMAP_RTC_STATUS_1H_EVENT	BIT(4)
57 #define OMAP_RTC_STATUS_1M_EVENT	BIT(3)
58 #define OMAP_RTC_STATUS_1S_EVENT	BIT(2)
59 #define OMAP_RTC_STATUS_RUN		BIT(1)
60 #define OMAP_RTC_STATUS_BUSY		BIT(0)
61 
62 /* OMAP_RTC_OSC_REG bit fields */
63 #define OMAP_RTC_OSC_32KCLK_EN		BIT(6)
64 #define OMAP_RTC_OSC_SEL_32KCLK_SRC	BIT(3)
65 #define OMAP_RTC_OSC_OSC32K_GZ_DISABLE	BIT(4)
66 
67 /* OMAP_RTC_KICKER values */
68 #define	OMAP_RTC_KICK0_VALUE		0x83e70b13
69 #define	OMAP_RTC_KICK1_VALUE		0x95a4f1e0
70 
71 struct omap_rtc_device_type {
72 	bool has_32kclk_en;
73 	bool has_irqwakeen;
74 	bool has_pmic_mode;
75 	bool has_power_up_reset;
76 };
77 
78 struct omap_rtc_priv {
79 	fdt_addr_t base;
80 	u8 max_reg;
81 	struct udevice *dev;
82 	struct clk clk;
83 	bool has_ext_clk;
84 	const struct omap_rtc_device_type *type;
85 };
86 
omap_rtc_readb(struct omap_rtc_priv * priv,unsigned int reg)87 static inline u8 omap_rtc_readb(struct omap_rtc_priv *priv, unsigned int reg)
88 {
89 	return readb(priv->base + reg);
90 }
91 
omap_rtc_readl(struct omap_rtc_priv * priv,unsigned int reg)92 static inline u32 omap_rtc_readl(struct omap_rtc_priv *priv, unsigned int reg)
93 {
94 	return readl(priv->base + reg);
95 }
96 
omap_rtc_writeb(struct omap_rtc_priv * priv,unsigned int reg,u8 val)97 static inline void omap_rtc_writeb(struct omap_rtc_priv *priv, unsigned int reg,
98 				   u8 val)
99 {
100 	writeb(val, priv->base + reg);
101 }
102 
omap_rtc_writel(struct omap_rtc_priv * priv,unsigned int reg,u32 val)103 static inline void omap_rtc_writel(struct omap_rtc_priv *priv, unsigned int reg,
104 				   u32 val)
105 {
106 	writel(val, priv->base + reg);
107 }
108 
omap_rtc_unlock(struct omap_rtc_priv * priv)109 static inline void omap_rtc_unlock(struct omap_rtc_priv *priv)
110 {
111 	omap_rtc_writel(priv, OMAP_RTC_KICK0_REG, OMAP_RTC_KICK0_VALUE);
112 	omap_rtc_writel(priv, OMAP_RTC_KICK1_REG, OMAP_RTC_KICK1_VALUE);
113 }
114 
omap_rtc_lock(struct omap_rtc_priv * priv)115 static inline void omap_rtc_lock(struct omap_rtc_priv *priv)
116 {
117 	omap_rtc_writel(priv, OMAP_RTC_KICK0_REG, 0);
118 	omap_rtc_writel(priv, OMAP_RTC_KICK1_REG, 0);
119 }
120 
omap_rtc_wait_not_busy(struct omap_rtc_priv * priv)121 static int omap_rtc_wait_not_busy(struct omap_rtc_priv *priv)
122 {
123 	int count;
124 	u8 status;
125 
126 	status = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
127 	if ((status & OMAP_RTC_STATUS_RUN) != OMAP_RTC_STATUS_RUN) {
128 		printf("RTC doesn't run\n");
129 		return -1;
130 	}
131 
132 	/* BUSY may stay active for 1/32768 second (~30 usec) */
133 	for (count = 0; count < 50; count++) {
134 		if (!(status & OMAP_RTC_STATUS_BUSY))
135 			break;
136 
137 		udelay(1);
138 		status = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
139 	}
140 
141 	/* now we have ~15 usec to read/write various registers */
142 	return 0;
143 }
144 
omap_rtc_reset(struct udevice * dev)145 static int omap_rtc_reset(struct udevice *dev)
146 {
147 	struct omap_rtc_priv *priv = dev_get_priv(dev);
148 
149 	/* run RTC counter */
150 	omap_rtc_writeb(priv, OMAP_RTC_CTRL_REG, 0x01);
151 	return 0;
152 }
153 
omap_rtc_set(struct udevice * dev,const struct rtc_time * tm)154 static int omap_rtc_set(struct udevice *dev, const struct rtc_time *tm)
155 {
156 	struct omap_rtc_priv *priv = dev_get_priv(dev);
157 	int ret;
158 
159 	ret = omap_rtc_wait_not_busy(priv);
160 	if (ret)
161 		return ret;
162 
163 	omap_rtc_unlock(priv);
164 	omap_rtc_writeb(priv, OMAP_RTC_YEARS_REG, bin2bcd(tm->tm_year % 100));
165 	omap_rtc_writeb(priv, OMAP_RTC_MONTHS_REG, bin2bcd(tm->tm_mon));
166 	omap_rtc_writeb(priv, OMAP_RTC_WEEKS_REG, bin2bcd(tm->tm_wday));
167 	omap_rtc_writeb(priv, OMAP_RTC_DAYS_REG, bin2bcd(tm->tm_mday));
168 	omap_rtc_writeb(priv, OMAP_RTC_HOURS_REG, bin2bcd(tm->tm_hour));
169 	omap_rtc_writeb(priv, OMAP_RTC_MINUTES_REG, bin2bcd(tm->tm_min));
170 	omap_rtc_writeb(priv, OMAP_RTC_SECONDS_REG, bin2bcd(tm->tm_sec));
171 	omap_rtc_lock(priv);
172 
173 	dev_dbg(dev, "Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
174 		tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour,
175 		tm->tm_min, tm->tm_sec);
176 
177 	return 0;
178 }
179 
omap_rtc_get(struct udevice * dev,struct rtc_time * tm)180 static int omap_rtc_get(struct udevice *dev, struct rtc_time *tm)
181 {
182 	struct omap_rtc_priv *priv = dev_get_priv(dev);
183 	unsigned long sec, min, hour, mday, wday, mon_cent, year;
184 	int ret;
185 
186 	ret = omap_rtc_wait_not_busy(priv);
187 	if (ret)
188 		return ret;
189 
190 	sec = omap_rtc_readb(priv, OMAP_RTC_SECONDS_REG);
191 	min = omap_rtc_readb(priv, OMAP_RTC_MINUTES_REG);
192 	hour = omap_rtc_readb(priv, OMAP_RTC_HOURS_REG);
193 	mday = omap_rtc_readb(priv, OMAP_RTC_DAYS_REG);
194 	wday = omap_rtc_readb(priv, OMAP_RTC_WEEKS_REG);
195 	mon_cent = omap_rtc_readb(priv, OMAP_RTC_MONTHS_REG);
196 	year = omap_rtc_readb(priv, OMAP_RTC_YEARS_REG);
197 
198 	dev_dbg(dev,
199 		"Get RTC year: %02lx mon/cent: %02lx mday: %02lx wday: %02lx "
200 		"hr: %02lx min: %02lx sec: %02lx\n",
201 		year, mon_cent, mday, wday,
202 		hour, min, sec);
203 
204 	tm->tm_sec  = bcd2bin(sec  & 0x7F);
205 	tm->tm_min  = bcd2bin(min  & 0x7F);
206 	tm->tm_hour = bcd2bin(hour & 0x3F);
207 	tm->tm_mday = bcd2bin(mday & 0x3F);
208 	tm->tm_mon  = bcd2bin(mon_cent & 0x1F);
209 	tm->tm_year = bcd2bin(year) + 2000;
210 	tm->tm_wday = bcd2bin(wday & 0x07);
211 	tm->tm_yday = 0;
212 	tm->tm_isdst = 0;
213 
214 	dev_dbg(dev, "Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
215 		tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour,
216 		tm->tm_min, tm->tm_sec);
217 
218 	return 0;
219 }
220 
omap_rtc_scratch_read(struct udevice * dev,uint offset,u8 * buffer,uint len)221 static int omap_rtc_scratch_read(struct udevice *dev, uint offset,
222 				 u8 *buffer, uint len)
223 {
224 	struct omap_rtc_priv *priv = dev_get_priv(dev);
225 	u32 *val = (u32 *)buffer;
226 	unsigned int reg;
227 	int i;
228 
229 	if (len & 3)
230 		return -EFAULT;
231 
232 	for (i = 0; i < len / 4; i++) {
233 		reg = OMAP_RTC_SCRATCH0_REG + offset + (i * 4);
234 		if (reg >= OMAP_RTC_KICK0_REG)
235 			return -EFAULT;
236 
237 		val[i] = omap_rtc_readl(priv, reg);
238 	}
239 
240 	return 0;
241 }
242 
omap_rtc_scratch_write(struct udevice * dev,uint offset,const u8 * buffer,uint len)243 static int omap_rtc_scratch_write(struct udevice *dev, uint offset,
244 				  const u8 *buffer, uint len)
245 {
246 	struct omap_rtc_priv *priv = dev_get_priv(dev);
247 	u32 *val = (u32 *)buffer;
248 	unsigned int reg;
249 	int i;
250 
251 	if (len & 3)
252 		return -EFAULT;
253 
254 	omap_rtc_unlock(priv);
255 	for (i = 0; i < len / 4; i++) {
256 		reg = OMAP_RTC_SCRATCH0_REG + offset + (i * 4);
257 		if (reg >= OMAP_RTC_KICK0_REG)
258 			return -EFAULT;
259 
260 		omap_rtc_writel(priv, reg, val[i]);
261 	}
262 	omap_rtc_lock(priv);
263 
264 	return 0;
265 }
266 
omap_rtc_remove(struct udevice * dev)267 static int omap_rtc_remove(struct udevice *dev)
268 {
269 	struct omap_rtc_priv *priv = dev_get_priv(dev);
270 	u8 reg;
271 
272 	if (priv->clk.dev)
273 		clk_disable(&priv->clk);
274 
275 	omap_rtc_unlock(priv);
276 
277 	/* leave rtc running, but disable irqs */
278 	omap_rtc_writeb(priv, OMAP_RTC_INTERRUPTS_REG, 0);
279 
280 	if (priv->has_ext_clk) {
281 		reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
282 		reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
283 		omap_rtc_writeb(priv, OMAP_RTC_OSC_REG, reg);
284 	}
285 
286 	omap_rtc_lock(priv);
287 	return 0;
288 }
289 
omap_rtc_probe(struct udevice * dev)290 static int omap_rtc_probe(struct udevice *dev)
291 {
292 	struct omap_rtc_priv *priv = dev_get_priv(dev);
293 	struct rtc_time tm;
294 	u8 reg, mask, new_ctrl;
295 
296 	priv->dev = dev;
297 	priv->type = (struct omap_rtc_device_type *)dev_get_driver_data(dev);
298 	priv->max_reg = OMAP_RTC_PMIC_REG;
299 
300 	if (!clk_get_by_name(dev, "ext-clk", &priv->clk))
301 		priv->has_ext_clk = true;
302 	else
303 		clk_get_by_name(dev, "int-clk", &priv->clk);
304 
305 	if (priv->clk.dev)
306 		clk_enable(&priv->clk);
307 	else
308 		dev_warn(dev, "missing clock\n");
309 
310 	omap_rtc_unlock(priv);
311 
312 	/*
313 	 * disable interrupts
314 	 *
315 	 * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
316 	 */
317 	omap_rtc_writel(priv, OMAP_RTC_INTERRUPTS_REG, 0);
318 
319 	if (priv->type->has_32kclk_en) {
320 		reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
321 		omap_rtc_writeb(priv, OMAP_RTC_OSC_REG,
322 				reg | OMAP_RTC_OSC_32KCLK_EN);
323 	}
324 
325 	/* clear old status */
326 	reg = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
327 
328 	mask = OMAP_RTC_STATUS_ALARM;
329 
330 	if (priv->type->has_pmic_mode)
331 		mask |= OMAP_RTC_STATUS_ALARM2;
332 
333 	if (priv->type->has_power_up_reset) {
334 		mask |= OMAP_RTC_STATUS_POWER_UP;
335 		if (reg & OMAP_RTC_STATUS_POWER_UP)
336 			dev_info(dev, "RTC power up reset detected\n");
337 	}
338 
339 	if (reg & mask)
340 		omap_rtc_writeb(priv, OMAP_RTC_STATUS_REG, reg & mask);
341 
342 	/* On boards with split power, RTC_ON_NOFF won't reset the RTC */
343 	reg = omap_rtc_readb(priv, OMAP_RTC_CTRL_REG);
344 	if (reg & OMAP_RTC_CTRL_STOP)
345 		dev_info(dev, "already running\n");
346 
347 	/* force to 24 hour mode */
348 	new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
349 	new_ctrl |= OMAP_RTC_CTRL_STOP;
350 
351 	/*
352 	 * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
353 	 *
354 	 *  - Device wake-up capability setting should come through chip
355 	 *    init logic. OMAP1 boards should initialize the "wakeup capable"
356 	 *    flag in the platform device if the board is wired right for
357 	 *    being woken up by RTC alarm. For OMAP-L138, this capability
358 	 *    is built into the SoC by the "Deep Sleep" capability.
359 	 *
360 	 *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
361 	 *    rather than nPWRON_RESET, should forcibly enable split
362 	 *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
363 	 *    is write-only, and always reads as zero...)
364 	 */
365 
366 	if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
367 		dev_info(dev, "split power mode\n");
368 
369 	if (reg != new_ctrl)
370 		omap_rtc_writeb(priv, OMAP_RTC_CTRL_REG, new_ctrl);
371 
372 	/*
373 	 * If we have the external clock then switch to it so we can keep
374 	 * ticking across suspend.
375 	 */
376 	if (priv->has_ext_clk) {
377 		reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
378 		reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
379 		reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
380 		omap_rtc_writeb(priv, OMAP_RTC_OSC_REG, reg);
381 	}
382 
383 	omap_rtc_lock(priv);
384 
385 	if (omap_rtc_get(dev, &tm)) {
386 		dev_err(dev, "failed to get datetime\n");
387 	} else if (tm.tm_year == 2000 && tm.tm_mon == 1 && tm.tm_mday == 1 &&
388 		   tm.tm_wday == 0) {
389 		tm.tm_wday = 6;
390 		omap_rtc_set(dev, &tm);
391 	}
392 
393 	return 0;
394 }
395 
omap_rtc_of_to_plat(struct udevice * dev)396 static int omap_rtc_of_to_plat(struct udevice *dev)
397 {
398 	struct omap_rtc_priv *priv = dev_get_priv(dev);
399 
400 	priv->base = dev_read_addr(dev);
401 	if (priv->base == FDT_ADDR_T_NONE) {
402 		dev_err(dev, "invalid address\n");
403 		return -EINVAL;
404 	}
405 
406 	dev_dbg(dev, "base=%pa\n", &priv->base);
407 	return 0;
408 }
409 
410 static const struct rtc_ops omap_rtc_ops = {
411 	.get = omap_rtc_get,
412 	.set = omap_rtc_set,
413 	.reset = omap_rtc_reset,
414 	.read = omap_rtc_scratch_read,
415 	.write = omap_rtc_scratch_write,
416 };
417 
418 static const struct omap_rtc_device_type omap_rtc_am3352_type = {
419 	.has_32kclk_en	= true,
420 	.has_irqwakeen	= true,
421 	.has_pmic_mode	= true,
422 };
423 
424 static const struct omap_rtc_device_type omap_rtc_da830_type = {
425 	.has_32kclk_en	= false,
426 	.has_irqwakeen	= false,
427 	.has_pmic_mode	= false,
428 };
429 
430 static const struct udevice_id omap_rtc_ids[] = {
431 	{.compatible = "ti,am3352-rtc", .data = (ulong)&omap_rtc_am3352_type},
432 	{.compatible = "ti,da830-rtc", .data = (ulong)&omap_rtc_da830_type }
433 };
434 
435 U_BOOT_DRIVER(omap_rtc) = {
436 	.name = "omap_rtc",
437 	.id = UCLASS_RTC,
438 	.of_match = omap_rtc_ids,
439 	.ops = &omap_rtc_ops,
440 	.of_to_plat = omap_rtc_of_to_plat,
441 	.probe = omap_rtc_probe,
442 	.remove = omap_rtc_remove,
443 	.priv_auto = sizeof(struct omap_rtc_priv),
444 };
445