1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Qualcomm GENI serial engine UART driver
4 *
5 * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
6 *
7 * Based on Linux driver.
8 */
9
10 #include <asm/io.h>
11 #include <clk.h>
12 #include <common.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <linux/delay.h>
16 #include <misc.h>
17 #include <serial.h>
18
19 #define UART_OVERSAMPLING 32
20 #define STALE_TIMEOUT 160
21
22 #define USEC_PER_SEC 1000000L
23
24 /* Registers*/
25 #define GENI_FORCE_DEFAULT_REG 0x20
26 #define GENI_SER_M_CLK_CFG 0x48
27 #define GENI_SER_S_CLK_CFG 0x4C
28 #define SE_HW_PARAM_0 0xE24
29 #define SE_GENI_STATUS 0x40
30 #define SE_GENI_S_CMD0 0x630
31 #define SE_GENI_S_CMD_CTRL_REG 0x634
32 #define SE_GENI_S_IRQ_CLEAR 0x648
33 #define SE_GENI_S_IRQ_STATUS 0x640
34 #define SE_GENI_S_IRQ_EN 0x644
35 #define SE_GENI_M_CMD0 0x600
36 #define SE_GENI_M_CMD_CTRL_REG 0x604
37 #define SE_GENI_M_IRQ_CLEAR 0x618
38 #define SE_GENI_M_IRQ_STATUS 0x610
39 #define SE_GENI_M_IRQ_EN 0x614
40 #define SE_GENI_TX_FIFOn 0x700
41 #define SE_GENI_RX_FIFOn 0x780
42 #define SE_GENI_TX_FIFO_STATUS 0x800
43 #define SE_GENI_RX_FIFO_STATUS 0x804
44 #define SE_GENI_TX_WATERMARK_REG 0x80C
45 #define SE_GENI_TX_PACKING_CFG0 0x260
46 #define SE_GENI_TX_PACKING_CFG1 0x264
47 #define SE_GENI_RX_PACKING_CFG0 0x284
48 #define SE_GENI_RX_PACKING_CFG1 0x288
49 #define SE_UART_RX_STALE_CNT 0x294
50 #define SE_UART_TX_TRANS_LEN 0x270
51 #define SE_UART_TX_STOP_BIT_LEN 0x26c
52 #define SE_UART_TX_WORD_LEN 0x268
53 #define SE_UART_RX_WORD_LEN 0x28c
54 #define SE_UART_TX_TRANS_CFG 0x25c
55 #define SE_UART_TX_PARITY_CFG 0x2a4
56 #define SE_UART_RX_TRANS_CFG 0x280
57 #define SE_UART_RX_PARITY_CFG 0x2a8
58
59 #define M_TX_FIFO_WATERMARK_EN (BIT(30))
60 #define DEF_TX_WM 2
61 /* GENI_FORCE_DEFAULT_REG fields */
62 #define FORCE_DEFAULT (BIT(0))
63
64 #define S_CMD_ABORT_EN (BIT(5))
65
66 #define UART_START_READ 0x1
67
68 /* GENI_M_CMD_CTRL_REG */
69 #define M_GENI_CMD_CANCEL (BIT(2))
70 #define M_GENI_CMD_ABORT (BIT(1))
71 #define M_GENI_DISABLE (BIT(0))
72
73 #define M_CMD_ABORT_EN (BIT(5))
74 #define M_CMD_DONE_EN (BIT(0))
75 #define M_CMD_DONE_DISABLE_MASK (~M_CMD_DONE_EN)
76
77 #define S_GENI_CMD_ABORT (BIT(1))
78
79 /* GENI_S_CMD0 fields */
80 #define S_OPCODE_MSK (GENMASK(31, 27))
81 #define S_PARAMS_MSK (GENMASK(26, 0))
82
83 /* GENI_STATUS fields */
84 #define M_GENI_CMD_ACTIVE (BIT(0))
85 #define S_GENI_CMD_ACTIVE (BIT(12))
86 #define M_CMD_DONE_EN (BIT(0))
87 #define S_CMD_DONE_EN (BIT(0))
88
89 #define M_OPCODE_SHIFT 27
90 #define S_OPCODE_SHIFT 27
91 #define M_TX_FIFO_WATERMARK_EN (BIT(30))
92 #define UART_START_TX 0x1
93 #define UART_CTS_MASK (BIT(1))
94 #define M_SEC_IRQ_EN (BIT(31))
95 #define TX_FIFO_WC_MSK (GENMASK(27, 0))
96 #define RX_FIFO_WC_MSK (GENMASK(24, 0))
97
98 #define S_RX_FIFO_WATERMARK_EN (BIT(26))
99 #define S_RX_FIFO_LAST_EN (BIT(27))
100 #define M_RX_FIFO_WATERMARK_EN (BIT(26))
101 #define M_RX_FIFO_LAST_EN (BIT(27))
102
103 /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
104 #define SER_CLK_EN (BIT(0))
105 #define CLK_DIV_MSK (GENMASK(15, 4))
106 #define CLK_DIV_SHFT 4
107
108 /* SE_HW_PARAM_0 fields */
109 #define TX_FIFO_WIDTH_MSK (GENMASK(29, 24))
110 #define TX_FIFO_WIDTH_SHFT 24
111 #define TX_FIFO_DEPTH_MSK (GENMASK(21, 16))
112 #define TX_FIFO_DEPTH_SHFT 16
113
114 /* GENI SE QUP Registers */
115 #define QUP_HW_VER_REG 0x4
116 #define QUP_SE_VERSION_2_5 0x20050000
117
118 /*
119 * Predefined packing configuration of the serial engine (CFG0, CFG1 regs)
120 * for uart mode.
121 *
122 * Defines following configuration:
123 * - Bits of data per transfer word 8
124 * - Number of words per fifo element 4
125 * - Transfer from MSB to LSB or vice-versa false
126 */
127 #define UART_PACKING_CFG0 0xf
128 #define UART_PACKING_CFG1 0x0
129
130 DECLARE_GLOBAL_DATA_PTR;
131
132 struct msm_serial_data {
133 phys_addr_t base;
134 u32 baud;
135 u32 oversampling;
136 };
137
138 unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
139 32000000, 48000000, 64000000, 80000000,
140 96000000, 100000000};
141
142 /**
143 * get_clk_cfg() - Get clock rate to apply on clock supplier.
144 * @clk_freq: Desired clock frequency after build-in divider.
145 *
146 * Return: frequency, supported by clock supplier, multiple of clk_freq.
147 */
get_clk_cfg(unsigned long clk_freq)148 static int get_clk_cfg(unsigned long clk_freq)
149 {
150 for (int i = 0; i < ARRAY_SIZE(root_freq); i++) {
151 if (!(root_freq[i] % clk_freq))
152 return root_freq[i];
153 }
154 return 0;
155 }
156
157 /**
158 * get_clk_div_rate() - Find clock supplier frequency, and calculate divisor.
159 * @baud: Baudrate.
160 * @sampling_rate: Clock ticks per character.
161 * @clk_div: Pointer to calculated divisor.
162 *
163 * This function searches for suitable frequency for clock supplier,
164 * calculates divisor for internal divider, based on found frequency,
165 * and stores divisor under clk_div pointer.
166 *
167 * Return: frequency, supported by clock supplier, multiple of clk_freq.
168 */
get_clk_div_rate(u32 baud,u64 sampling_rate,u32 * clk_div)169 static int get_clk_div_rate(u32 baud, u64 sampling_rate, u32 *clk_div)
170 {
171 unsigned long ser_clk;
172 unsigned long desired_clk;
173
174 desired_clk = baud * sampling_rate;
175 ser_clk = get_clk_cfg(desired_clk);
176 if (!ser_clk) {
177 pr_err("%s: Can't find matching DFS entry for baud %d\n",
178 __func__, baud);
179 return ser_clk;
180 }
181
182 *clk_div = ser_clk / desired_clk;
183 return ser_clk;
184 }
185
geni_serial_set_clock_rate(struct udevice * dev,u64 rate)186 static int geni_serial_set_clock_rate(struct udevice *dev, u64 rate)
187 {
188 struct clk *clk;
189 int ret;
190
191 clk = devm_clk_get(dev, NULL);
192 if (!clk)
193 return -EINVAL;
194
195 ret = clk_set_rate(clk, rate);
196 return ret;
197 }
198
199 /**
200 * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine
201 * @base: Pointer to the concerned serial engine.
202 *
203 * This function is used to get the depth i.e. number of elements in the
204 * TX fifo of the serial engine.
205 *
206 * Return: TX fifo depth in units of FIFO words.
207 */
geni_se_get_tx_fifo_depth(long base)208 static inline u32 geni_se_get_tx_fifo_depth(long base)
209 {
210 u32 tx_fifo_depth;
211
212 tx_fifo_depth = ((readl(base + SE_HW_PARAM_0) & TX_FIFO_DEPTH_MSK) >>
213 TX_FIFO_DEPTH_SHFT);
214 return tx_fifo_depth;
215 }
216
217 /**
218 * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine
219 * @base: Pointer to the concerned serial engine.
220 *
221 * This function is used to get the width i.e. word size per element in the
222 * TX fifo of the serial engine.
223 *
224 * Return: TX fifo width in bits
225 */
geni_se_get_tx_fifo_width(long base)226 static inline u32 geni_se_get_tx_fifo_width(long base)
227 {
228 u32 tx_fifo_width;
229
230 tx_fifo_width = ((readl(base + SE_HW_PARAM_0) & TX_FIFO_WIDTH_MSK) >>
231 TX_FIFO_WIDTH_SHFT);
232 return tx_fifo_width;
233 }
234
geni_serial_baud(phys_addr_t base_address,u32 clk_div,int baud)235 static inline void geni_serial_baud(phys_addr_t base_address, u32 clk_div,
236 int baud)
237 {
238 u32 s_clk_cfg = 0;
239
240 s_clk_cfg |= SER_CLK_EN;
241 s_clk_cfg |= (clk_div << CLK_DIV_SHFT);
242
243 writel(s_clk_cfg, base_address + GENI_SER_M_CLK_CFG);
244 writel(s_clk_cfg, base_address + GENI_SER_S_CLK_CFG);
245 }
246
msm_serial_setbrg(struct udevice * dev,int baud)247 static int msm_serial_setbrg(struct udevice *dev, int baud)
248 {
249 struct msm_serial_data *priv = dev_get_priv(dev);
250 u64 clk_rate;
251 u32 clk_div;
252
253 priv->baud = baud;
254
255 clk_rate = get_clk_div_rate(baud, priv->oversampling, &clk_div);
256 geni_serial_set_clock_rate(dev, clk_rate);
257 geni_serial_baud(priv->base, clk_div, baud);
258
259 return 0;
260 }
261
262 /**
263 * qcom_geni_serial_poll_bit() - Poll reg bit until desired value or timeout.
264 * @base: Pointer to the concerned serial engine.
265 * @offset: Offset to register address.
266 * @field: AND bitmask for desired bit.
267 * @set: Desired bit value.
268 *
269 * This function is used to get the width i.e. word size per element in the
270 * TX fifo of the serial engine.
271 *
272 * Return: true, when register bit equals desired value, false, when timeout
273 * reached.
274 */
qcom_geni_serial_poll_bit(const struct udevice * dev,int offset,int field,bool set)275 static bool qcom_geni_serial_poll_bit(const struct udevice *dev, int offset,
276 int field, bool set)
277 {
278 u32 reg;
279 struct msm_serial_data *priv = dev_get_priv(dev);
280 unsigned int baud;
281 unsigned int tx_fifo_depth;
282 unsigned int tx_fifo_width;
283 unsigned int fifo_bits;
284 unsigned long timeout_us = 10000;
285
286 baud = 115200;
287
288 if (priv) {
289 baud = priv->baud;
290 if (!baud)
291 baud = 115200;
292 tx_fifo_depth = geni_se_get_tx_fifo_depth(priv->base);
293 tx_fifo_width = geni_se_get_tx_fifo_width(priv->base);
294 fifo_bits = tx_fifo_depth * tx_fifo_width;
295 /*
296 * Total polling iterations based on FIFO worth of bytes to be
297 * sent at current baud. Add a little fluff to the wait.
298 */
299 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
300 }
301
302 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
303 while (timeout_us) {
304 reg = readl(priv->base + offset);
305 if ((bool)(reg & field) == set)
306 return true;
307 udelay(10);
308 timeout_us -= 10;
309 }
310 return false;
311 }
312
qcom_geni_serial_setup_tx(u64 base,u32 xmit_size)313 static void qcom_geni_serial_setup_tx(u64 base, u32 xmit_size)
314 {
315 u32 m_cmd;
316
317 writel(xmit_size, base + SE_UART_TX_TRANS_LEN);
318 m_cmd = UART_START_TX << M_OPCODE_SHIFT;
319 writel(m_cmd, base + SE_GENI_M_CMD0);
320 }
321
qcom_geni_serial_poll_tx_done(const struct udevice * dev)322 static inline void qcom_geni_serial_poll_tx_done(const struct udevice *dev)
323 {
324 struct msm_serial_data *priv = dev_get_priv(dev);
325 int done = 0;
326 u32 irq_clear = M_CMD_DONE_EN;
327
328 done = qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS,
329 M_CMD_DONE_EN, true);
330 if (!done) {
331 writel(M_GENI_CMD_ABORT, priv->base + SE_GENI_M_CMD_CTRL_REG);
332 irq_clear |= M_CMD_ABORT_EN;
333 qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS,
334 M_CMD_ABORT_EN, true);
335 }
336 writel(irq_clear, priv->base + SE_GENI_M_IRQ_CLEAR);
337 }
338
qcom_geni_serial_tx_empty(u64 base)339 static u32 qcom_geni_serial_tx_empty(u64 base)
340 {
341 return !readl(base + SE_GENI_TX_FIFO_STATUS);
342 }
343
344 /**
345 * geni_se_setup_s_cmd() - Setup the secondary sequencer
346 * @se: Pointer to the concerned serial engine.
347 * @cmd: Command/Operation to setup in the secondary sequencer.
348 * @params: Parameter for the sequencer command.
349 *
350 * This function is used to configure the secondary sequencer with the
351 * command and its associated parameters.
352 */
geni_se_setup_s_cmd(u64 base,u32 cmd,u32 params)353 static inline void geni_se_setup_s_cmd(u64 base, u32 cmd, u32 params)
354 {
355 u32 s_cmd;
356
357 s_cmd = readl(base + SE_GENI_S_CMD0);
358 s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
359 s_cmd |= (cmd << S_OPCODE_SHIFT);
360 s_cmd |= (params & S_PARAMS_MSK);
361 writel(s_cmd, base + SE_GENI_S_CMD0);
362 }
363
qcom_geni_serial_start_tx(u64 base)364 static void qcom_geni_serial_start_tx(u64 base)
365 {
366 u32 irq_en;
367 u32 status;
368
369 status = readl(base + SE_GENI_STATUS);
370 if (status & M_GENI_CMD_ACTIVE)
371 return;
372
373 if (!qcom_geni_serial_tx_empty(base))
374 return;
375
376 irq_en = readl(base + SE_GENI_M_IRQ_EN);
377 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
378
379 writel(DEF_TX_WM, base + SE_GENI_TX_WATERMARK_REG);
380 writel(irq_en, base + SE_GENI_M_IRQ_EN);
381 }
382
qcom_geni_serial_start_rx(struct udevice * dev)383 static void qcom_geni_serial_start_rx(struct udevice *dev)
384 {
385 u32 status;
386 struct msm_serial_data *priv = dev_get_priv(dev);
387
388 status = readl(priv->base + SE_GENI_STATUS);
389
390 geni_se_setup_s_cmd(priv->base, UART_START_READ, 0);
391
392 setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
393 setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
394 }
395
qcom_geni_serial_abort_rx(struct udevice * dev)396 static void qcom_geni_serial_abort_rx(struct udevice *dev)
397 {
398 struct msm_serial_data *priv = dev_get_priv(dev);
399
400 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
401
402 writel(S_GENI_CMD_ABORT, priv->base + SE_GENI_S_CMD_CTRL_REG);
403 qcom_geni_serial_poll_bit(dev, SE_GENI_S_CMD_CTRL_REG,
404 S_GENI_CMD_ABORT, false);
405 writel(irq_clear, priv->base + SE_GENI_S_IRQ_CLEAR);
406 writel(FORCE_DEFAULT, priv->base + GENI_FORCE_DEFAULT_REG);
407 }
408
msm_geni_serial_setup_rx(struct udevice * dev)409 static void msm_geni_serial_setup_rx(struct udevice *dev)
410 {
411 struct msm_serial_data *priv = dev_get_priv(dev);
412
413 qcom_geni_serial_abort_rx(dev);
414
415 writel(UART_PACKING_CFG0, priv->base + SE_GENI_RX_PACKING_CFG0);
416 writel(UART_PACKING_CFG1, priv->base + SE_GENI_RX_PACKING_CFG1);
417
418 geni_se_setup_s_cmd(priv->base, UART_START_READ, 0);
419
420 setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
421 setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
422 }
423
msm_serial_putc(struct udevice * dev,const char ch)424 static int msm_serial_putc(struct udevice *dev, const char ch)
425 {
426 struct msm_serial_data *priv = dev_get_priv(dev);
427
428 writel(DEF_TX_WM, priv->base + SE_GENI_TX_WATERMARK_REG);
429 qcom_geni_serial_setup_tx(priv->base, 1);
430
431 qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS,
432 M_TX_FIFO_WATERMARK_EN, true);
433
434 writel(ch, priv->base + SE_GENI_TX_FIFOn);
435 writel(M_TX_FIFO_WATERMARK_EN, priv->base + SE_GENI_M_IRQ_CLEAR);
436
437 qcom_geni_serial_poll_tx_done(dev);
438
439 return 0;
440 }
441
msm_serial_getc(struct udevice * dev)442 static int msm_serial_getc(struct udevice *dev)
443 {
444 struct msm_serial_data *priv = dev_get_priv(dev);
445 u32 rx_fifo;
446 u32 m_irq_status;
447 u32 s_irq_status;
448
449 writel(1 << S_OPCODE_SHIFT, priv->base + SE_GENI_S_CMD0);
450
451 qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS, M_SEC_IRQ_EN,
452 true);
453
454 m_irq_status = readl(priv->base + SE_GENI_M_IRQ_STATUS);
455 s_irq_status = readl(priv->base + SE_GENI_S_IRQ_STATUS);
456 writel(m_irq_status, priv->base + SE_GENI_M_IRQ_CLEAR);
457 writel(s_irq_status, priv->base + SE_GENI_S_IRQ_CLEAR);
458 qcom_geni_serial_poll_bit(dev, SE_GENI_RX_FIFO_STATUS, RX_FIFO_WC_MSK,
459 true);
460
461 if (!readl(priv->base + SE_GENI_RX_FIFO_STATUS))
462 return 0;
463
464 rx_fifo = readl(priv->base + SE_GENI_RX_FIFOn);
465 return rx_fifo & 0xff;
466 }
467
msm_serial_pending(struct udevice * dev,bool input)468 static int msm_serial_pending(struct udevice *dev, bool input)
469 {
470 struct msm_serial_data *priv = dev_get_priv(dev);
471
472 if (input)
473 return readl(priv->base + SE_GENI_RX_FIFO_STATUS) &
474 RX_FIFO_WC_MSK;
475 else
476 return readl(priv->base + SE_GENI_TX_FIFO_STATUS) &
477 TX_FIFO_WC_MSK;
478
479 return 0;
480 }
481
482 static const struct dm_serial_ops msm_serial_ops = {
483 .putc = msm_serial_putc,
484 .pending = msm_serial_pending,
485 .getc = msm_serial_getc,
486 .setbrg = msm_serial_setbrg,
487 };
488
geni_set_oversampling(struct udevice * dev)489 static void geni_set_oversampling(struct udevice *dev)
490 {
491 struct msm_serial_data *priv = dev_get_priv(dev);
492 struct udevice *parent_dev = dev_get_parent(dev);
493 u32 geni_se_version;
494 int ret;
495
496 priv->oversampling = UART_OVERSAMPLING;
497
498 /*
499 * It could happen that GENI SE IP is missing in the board's device
500 * tree or GENI UART node is a direct child of SoC device tree node.
501 */
502 if (device_get_uclass_id(parent_dev) != UCLASS_MISC)
503 return;
504
505 ret = misc_read(parent_dev, QUP_HW_VER_REG,
506 &geni_se_version, sizeof(geni_se_version));
507 if (ret != sizeof(geni_se_version))
508 return;
509
510 if (geni_se_version >= QUP_SE_VERSION_2_5)
511 priv->oversampling /= 2;
512 }
513
geni_serial_init(struct udevice * dev)514 static inline void geni_serial_init(struct udevice *dev)
515 {
516 struct msm_serial_data *priv = dev_get_priv(dev);
517 phys_addr_t base_address = priv->base;
518 u32 tx_trans_cfg;
519 u32 tx_parity_cfg = 0; /* Disable Tx Parity */
520 u32 rx_trans_cfg = 0;
521 u32 rx_parity_cfg = 0; /* Disable Rx Parity */
522 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
523 u32 bits_per_char;
524
525 /*
526 * Ignore Flow control.
527 * n = 8.
528 */
529 tx_trans_cfg = UART_CTS_MASK;
530 bits_per_char = BITS_PER_BYTE;
531
532 /*
533 * Make an unconditional cancel on the main sequencer to reset
534 * it else we could end up in data loss scenarios.
535 */
536 qcom_geni_serial_poll_tx_done(dev);
537 qcom_geni_serial_abort_rx(dev);
538
539 writel(UART_PACKING_CFG0, base_address + SE_GENI_TX_PACKING_CFG0);
540 writel(UART_PACKING_CFG1, base_address + SE_GENI_TX_PACKING_CFG1);
541 writel(UART_PACKING_CFG0, base_address + SE_GENI_RX_PACKING_CFG0);
542 writel(UART_PACKING_CFG1, base_address + SE_GENI_RX_PACKING_CFG1);
543
544 writel(tx_trans_cfg, base_address + SE_UART_TX_TRANS_CFG);
545 writel(tx_parity_cfg, base_address + SE_UART_TX_PARITY_CFG);
546 writel(rx_trans_cfg, base_address + SE_UART_RX_TRANS_CFG);
547 writel(rx_parity_cfg, base_address + SE_UART_RX_PARITY_CFG);
548 writel(bits_per_char, base_address + SE_UART_TX_WORD_LEN);
549 writel(bits_per_char, base_address + SE_UART_RX_WORD_LEN);
550 writel(stop_bit_len, base_address + SE_UART_TX_STOP_BIT_LEN);
551 }
552
msm_serial_probe(struct udevice * dev)553 static int msm_serial_probe(struct udevice *dev)
554 {
555 struct msm_serial_data *priv = dev_get_priv(dev);
556
557 geni_set_oversampling(dev);
558
559 /* No need to reinitialize the UART after relocation */
560 if (gd->flags & GD_FLG_RELOC)
561 return 0;
562
563 geni_serial_init(dev);
564 msm_geni_serial_setup_rx(dev);
565 qcom_geni_serial_start_rx(dev);
566 qcom_geni_serial_start_tx(priv->base);
567
568 return 0;
569 }
570
msm_serial_ofdata_to_platdata(struct udevice * dev)571 static int msm_serial_ofdata_to_platdata(struct udevice *dev)
572 {
573 struct msm_serial_data *priv = dev_get_priv(dev);
574
575 priv->base = dev_read_addr(dev);
576 if (priv->base == FDT_ADDR_T_NONE)
577 return -EINVAL;
578
579 return 0;
580 }
581
582 static const struct udevice_id msm_serial_ids[] = {
583 { .compatible = "qcom,geni-debug-uart" },
584 { }
585 };
586
587 U_BOOT_DRIVER(serial_msm_geni) = {
588 .name = "serial_msm_geni",
589 .id = UCLASS_SERIAL,
590 .of_match = msm_serial_ids,
591 .of_to_plat = msm_serial_ofdata_to_platdata,
592 .priv_auto = sizeof(struct msm_serial_data),
593 .probe = msm_serial_probe,
594 .ops = &msm_serial_ops,
595 .flags = DM_FLAG_PRE_RELOC,
596 };
597
598 #ifdef CONFIG_DEBUG_UART_MSM_GENI
599
600 static struct msm_serial_data init_serial_data = {
601 .base = CONFIG_VAL(DEBUG_UART_BASE)
602 };
603
604 /* Serial dumb device, to reuse driver code */
605 static struct udevice init_dev = {
606 .priv_ = &init_serial_data,
607 };
608
609 #include <debug_uart.h>
610
611 #define CLK_DIV (CONFIG_DEBUG_UART_CLOCK / \
612 (CONFIG_BAUDRATE * UART_OVERSAMPLING))
613 #if (CONFIG_DEBUG_UART_CLOCK % (CONFIG_BAUDRATE * UART_OVERSAMPLING) > 0)
614 #error Clocks cannot be set at early debug. Change CONFIG_BAUDRATE
615 #endif
616
_debug_uart_init(void)617 static inline void _debug_uart_init(void)
618 {
619 phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
620
621 geni_serial_init(&init_dev);
622 geni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE);
623 qcom_geni_serial_start_tx(base);
624 }
625
_debug_uart_putc(int ch)626 static inline void _debug_uart_putc(int ch)
627 {
628 phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
629
630 writel(DEF_TX_WM, base + SE_GENI_TX_WATERMARK_REG);
631 qcom_geni_serial_setup_tx(base, 1);
632 qcom_geni_serial_poll_bit(&init_dev, SE_GENI_M_IRQ_STATUS,
633 M_TX_FIFO_WATERMARK_EN, true);
634
635 writel(ch, base + SE_GENI_TX_FIFOn);
636 writel(M_TX_FIFO_WATERMARK_EN, base + SE_GENI_M_IRQ_CLEAR);
637 qcom_geni_serial_poll_tx_done(&init_dev);
638 }
639
640 DEBUG_UART_FUNCS
641
642 #endif
643