1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
5 */
6
7 #include <clk.h>
8 #include <common.h>
9 #include <debug_uart.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <fdtdec.h>
13 #include <log.h>
14 #include <watchdog.h>
15 #include <asm/io.h>
16 #include <dm/device_compat.h>
17 #include <linux/bitops.h>
18 #include <linux/compiler.h>
19 #include <serial.h>
20 #include <linux/err.h>
21
22 #define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */
23 #define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */
24 #define ZYNQ_UART_SR_TXEMPTY BIT(3) /* TX FIFO empty */
25 #define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */
26
27 #define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */
28 #define ZYNQ_UART_CR_RX_EN BIT(2) /* RX enabled */
29 #define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */
30 #define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */
31
32 #define ZYNQ_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
33 #define ZYNQ_UART_MR_STOPMODE_1_5_BIT 0x00000040 /* 1.5 stop bits */
34 #define ZYNQ_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
35
36 #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
37 #define ZYNQ_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
38 #define ZYNQ_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
39
40 #define ZYNQ_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
41 #define ZYNQ_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
42 #define ZYNQ_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
43
44 struct uart_zynq {
45 u32 control; /* 0x0 - Control Register [8:0] */
46 u32 mode; /* 0x4 - Mode Register [10:0] */
47 u32 reserved1[4];
48 u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
49 u32 reserved2[4];
50 u32 channel_sts; /* 0x2c - Channel Status [11:0] */
51 u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
52 u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
53 };
54
55 struct zynq_uart_plat {
56 struct uart_zynq *regs;
57 };
58
59 /* Set up the baud rate */
_uart_zynq_serial_setbrg(struct uart_zynq * regs,unsigned long clock,unsigned long baud)60 static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
61 unsigned long clock, unsigned long baud)
62 {
63 /* Calculation results. */
64 unsigned int calc_bauderror, bdiv, bgen;
65 unsigned long calc_baud = 0;
66
67 /* Covering case where input clock is so slow */
68 if (clock < 1000000 && baud > 4800)
69 baud = 4800;
70
71 /* master clock
72 * Baud rate = ------------------
73 * bgen * (bdiv + 1)
74 *
75 * Find acceptable values for baud generation.
76 */
77 for (bdiv = 4; bdiv < 255; bdiv++) {
78 bgen = DIV_ROUND_CLOSEST(clock, baud * (bdiv + 1));
79 if (bgen < 2 || bgen > 65535)
80 continue;
81
82 calc_baud = clock / (bgen * (bdiv + 1));
83
84 /*
85 * Use first calculated baudrate with
86 * an acceptable (<3%) error
87 */
88 if (baud > calc_baud)
89 calc_bauderror = baud - calc_baud;
90 else
91 calc_bauderror = calc_baud - baud;
92 if (((calc_bauderror * 100) / baud) < 3)
93 break;
94 }
95
96 writel(bdiv, ®s->baud_rate_divider);
97 writel(bgen, ®s->baud_rate_gen);
98 }
99
100 /* Initialize the UART, with...some settings. */
_uart_zynq_serial_init(struct uart_zynq * regs)101 static void _uart_zynq_serial_init(struct uart_zynq *regs)
102 {
103 /* RX/TX enabled & reset */
104 writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
105 ZYNQ_UART_CR_RXRST, ®s->control);
106 writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */
107 }
108
_uart_zynq_serial_putc(struct uart_zynq * regs,const char c)109 static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
110 {
111 if (IS_ENABLED(CONFIG_DEBUG_UART_ZYNQ)) {
112 if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY))
113 return -EAGAIN;
114 } else {
115 if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL)
116 return -EAGAIN;
117 }
118
119 writel(c, ®s->tx_rx_fifo);
120
121 return 0;
122 }
123
zynq_serial_setbrg(struct udevice * dev,int baudrate)124 static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
125 {
126 struct zynq_uart_plat *plat = dev_get_plat(dev);
127 unsigned long clock;
128
129 int ret;
130 struct clk clk;
131
132 ret = clk_get_by_index(dev, 0, &clk);
133 if (ret < 0) {
134 dev_err(dev, "failed to get clock\n");
135 return ret;
136 }
137
138 clock = clk_get_rate(&clk);
139 if (IS_ERR_VALUE(clock)) {
140 dev_err(dev, "failed to get rate\n");
141 return clock;
142 }
143 debug("%s: CLK %ld\n", __func__, clock);
144
145 ret = clk_enable(&clk);
146 if (ret) {
147 dev_err(dev, "failed to enable clock\n");
148 return ret;
149 }
150
151 _uart_zynq_serial_setbrg(plat->regs, clock, baudrate);
152
153 return 0;
154 }
155
156 #if !defined(CONFIG_SPL_BUILD)
zynq_serial_setconfig(struct udevice * dev,uint serial_config)157 static int zynq_serial_setconfig(struct udevice *dev, uint serial_config)
158 {
159 struct zynq_uart_plat *plat = dev_get_plat(dev);
160 struct uart_zynq *regs = plat->regs;
161 u32 val = 0;
162
163 switch (SERIAL_GET_BITS(serial_config)) {
164 case SERIAL_6_BITS:
165 val |= ZYNQ_UART_MR_CHARLEN_6_BIT;
166 break;
167 case SERIAL_7_BITS:
168 val |= ZYNQ_UART_MR_CHARLEN_7_BIT;
169 break;
170 case SERIAL_8_BITS:
171 val |= ZYNQ_UART_MR_CHARLEN_8_BIT;
172 break;
173 default:
174 return -ENOTSUPP; /* not supported in driver */
175 }
176
177 switch (SERIAL_GET_STOP(serial_config)) {
178 case SERIAL_ONE_STOP:
179 val |= ZYNQ_UART_MR_STOPMODE_1_BIT;
180 break;
181 case SERIAL_ONE_HALF_STOP:
182 val |= ZYNQ_UART_MR_STOPMODE_1_5_BIT;
183 break;
184 case SERIAL_TWO_STOP:
185 val |= ZYNQ_UART_MR_STOPMODE_2_BIT;
186 break;
187 default:
188 return -ENOTSUPP; /* not supported in driver */
189 }
190
191 switch (SERIAL_GET_PARITY(serial_config)) {
192 case SERIAL_PAR_NONE:
193 val |= ZYNQ_UART_MR_PARITY_NONE;
194 break;
195 case SERIAL_PAR_ODD:
196 val |= ZYNQ_UART_MR_PARITY_ODD;
197 break;
198 case SERIAL_PAR_EVEN:
199 val |= ZYNQ_UART_MR_PARITY_EVEN;
200 break;
201 default:
202 return -ENOTSUPP; /* not supported in driver */
203 }
204
205 writel(val, ®s->mode);
206
207 return 0;
208 }
209 #else
210 #define zynq_serial_setconfig NULL
211 #endif
212
zynq_serial_probe(struct udevice * dev)213 static int zynq_serial_probe(struct udevice *dev)
214 {
215 struct zynq_uart_plat *plat = dev_get_plat(dev);
216 struct uart_zynq *regs = plat->regs;
217 u32 val;
218
219 /* No need to reinitialize the UART if TX already enabled */
220 val = readl(®s->control);
221 if (val & ZYNQ_UART_CR_TX_EN)
222 return 0;
223
224 _uart_zynq_serial_init(plat->regs);
225
226 return 0;
227 }
228
zynq_serial_getc(struct udevice * dev)229 static int zynq_serial_getc(struct udevice *dev)
230 {
231 struct zynq_uart_plat *plat = dev_get_plat(dev);
232 struct uart_zynq *regs = plat->regs;
233
234 if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
235 return -EAGAIN;
236
237 return readl(®s->tx_rx_fifo);
238 }
239
zynq_serial_putc(struct udevice * dev,const char ch)240 static int zynq_serial_putc(struct udevice *dev, const char ch)
241 {
242 struct zynq_uart_plat *plat = dev_get_plat(dev);
243
244 return _uart_zynq_serial_putc(plat->regs, ch);
245 }
246
zynq_serial_pending(struct udevice * dev,bool input)247 static int zynq_serial_pending(struct udevice *dev, bool input)
248 {
249 struct zynq_uart_plat *plat = dev_get_plat(dev);
250 struct uart_zynq *regs = plat->regs;
251
252 if (input)
253 return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
254 else
255 return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
256 }
257
zynq_serial_of_to_plat(struct udevice * dev)258 static int zynq_serial_of_to_plat(struct udevice *dev)
259 {
260 struct zynq_uart_plat *plat = dev_get_plat(dev);
261
262 plat->regs = dev_read_addr_ptr(dev);
263 if (!plat->regs)
264 return -EINVAL;
265
266 return 0;
267 }
268
269 static const struct dm_serial_ops zynq_serial_ops = {
270 .putc = zynq_serial_putc,
271 .pending = zynq_serial_pending,
272 .getc = zynq_serial_getc,
273 .setbrg = zynq_serial_setbrg,
274 .setconfig = zynq_serial_setconfig,
275 };
276
277 static const struct udevice_id zynq_serial_ids[] = {
278 { .compatible = "xlnx,xuartps" },
279 { .compatible = "cdns,uart-r1p8" },
280 { .compatible = "cdns,uart-r1p12" },
281 { .compatible = "xlnx,zynqmp-uart" },
282 { }
283 };
284
285 U_BOOT_DRIVER(serial_zynq) = {
286 .name = "serial_zynq",
287 .id = UCLASS_SERIAL,
288 .of_match = zynq_serial_ids,
289 .of_to_plat = zynq_serial_of_to_plat,
290 .plat_auto = sizeof(struct zynq_uart_plat),
291 .probe = zynq_serial_probe,
292 .ops = &zynq_serial_ops,
293 };
294
295 #ifdef CONFIG_DEBUG_UART_ZYNQ
_debug_uart_init(void)296 static inline void _debug_uart_init(void)
297 {
298 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE);
299
300 _uart_zynq_serial_init(regs);
301 _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
302 CONFIG_BAUDRATE);
303 }
304
_debug_uart_putc(int ch)305 static inline void _debug_uart_putc(int ch)
306 {
307 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE);
308
309 while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
310 schedule();
311 }
312
313 DEBUG_UART_FUNCS
314
315 #endif
316