1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012
4 * Altera Corporation <www.altera.com>
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <log.h>
10 #include <asm-generic/io.h>
11 #include <dm.h>
12 #include <fdtdec.h>
13 #include <malloc.h>
14 #include <reset.h>
15 #include <spi.h>
16 #include <spi-mem.h>
17 #include <dm/device_compat.h>
18 #include <linux/err.h>
19 #include <linux/errno.h>
20 #include <linux/sizes.h>
21 #include <zynqmp_firmware.h>
22 #include "cadence_qspi.h"
23 #include <dt-bindings/power/xlnx-versal-power.h>
24
25 #define NSEC_PER_SEC 1000000000L
26
27 #define CQSPI_STIG_READ 0
28 #define CQSPI_STIG_WRITE 1
29 #define CQSPI_READ 2
30 #define CQSPI_WRITE 3
31
cadence_qspi_apb_dma_read(struct cadence_spi_priv * priv,const struct spi_mem_op * op)32 __weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
33 const struct spi_mem_op *op)
34 {
35 return 0;
36 }
37
cadence_qspi_versal_flash_reset(struct udevice * dev)38 __weak int cadence_qspi_versal_flash_reset(struct udevice *dev)
39 {
40 return 0;
41 }
42
cadence_spi_write_speed(struct udevice * bus,uint hz)43 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
44 {
45 struct cadence_spi_priv *priv = dev_get_priv(bus);
46
47 cadence_qspi_apb_config_baudrate_div(priv->regbase,
48 priv->ref_clk_hz, hz);
49
50 /* Reconfigure delay timing if speed is changed. */
51 cadence_qspi_apb_delay(priv->regbase, priv->ref_clk_hz, hz,
52 priv->tshsl_ns, priv->tsd2d_ns,
53 priv->tchsh_ns, priv->tslch_ns);
54
55 return 0;
56 }
57
cadence_spi_read_id(struct cadence_spi_priv * priv,u8 len,u8 * idcode)58 static int cadence_spi_read_id(struct cadence_spi_priv *priv, u8 len,
59 u8 *idcode)
60 {
61 int err;
62
63 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
64 SPI_MEM_OP_NO_ADDR,
65 SPI_MEM_OP_NO_DUMMY,
66 SPI_MEM_OP_DATA_IN(len, idcode, 1));
67
68 err = cadence_qspi_apb_command_read_setup(priv, &op);
69 if (!err)
70 err = cadence_qspi_apb_command_read(priv, &op);
71
72 return err;
73 }
74
75 /* Calibration sequence to determine the read data capture delay register */
spi_calibration(struct udevice * bus,uint hz)76 static int spi_calibration(struct udevice *bus, uint hz)
77 {
78 struct cadence_spi_priv *priv = dev_get_priv(bus);
79 void *base = priv->regbase;
80 unsigned int idcode = 0, temp = 0;
81 int err = 0, i, range_lo = -1, range_hi = -1;
82
83 /* start with slowest clock (1 MHz) */
84 cadence_spi_write_speed(bus, 1000000);
85
86 /* configure the read data capture delay register to 0 */
87 cadence_qspi_apb_readdata_capture(base, 1, 0);
88
89 /* Enable QSPI */
90 cadence_qspi_apb_controller_enable(base);
91
92 /* read the ID which will be our golden value */
93 err = cadence_spi_read_id(priv, 3, (u8 *)&idcode);
94 if (err) {
95 puts("SF: Calibration failed (read)\n");
96 return err;
97 }
98
99 /* use back the intended clock and find low range */
100 cadence_spi_write_speed(bus, hz);
101 for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
102 /* Disable QSPI */
103 cadence_qspi_apb_controller_disable(base);
104
105 /* reconfigure the read data capture delay register */
106 cadence_qspi_apb_readdata_capture(base, 1, i);
107
108 /* Enable back QSPI */
109 cadence_qspi_apb_controller_enable(base);
110
111 /* issue a RDID to get the ID value */
112 err = cadence_spi_read_id(priv, 3, (u8 *)&temp);
113 if (err) {
114 puts("SF: Calibration failed (read)\n");
115 return err;
116 }
117
118 /* search for range lo */
119 if (range_lo == -1 && temp == idcode) {
120 range_lo = i;
121 continue;
122 }
123
124 /* search for range hi */
125 if (range_lo != -1 && temp != idcode) {
126 range_hi = i - 1;
127 break;
128 }
129 range_hi = i;
130 }
131
132 if (range_lo == -1) {
133 puts("SF: Calibration failed (low range)\n");
134 return err;
135 }
136
137 /* Disable QSPI for subsequent initialization */
138 cadence_qspi_apb_controller_disable(base);
139
140 /* configure the final value for read data capture delay register */
141 cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
142 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
143 (range_hi + range_lo) / 2, range_lo, range_hi);
144
145 /* just to ensure we do once only when speed or chip select change */
146 priv->qspi_calibrated_hz = hz;
147 priv->qspi_calibrated_cs = spi_chip_select(bus);
148
149 return 0;
150 }
151
cadence_spi_set_speed(struct udevice * bus,uint hz)152 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
153 {
154 struct cadence_spi_priv *priv = dev_get_priv(bus);
155 int err;
156
157 if (!hz || hz > priv->max_hz)
158 hz = priv->max_hz;
159 /* Disable QSPI */
160 cadence_qspi_apb_controller_disable(priv->regbase);
161
162 /*
163 * If the device tree already provides a read delay value, use that
164 * instead of calibrating.
165 */
166 if (priv->read_delay >= 0) {
167 cadence_spi_write_speed(bus, hz);
168 cadence_qspi_apb_readdata_capture(priv->regbase, 1,
169 priv->read_delay);
170 } else if (priv->previous_hz != hz ||
171 priv->qspi_calibrated_hz != hz ||
172 priv->qspi_calibrated_cs != spi_chip_select(bus)) {
173 /*
174 * Calibration required for different current SCLK speed,
175 * requested SCLK speed or chip select
176 */
177 err = spi_calibration(bus, hz);
178 if (err)
179 return err;
180
181 /* prevent calibration run when same as previous request */
182 priv->previous_hz = hz;
183 }
184
185 /* Enable QSPI */
186 cadence_qspi_apb_controller_enable(priv->regbase);
187
188 debug("%s: speed=%d\n", __func__, hz);
189
190 return 0;
191 }
192
cadence_spi_probe(struct udevice * bus)193 static int cadence_spi_probe(struct udevice *bus)
194 {
195 struct cadence_spi_plat *plat = dev_get_plat(bus);
196 struct cadence_spi_priv *priv = dev_get_priv(bus);
197 struct clk clk;
198 int ret;
199
200 priv->regbase = plat->regbase;
201 priv->ahbbase = plat->ahbbase;
202 priv->is_dma = plat->is_dma;
203 priv->is_decoded_cs = plat->is_decoded_cs;
204 priv->fifo_depth = plat->fifo_depth;
205 priv->fifo_width = plat->fifo_width;
206 priv->trigger_address = plat->trigger_address;
207 priv->read_delay = plat->read_delay;
208 priv->ahbsize = plat->ahbsize;
209 priv->max_hz = plat->max_hz;
210
211 priv->page_size = plat->page_size;
212 priv->block_size = plat->block_size;
213 priv->tshsl_ns = plat->tshsl_ns;
214 priv->tsd2d_ns = plat->tsd2d_ns;
215 priv->tchsh_ns = plat->tchsh_ns;
216 priv->tslch_ns = plat->tslch_ns;
217
218 if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE))
219 xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI,
220 ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS,
221 ZYNQMP_PM_REQUEST_ACK_NO, NULL);
222
223 if (priv->ref_clk_hz == 0) {
224 ret = clk_get_by_index(bus, 0, &clk);
225 if (ret) {
226 #ifdef CONFIG_HAS_CQSPI_REF_CLK
227 priv->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
228 #elif defined(CONFIG_ARCH_SOCFPGA)
229 priv->ref_clk_hz = cm_get_qspi_controller_clk_hz();
230 #else
231 return ret;
232 #endif
233 } else {
234 priv->ref_clk_hz = clk_get_rate(&clk);
235 clk_free(&clk);
236 if (IS_ERR_VALUE(priv->ref_clk_hz))
237 return priv->ref_clk_hz;
238 }
239 }
240
241 priv->resets = devm_reset_bulk_get_optional(bus);
242 if (priv->resets)
243 reset_deassert_bulk(priv->resets);
244
245 if (!priv->qspi_is_init) {
246 cadence_qspi_apb_controller_init(priv);
247 priv->qspi_is_init = 1;
248 }
249
250 priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
251
252 if (IS_ENABLED(CONFIG_ARCH_VERSAL)) {
253 /* Versal platform uses spi calibration to set read delay */
254 if (priv->read_delay >= 0)
255 priv->read_delay = -1;
256 /* Reset ospi flash device */
257 ret = cadence_qspi_versal_flash_reset(bus);
258 if (ret)
259 return ret;
260 }
261
262 return 0;
263 }
264
cadence_spi_remove(struct udevice * dev)265 static int cadence_spi_remove(struct udevice *dev)
266 {
267 struct cadence_spi_priv *priv = dev_get_priv(dev);
268 int ret = 0;
269
270 if (priv->resets)
271 ret = reset_release_bulk(priv->resets);
272
273 return ret;
274 }
275
cadence_spi_set_mode(struct udevice * bus,uint mode)276 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
277 {
278 struct cadence_spi_priv *priv = dev_get_priv(bus);
279
280 /* Disable QSPI */
281 cadence_qspi_apb_controller_disable(priv->regbase);
282
283 /* Set SPI mode */
284 cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
285
286 /* Enable Direct Access Controller */
287 if (priv->use_dac_mode)
288 cadence_qspi_apb_dac_mode_enable(priv->regbase);
289
290 /* Enable QSPI */
291 cadence_qspi_apb_controller_enable(priv->regbase);
292
293 return 0;
294 }
295
cadence_spi_mem_exec_op(struct spi_slave * spi,const struct spi_mem_op * op)296 static int cadence_spi_mem_exec_op(struct spi_slave *spi,
297 const struct spi_mem_op *op)
298 {
299 struct udevice *bus = spi->dev->parent;
300 struct cadence_spi_priv *priv = dev_get_priv(bus);
301 void *base = priv->regbase;
302 int err = 0;
303 u32 mode;
304
305 /* Set Chip select */
306 cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
307 priv->is_decoded_cs);
308
309 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
310 /*
311 * Performing reads in DAC mode forces to read minimum 4 bytes
312 * which is unsupported on some flash devices during register
313 * reads, prefer STIG mode for such small reads.
314 */
315 if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
316 mode = CQSPI_STIG_READ;
317 else
318 mode = CQSPI_READ;
319 } else {
320 if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
321 mode = CQSPI_STIG_WRITE;
322 else
323 mode = CQSPI_WRITE;
324 }
325
326 switch (mode) {
327 case CQSPI_STIG_READ:
328 err = cadence_qspi_apb_command_read_setup(priv, op);
329 if (!err)
330 err = cadence_qspi_apb_command_read(priv, op);
331 break;
332 case CQSPI_STIG_WRITE:
333 err = cadence_qspi_apb_command_write_setup(priv, op);
334 if (!err)
335 err = cadence_qspi_apb_command_write(priv, op);
336 break;
337 case CQSPI_READ:
338 err = cadence_qspi_apb_read_setup(priv, op);
339 if (!err) {
340 if (priv->is_dma)
341 err = cadence_qspi_apb_dma_read(priv, op);
342 else
343 err = cadence_qspi_apb_read_execute(priv, op);
344 }
345 break;
346 case CQSPI_WRITE:
347 err = cadence_qspi_apb_write_setup(priv, op);
348 if (!err)
349 err = cadence_qspi_apb_write_execute(priv, op);
350 break;
351 default:
352 err = -1;
353 break;
354 }
355
356 return err;
357 }
358
cadence_spi_mem_supports_op(struct spi_slave * slave,const struct spi_mem_op * op)359 static bool cadence_spi_mem_supports_op(struct spi_slave *slave,
360 const struct spi_mem_op *op)
361 {
362 bool all_true, all_false;
363
364 /*
365 * op->dummy.dtr is required for converting nbytes into ncycles.
366 * Also, don't check the dtr field of the op phase having zero nbytes.
367 */
368 all_true = op->cmd.dtr &&
369 (!op->addr.nbytes || op->addr.dtr) &&
370 (!op->dummy.nbytes || op->dummy.dtr) &&
371 (!op->data.nbytes || op->data.dtr);
372
373 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
374 !op->data.dtr;
375
376 /* Mixed DTR modes not supported. */
377 if (!(all_true || all_false))
378 return false;
379
380 if (all_true)
381 return spi_mem_dtr_supports_op(slave, op);
382 else
383 return spi_mem_default_supports_op(slave, op);
384 }
385
cadence_spi_of_to_plat(struct udevice * bus)386 static int cadence_spi_of_to_plat(struct udevice *bus)
387 {
388 struct cadence_spi_plat *plat = dev_get_plat(bus);
389 struct cadence_spi_priv *priv = dev_get_priv(bus);
390 ofnode subnode;
391
392 plat->regbase = devfdt_get_addr_index_ptr(bus, 0);
393 plat->ahbbase = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahbsize);
394 plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
395 plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
396 plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
397 plat->trigger_address = dev_read_u32_default(bus,
398 "cdns,trigger-address",
399 0);
400 /* Use DAC mode only when MMIO window is at least 8M wide */
401 if (plat->ahbsize >= SZ_8M)
402 priv->use_dac_mode = true;
403
404 plat->is_dma = dev_read_bool(bus, "cdns,is-dma");
405
406 /* All other parameters are embedded in the child node */
407 subnode = dev_read_first_subnode(bus);
408 if (!ofnode_valid(subnode)) {
409 printf("Error: subnode with SPI flash config missing!\n");
410 return -ENODEV;
411 }
412
413 /* Use 500 KHz as a suitable default */
414 plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
415 500000);
416
417 /* Read other parameters from DT */
418 plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
419 plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
420 plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
421 200);
422 plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
423 255);
424 plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
425 plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
426 /*
427 * Read delay should be an unsigned value but we use a signed integer
428 * so that negative values can indicate that the device tree did not
429 * specify any signed values and we need to perform the calibration
430 * sequence to find it out.
431 */
432 plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay",
433 -1);
434
435 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
436 __func__, plat->regbase, plat->ahbbase, plat->max_hz,
437 plat->page_size);
438
439 return 0;
440 }
441
442 static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
443 .exec_op = cadence_spi_mem_exec_op,
444 .supports_op = cadence_spi_mem_supports_op,
445 };
446
447 static const struct dm_spi_ops cadence_spi_ops = {
448 .set_speed = cadence_spi_set_speed,
449 .set_mode = cadence_spi_set_mode,
450 .mem_ops = &cadence_spi_mem_ops,
451 /*
452 * cs_info is not needed, since we require all chip selects to be
453 * in the device tree explicitly
454 */
455 };
456
457 static const struct udevice_id cadence_spi_ids[] = {
458 { .compatible = "cdns,qspi-nor" },
459 { .compatible = "ti,am654-ospi" },
460 { }
461 };
462
463 U_BOOT_DRIVER(cadence_spi) = {
464 .name = "cadence_spi",
465 .id = UCLASS_SPI,
466 .of_match = cadence_spi_ids,
467 .ops = &cadence_spi_ops,
468 .of_to_plat = cadence_spi_of_to_plat,
469 .plat_auto = sizeof(struct cadence_spi_plat),
470 .priv_auto = sizeof(struct cadence_spi_priv),
471 .probe = cadence_spi_probe,
472 .remove = cadence_spi_remove,
473 .flags = DM_FLAG_OS_PREPARE,
474 };
475