1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SH QSPI (Quad SPI) driver
4 *
5 * Copyright (C) 2013 Renesas Electronics Corporation
6 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 */
8
9 #define LOG_CATEGORY UCLASS_SPI
10
11 #include <common.h>
12 #include <console.h>
13 #include <malloc.h>
14 #include <spi.h>
15 #include <wait_bit.h>
16 #include <asm/arch/rmobile.h>
17 #include <asm/io.h>
18 #include <linux/bitops.h>
19
20 /* SH QSPI register bit masks <REG>_<BIT> */
21 #define SPCR_MSTR 0x08
22 #define SPCR_SPE 0x40
23 #define SPSR_SPRFF 0x80
24 #define SPSR_SPTEF 0x20
25 #define SPPCR_IO3FV 0x04
26 #define SPPCR_IO2FV 0x02
27 #define SPPCR_IO1FV 0x01
28 #define SPBDCR_RXBC0 BIT(0)
29 #define SPCMD_SCKDEN BIT(15)
30 #define SPCMD_SLNDEN BIT(14)
31 #define SPCMD_SPNDEN BIT(13)
32 #define SPCMD_SSLKP BIT(7)
33 #define SPCMD_BRDV0 BIT(2)
34 #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
35 SPCMD_SPNDEN | SPCMD_SSLKP | \
36 SPCMD_BRDV0
37 #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
38 SPCMD_BRDV0
39 #define SPBFCR_TXRST BIT(7)
40 #define SPBFCR_RXRST BIT(6)
41 #define SPBFCR_TXTRG 0x30
42 #define SPBFCR_RXTRG 0x07
43
44 /* SH QSPI register set */
45 struct sh_qspi_regs {
46 u8 spcr;
47 u8 sslp;
48 u8 sppcr;
49 u8 spsr;
50 u32 spdr;
51 u8 spscr;
52 u8 spssr;
53 u8 spbr;
54 u8 spdcr;
55 u8 spckd;
56 u8 sslnd;
57 u8 spnd;
58 u8 dummy0;
59 u16 spcmd0;
60 u16 spcmd1;
61 u16 spcmd2;
62 u16 spcmd3;
63 u8 spbfcr;
64 u8 dummy1;
65 u16 spbdcr;
66 u32 spbmul0;
67 u32 spbmul1;
68 u32 spbmul2;
69 u32 spbmul3;
70 };
71
72 struct sh_qspi_slave {
73 #if !CONFIG_IS_ENABLED(DM_SPI)
74 struct spi_slave slave;
75 #endif
76 struct sh_qspi_regs *regs;
77 };
78
sh_qspi_init(struct sh_qspi_slave * ss)79 static void sh_qspi_init(struct sh_qspi_slave *ss)
80 {
81 /* QSPI initialize */
82 /* Set master mode only */
83 writeb(SPCR_MSTR, &ss->regs->spcr);
84
85 /* Set SSL signal level */
86 writeb(0x00, &ss->regs->sslp);
87
88 /* Set MOSI signal value when transfer is in idle state */
89 writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
90
91 /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
92 writeb(0x01, &ss->regs->spbr);
93
94 /* Disable Dummy Data Transmission */
95 writeb(0x00, &ss->regs->spdcr);
96
97 /* Set clock delay value */
98 writeb(0x00, &ss->regs->spckd);
99
100 /* Set SSL negation delay value */
101 writeb(0x00, &ss->regs->sslnd);
102
103 /* Set next-access delay value */
104 writeb(0x00, &ss->regs->spnd);
105
106 /* Set equence command */
107 writew(SPCMD_INIT2, &ss->regs->spcmd0);
108
109 /* Reset transfer and receive Buffer */
110 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
111
112 /* Clear transfer and receive Buffer control bit */
113 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
114
115 /* Set equence control method. Use equence0 only */
116 writeb(0x00, &ss->regs->spscr);
117
118 /* Enable SPI function */
119 setbits_8(&ss->regs->spcr, SPCR_SPE);
120 }
121
sh_qspi_cs_activate(struct sh_qspi_slave * ss)122 static void sh_qspi_cs_activate(struct sh_qspi_slave *ss)
123 {
124 /* Set master mode only */
125 writeb(SPCR_MSTR, &ss->regs->spcr);
126
127 /* Set command */
128 writew(SPCMD_INIT1, &ss->regs->spcmd0);
129
130 /* Reset transfer and receive Buffer */
131 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
132
133 /* Clear transfer and receive Buffer control bit */
134 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
135
136 /* Set equence control method. Use equence0 only */
137 writeb(0x00, &ss->regs->spscr);
138
139 /* Enable SPI function */
140 setbits_8(&ss->regs->spcr, SPCR_SPE);
141 }
142
sh_qspi_cs_deactivate(struct sh_qspi_slave * ss)143 static void sh_qspi_cs_deactivate(struct sh_qspi_slave *ss)
144 {
145 /* Disable SPI Function */
146 clrbits_8(&ss->regs->spcr, SPCR_SPE);
147 }
148
sh_qspi_xfer_common(struct sh_qspi_slave * ss,unsigned int bitlen,const void * dout,void * din,unsigned long flags)149 static int sh_qspi_xfer_common(struct sh_qspi_slave *ss, unsigned int bitlen,
150 const void *dout, void *din, unsigned long flags)
151 {
152 u32 nbyte, chunk;
153 int i, ret = 0;
154 u8 dtdata = 0, drdata;
155 u8 *tdata = &dtdata, *rdata = &drdata;
156 u32 *spbmul0 = &ss->regs->spbmul0;
157
158 if (dout == NULL && din == NULL) {
159 if (flags & SPI_XFER_END)
160 sh_qspi_cs_deactivate(ss);
161 return 0;
162 }
163
164 if (bitlen % 8) {
165 log_warning("bitlen is not 8bit aligned %d", bitlen);
166 return 1;
167 }
168
169 nbyte = bitlen / 8;
170
171 if (flags & SPI_XFER_BEGIN) {
172 sh_qspi_cs_activate(ss);
173
174 /* Set 1048576 byte */
175 writel(0x100000, spbmul0);
176 }
177
178 if (flags & SPI_XFER_END)
179 writel(nbyte, spbmul0);
180
181 if (dout != NULL)
182 tdata = (u8 *)dout;
183
184 if (din != NULL)
185 rdata = din;
186
187 while (nbyte > 0) {
188 /*
189 * Check if there is 32 Byte chunk and if there is, transfer
190 * it in one burst, otherwise transfer on byte-by-byte basis.
191 */
192 chunk = (nbyte >= 32) ? 32 : 1;
193
194 clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG | SPBFCR_RXTRG,
195 chunk == 32 ? SPBFCR_TXTRG | SPBFCR_RXTRG : 0);
196
197 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF,
198 true, 1000, true);
199 if (ret)
200 return ret;
201
202 for (i = 0; i < chunk; i++) {
203 writeb(*tdata, &ss->regs->spdr);
204 if (dout != NULL)
205 tdata++;
206 }
207
208 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF,
209 true, 1000, true);
210 if (ret)
211 return ret;
212
213 for (i = 0; i < chunk; i++) {
214 *rdata = readb(&ss->regs->spdr);
215 if (din != NULL)
216 rdata++;
217 }
218
219 nbyte -= chunk;
220 }
221
222 if (flags & SPI_XFER_END)
223 sh_qspi_cs_deactivate(ss);
224
225 return ret;
226 }
227
228 #if !CONFIG_IS_ENABLED(DM_SPI)
to_sh_qspi(struct spi_slave * slave)229 static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
230 {
231 return container_of(slave, struct sh_qspi_slave, slave);
232 }
233
spi_cs_is_valid(unsigned int bus,unsigned int cs)234 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
235 {
236 return 1;
237 }
238
spi_cs_activate(struct spi_slave * slave)239 void spi_cs_activate(struct spi_slave *slave)
240 {
241 struct sh_qspi_slave *ss = to_sh_qspi(slave);
242
243 sh_qspi_cs_activate(ss);
244 }
245
spi_cs_deactivate(struct spi_slave * slave)246 void spi_cs_deactivate(struct spi_slave *slave)
247 {
248 struct sh_qspi_slave *ss = to_sh_qspi(slave);
249
250 sh_qspi_cs_deactivate(ss);
251 }
252
spi_setup_slave(unsigned int bus,unsigned int cs,unsigned int max_hz,unsigned int mode)253 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
254 unsigned int max_hz, unsigned int mode)
255 {
256 struct sh_qspi_slave *ss;
257
258 if (!spi_cs_is_valid(bus, cs))
259 return NULL;
260
261 ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs);
262 if (!ss) {
263 printf("SPI_error: Fail to allocate sh_qspi_slave\n");
264 return NULL;
265 }
266
267 ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
268
269 /* Init SH QSPI */
270 sh_qspi_init(ss);
271
272 return &ss->slave;
273 }
274
spi_free_slave(struct spi_slave * slave)275 void spi_free_slave(struct spi_slave *slave)
276 {
277 struct sh_qspi_slave *spi = to_sh_qspi(slave);
278
279 free(spi);
280 }
281
spi_claim_bus(struct spi_slave * slave)282 int spi_claim_bus(struct spi_slave *slave)
283 {
284 return 0;
285 }
286
spi_release_bus(struct spi_slave * slave)287 void spi_release_bus(struct spi_slave *slave)
288 {
289 }
290
spi_xfer(struct spi_slave * slave,unsigned int bitlen,const void * dout,void * din,unsigned long flags)291 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
292 const void *dout, void *din, unsigned long flags)
293 {
294 struct sh_qspi_slave *ss = to_sh_qspi(slave);
295
296 return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
297 }
298
299 #else
300
301 #include <dm.h>
302
sh_qspi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)303 static int sh_qspi_xfer(struct udevice *dev, unsigned int bitlen,
304 const void *dout, void *din, unsigned long flags)
305 {
306 struct udevice *bus = dev->parent;
307 struct sh_qspi_slave *ss = dev_get_plat(bus);
308
309 return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
310 }
311
sh_qspi_set_speed(struct udevice * dev,uint speed)312 static int sh_qspi_set_speed(struct udevice *dev, uint speed)
313 {
314 /* This is a SPI NOR controller, do nothing. */
315 return 0;
316 }
317
sh_qspi_set_mode(struct udevice * dev,uint mode)318 static int sh_qspi_set_mode(struct udevice *dev, uint mode)
319 {
320 /* This is a SPI NOR controller, do nothing. */
321 return 0;
322 }
323
sh_qspi_probe(struct udevice * dev)324 static int sh_qspi_probe(struct udevice *dev)
325 {
326 struct sh_qspi_slave *ss = dev_get_plat(dev);
327
328 sh_qspi_init(ss);
329
330 return 0;
331 }
332
sh_qspi_of_to_plat(struct udevice * dev)333 static int sh_qspi_of_to_plat(struct udevice *dev)
334 {
335 struct sh_qspi_slave *plat = dev_get_plat(dev);
336
337 plat->regs = dev_read_addr_ptr(dev);
338
339 return 0;
340 }
341
342 static const struct dm_spi_ops sh_qspi_ops = {
343 .xfer = sh_qspi_xfer,
344 .set_speed = sh_qspi_set_speed,
345 .set_mode = sh_qspi_set_mode,
346 };
347
348 static const struct udevice_id sh_qspi_ids[] = {
349 { .compatible = "renesas,qspi" },
350 { }
351 };
352
353 U_BOOT_DRIVER(sh_qspi) = {
354 .name = "sh_qspi",
355 .id = UCLASS_SPI,
356 .of_match = sh_qspi_ids,
357 .ops = &sh_qspi_ops,
358 .of_to_plat = sh_qspi_of_to_plat,
359 .plat_auto = sizeof(struct sh_qspi_slave),
360 .probe = sh_qspi_probe,
361 };
362 #endif
363